CN86203364U - Simple logic circuit type multichannel programmable time controllor - Google Patents

Abstract

The utility model discloses a simple logic circuit type multichannel programmable time controller, comprising a controlled frequency dividing circuit (1), a time counter (2), a decoding and driving circuit (3), a time display (4), a static storage array (5), a state setting circuit (6), and a load control circuit (7). The utility model can realize sequence control of multiplex, multiplicating on-off action with minimal time period which is more than one minute. The utility model, which has the advantages of simple route, low cost, small size, and wide ranges of application, is very suitable for household appliances or other appliances and is wide in field of application after being integrated.

Description

Simple logic circuit type multichannel programmable time controllor

The utility model relates to a kind of logical circuit formula multichannel programmable time controller.

Existing logical circuit formula time controller or can not compile, change program easily, perhaps can not be directly installed on family expenses and other electrical equipment and be applied in industrial field boundary less demanding, that take the automatic control of preface and close, limit further promoteing the wider application of sequential automatic control technology.

Logic block-diagram of the present utility model as shown in Figure 1.(1) is controlled frequency dividing circuit among Fig. 1, and it generally has three kinds of frequency divisions, respectively when normally walking, the usefulness of F.F., slow-motion, which kind of frequency division circuit exports, and several is arranged by key control.(2) be time counter.(3) be decoding, driving circuit.(4) be time display.(5) Shi Static attitudes storage array.(6) be state setting circuit.(7) be load control circuit.(8) be delay circuit.(9) be the input signal of certain frequency.

Time counter (2) is answered available manual zero clearing, and its each output terminal is connected with the address end of Static attitude storage array (5) with each input end of decoder driver circuit (3) respectively.The address signal of Static attitude storage array (5) also can be drawn from the output terminal of decoding, driving circuit (3), as shown in phantom in Figure 1.(5) WE end is when programming state, be connected with the output terminal of controlled frequency dividing circuit (1), with the output signal of (1) as write control signal (when the address signal when the output terminal of (3) is drawn, write control signal is drawn from a branch position g section output terminal of (3)).Delay circuit (8) makes the just input after the address signal of (5) changes of WE control signal, and its effect is to prevent that address signal from also not stablizing mistiming write state signal.Time display (4) can be light-emitting diodes tube panel or LCDs etc.State setting circuit (6) is made up of several triggers or bistable circuit, and each trigger or bistable circuit have common reset button and independent set button, can be provided with the diode displaying flip-flop states on the circuit.(7) be load control circuit, can form, also can follow relay in conjunction with forming by current amplifier by several current amplifiers, can also be by triode as switch, the circuit of control controllable silicon phase shift regulating circuit is formed, and realizes multichannel control.An I/O mouth of Static attitude storage array is corresponding to connect a road of a trigger and load control circuit, and enables a plurality of I/O, sets up relative trigger device and load control circuit, just can realize multicircuit time control.The civil power that input signal (9) can be introduced 50HZ or 60HZ produces through High frequency filter, shaping, also can be produced by oscillation frequency dividing circuit (10), shown in Fig. 1 frame of broken lines.

When the system of each counter of the crossover frequency of controlled frequency dividing circuit (1), time counter (2) and when the mode that the output terminal of (2) or (3) is drawn address signal changes, can obtain the different all kinds of time controllers of minimum time section.

(1) of the present utility model, (2), (3), (5), (6), (7) and (8) circuit can be integrated on a slice chip, become the special IC product.If any oscillation frequency dividing circuit (10), also Ke Yi And is integrated.

The utility model can realize that cycle period is 24 hours, and the minimum time section is that the sequential of the repeatedly repeat switch action more than 1 minute is controlled automatically, or realizes that cycle period is shorter, and the minimum time section is that the sequential of Millisecond is controlled automatically.The utility model circuit is simple, cheap, volume is little, is particularly suitable as the time controller on family expenses and other electrical equipment, integrated after, then accommodation is wider, helps promoteing the wider application of control time in program design device.

Embodiment:

Embodiment 1 as shown in Figure 2, oscillation frequency dividing circuit (10) is selected commercially available integrated package MM5369 and supporting quartz resonator for use, the square wave of this circuit output 60HZ.(11) be commercially available LM8361(AM11998A, MM5387 etc. also can) the digital electronic clock integrated package, it has comprised the circuit of (1) among Fig. 1, (2), (3) three parts.(11) part pin name is as shown in table 1.(4) select for use and (11) supporting light-emitting diodes tube panel FR1094-11T(or LT667D etc.).The function of button AN1, AN2, AN3 be respectively make display screen put 12:00 initial point (zero clearing), when 2 minutes/second being careful and when hurrying up in 60 minutes/second.(11) maximum is shown as 11:59 or 23:59.(5) select the CD2114 chip of 1K * 4 for use, this routine address wire from Fig. 1 circuit (3) output terminal promptly the pin of (11) draw, A0～A9 is connected with pin 1,2,3,4,5,6,9,10,12,14 in turn.

Table one

By finding out in the table 1, address code of per 10 minutes Bian Change is so this routine minimum time section is 10 minutes.

K switch 1 is in order to the state of operation circuit, K1-1, K1-2 interlock.When K1 puts a shelves, be programming state, K1-1 is connected the pin of (11) (promptly dividing a g section control line of position) with the WE end of (5), introducing write control signal, its waveform as shown in Figure 3, delay circuit (8) is used the RC circuit.K1-2 causes high level the base stage of pin 31 and BG2.Time during for actual walk that do not change that clock shows when the programming state, utilized the time of fire alarming of LM8361 to show here, at this moment, walk hour counter and be blocked, display screen shows the programming time.The situation of the single channel of only having drawn among Fig. 2 control, this moment, BG2 was saturated, no matter the BG1 base stage has not electric current input, controllable silicon equal triggerless electric current and ending.Programming step is as follows:

1. use key AN4 with trigger reset (R input high level, Q are output as " 0 ");

2. by AN1 display screen is put initial point " 12:00 ";

3. walk to load opening time first by fast, slow-motion key AN3, AN2, general all make branchs individual be 0,1 or the WE of 7(CD2114 write during for low level), press key AN5, I/O writes " 1 " (D input high level, Q are output as " 1 ");

4. walk to the unused time by button AN2, AN3, click key AN4, I/O writes " 0 ".

Need multiple switching as load, repeat above step 3., 4., at last the internal memory that allows excess time in inswept 24 hours of the address with key AN2, AN3.

When K1 beats to the b shelves, K1-1 makes WE be connected to high level, (5) for reading state, K1-2 is identical with situation when a shelves, at this moment circuit disengaging programming state place examines shelves soon, can verify the situation of programming fast by button AN2, AN3, also be convenient to rewrite at any time arbitrary section contents of program in addition.

When K1 beats the shelves to C, (5) are still the state of reading, and K1-2 puts electronegative potential with pin 31 and BG2 base stage, walk hour counter and open this moment, and time when display screen shows to walk, BG2 ends in addition, the signal controlling that the controllable silicon duty of circuit (7) is read by the I/O mouth, circuit place programmed state.When I/O mouth output " 0 ", BG1 ends, and controllable silicon SCR 1 is ended, when I/O mouth output " 1 ", BG1 conducting, SCR1 conducting, load starting.

This example can be provided with the several load control circuit as required.When enabling two-way simultaneously when above, write-in program simultaneously.

Embodiment 2 as shown in Figure 4.(11), (4), (5) and connection thereof and example 1 are just the same in this example, be with the key distinction of example 1: being connected with example 1 of the Q end of (6) is same, the Q end is connected with the BG1 of (7) with a diode by one resistance, the R end is connected to the I/O2 of (5) by a diode, electric capacity and K switch 2, K2 is " disposable control " and " cycle control " selector switch, when K2 puts " disposable control " shelves a, during programmed state after program control action is finished in load, I/O2 exports high level, make the set of Q end, BG ₁Conducting, bidirectional trigger diode ST closes, and load breaks away from programmed state, works as K ₂Place " cycle control " shelves during b, programmed state is located in load always, but every day repetitive routine content.

What (9) of this example were input to (11) is the mains frequency of 50HZ, delay circuit (8) adopts the RC circuit, when beating to a shelves and K2, beats K1 to " disposable control " (a) during shelves, the WE signal is introduced, and pin 31 place's high level are under this state, the BG1 of circuit (7) is saturated, ST does not trigger, and the controllable silicon SCR of circuit (7) is ended, circuit place programming state.Programming step and example 1 1., 2., 3., 4. with.In the I/O1 write-in program, I/O2 has also write low level simultaneously.When K1 beats the shelves to b, I/O ₂The instantaneous high level that writes, afterwards, WE goes back to high level, and pin 31 is a low level, and the BG1 base stage is by I/O ₁Control (when Q is low level), circuit place programmed state is when last shutdown action, I/O are finished in load ₂Export a high level, make trigger Q set, BG1 is pinned, circuit (7) no longer is subjected to I/O ₁That control, circuit break away from is program control (also can be program control by pressing AN4 (7) being broken away from when program control, can recover program control again by AN5 again).If K2 places " cycle control " shelves (b shelves), then circuit is in programmed state always, and every day, circulation repeated program control content.When K1 beats the shelves to C, the BG1 remain off, load becomes " manually " control.

In addition, the resistance of the potentiometer (W) of regulating load control circuit (7) can make the conduction angle of controllable silicon when conducting change, thus the voltage of regulating load.When this product is used on the electric fan,, then can realize natural wind simulating control, as shown in Figure 5 at the triode of (W) two ends parallel connection one by oscillator (12) control; If other I/O mouth such as I/O by storage array (5) in parallel ₃, I/O ₄The D/A switch circuit (13) (as shown in Figure 6) of internal memory signal controlling, then can realize the programmed control of fan wind speed, become a kind of novel electric fan of superior performance.This novel fan also can utilize the warning circuit of LM8361 to increase additional functions such as locking.

Claims (10)

1, a kind of logical circuit formula multichannel programmable time controller is characterized in that being made up of controlled frequency dividing circuit (1), time counter (2), decoding, driving circuit (3), time display (4), static storage array (5), state setting circuit (6), load control circuit (7).

2, time controller according to claim 1 is characterized in that the address wire of static storage array (5) is connected with the output terminal of time counter (2) or the output terminal of decoder driver circuit (3).

3, time controller according to claim 2, it is characterized in that static storage array (5) when programming the WE end by delay circuit (8) and controlled frequency dividing circuit (1) output terminal or the control display screen of decoding, driving circuit (3) divide an output terminal of a g section to be connected.

4,, it is characterized in that state setting circuit (6) is made up of one or more bistable circuits or trigger according to claim 1 or 3 described time controllers.

5, time controller according to claim 1, it is characterized in that load control circuit (7) can be made up of several current amplifiers, also can form by current amplifier and relay, also can be by triode as switch, the circuit of control controllable silicon phase shift regulating circuit is formed.

6, time controller according to claim 4, it is characterized in that load control circuit (7) can be made up of several current amplifiers, also can form by current amplifier and relay, also can be by triode as switch, the circuit of control controllable silicon phase shift regulating circuit is formed.

7, according to claim 1 or 6 described time controllers, trigger of the I/O mouth that it is characterized in that static storage array (5) and state setting circuit (6) and one road input end of load control circuit (7) are connected.

8, according to claim 1 or 7 described time controllers, an I/O mouth that it is characterized in that static storage array (5) is connected with the R end of a trigger of state setting circuit (6) through a diode, electric capacity, and this trigger Q end is connected with one road input end of load control circuit (7) through a diode, resistance.

9, according to claim 5 or 6 described time controllers, it is characterized in that can be at triode by oscillator (12) control of potentiometer (W) two ends of load control circuit (7) parallel connection.

10, according to claim 5 or 6 described time controllers, it is characterized in that can be at above-mentioned potentiometer (W) two ends D/A switch circuit (13) in parallel, and each triode of (13) is connected with a static I/O who stores array (5) by resistance.

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