CN85103577A - The Play System of memory disc - Google Patents

The Play System of memory disc Download PDF

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Publication number
CN85103577A
CN85103577A CN85103577.9A CN85103577A CN85103577A CN 85103577 A CN85103577 A CN 85103577A CN 85103577 A CN85103577 A CN 85103577A CN 85103577 A CN85103577 A CN 85103577A
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China
Prior art keywords
data
dish
numerical data
auxiliary
signal
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Expired - Lifetime
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CN85103577.9A
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Chinese (zh)
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CN1010624B (en
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古谷恒雄
古川俊介
堀克弥
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Sony Corp
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Sony Corp
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Priority to CN 85103577 priority Critical patent/CN1010624B/en
Publication of CN85103577A publication Critical patent/CN85103577A/en
Publication of CN1010624B publication Critical patent/CN1010624B/en
Expired legal-status Critical Current

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Abstract

The invention of this part relates to a kind of Play System of fine groove dish, and this system comprises: a) according to the dish regenerated signal, produce with data cell synchronous write the time target device; B) target device in the time of producing the reading of constant frequency; C) memory buffer, from dish more from birth main numerical data and the auxiliary figure data all by writing the synchronous mode of markers that writes that the markers generation device comes and write this memory buffer with said, and read main numerical data and auxiliary figure data by the mode synchronous with reading markers from this memory buffer; And d) on the auxiliary figure data basis that memory buffer is read, the device of main numerical data play position in the search dish.

Description

The Play System of memory disc
This part invention is related to a kind of system that plays numerical data from the dish of prerecording.
Optical digital sound equipment dish (also being called fine groove dish CD) system can play out high-quality stereo music.In this fine groove disc system, if the structure to dish is not done big change and can be play the numerical data different with music, the for example alphanumeric data of books literal, graphic display data or computer program data, and add one tunnel music at least again, just can constitute a complete visual information Play System as long as acquire display unit so, for example can play figure, statistical form, still image and (perhaps) video game.This has just expanded the range of application of fine groove disc system.In addition, the memory space of fine groove dish is about the 500M byte at present, and is more much bigger than common floppy disk.
On the other hand, in common fine groove dish, data storage cell is relatively said long, for example can deposit whole melody or wherein one section therein in, because the fine groove dish was to play the acoustic signal design originally.Use if general data-carrier store is used as by this system, just need to the unit of 10K byte, go reading of data in accurate for example 128 bytes.
In addition, when playing back music, the tracking accuracy of title is less demanding, can not cause the influence that can note to the sound of playing.This is because the main channel sound data of telling from the dish regenerated signal is all write in the memory buffer, through correction process, has so just eliminated the phase fluctuation (signal is beated) on any time axle in the data.Yet, as mentioned above, because subcode signal does not need high-precision title to follow the tracks of, so in order to reduce manufacturing cost, fine groove disc system itself is the phase fluctuation (beating) on the timing countershaft not.Therefore, use a problem will take place if data-carrier store is used as by this system, this system can not only rely on subcode signal to determine exactly the address of reading on the placing.
The problems referred to above have been known, fundamental purpose of the present invention just provides a kind of dial system that is used for the broadcast dish that can obtain on market, it can be used to reading word signal, for example replaces digital audio signal, can read computer program and data with it.
Another object of the present invention provides a kind of low-cost dish Play System, wherein has a memory buffer to be used to intersection reducing action to the main channel numerical data.
The present invention also has a purpose to provide a kind of Play System of dish, only need add a circuit simply, does not need to change the playback process circuit of common fine groove dish, just can visit the main channel digital signal.
In order to achieve the above object, this system comprises: a) can produce and the synchronous device that writes clock of data cell from the dish regenerated signal; B) can produce the device of the readout clock of constant frequency; C) memory buffer, from dish more from birth main numerical data and the auxiliary figure data all by writing in this memory buffer with the mode that writes the clock synchronised that writes clock generating device, and from the buffering storer by reading main numerical data with the mode of readout clock synchronised; And d) make this dish seek the device of main numerical data play position according to the auxiliary figure data that go out from the buffering memory read.Above-mentioned memory buffer can comprise a FIFO(first in first out that separates) buffer register.
Can finish the effect of disk storage according to broadcast disc system of the present invention, but memory space is more much bigger than common floppy disk, and can comes the reading number data with the unit one by one that is suitable for handling.
In addition, system of the present invention can also write down the numerical data different with stereophonic music signal, these numerical datas adopt the signal format of the signal processing model and the record data form of for example error correction, enable with market on the fine groove disc system compatibility that is used to play stereo music of selling.And because system of the present invention has adopted one to intersect reduction RAM in order to correct the subcode signal on the time shaft, the similar all playback process circuit of fine groove dish usually all can utilize, and therefore can make the low system architecture of cost.
In addition, system of the present invention only need add an external circuit simply, does not need to change the playback process circuit of common fine groove dish, just can visit the digital signal of main channel.
The cutline of accompanying drawing
Can more completely understand this part invention from above explanation referring again to accompanying drawing.
Fig. 1 and 2 is recorded in data structure on the fine groove dish;
Fig. 3 is a numerical data that is write down in first embodiment;
Fig. 4 is the simplified block diagram that is used for producing a writing circuit of the signal that will be recorded on the dish;
Fig. 5 is the simplified block diagram of first embodiment of playing circuit, just is sent to this playing circuit from the born again signal of dish;
Fig. 6 is the figure of numerical data, is used for illustrating rising and falling proofreading and correct and the intersection reduction process;
Fig. 7 A to 7E is used for illustrating the sequential chart that rises and falls and proofread and correct and intersect reduction process;
Fig. 8 is the simplified block diagram of another example of buffer circuit;
Fig. 9 is the block scheme of the total of second embodiment of the invention;
Figure 10 is the form of tandem data word among second embodiment.
For the ease of understanding this part invention, can be with reference to accompanying drawing.
Fig. 1 represents to be recorded in a data stream on the fine groove dish.
One frame data contain 588 record data.Every frame data begin with 24 frame-synchronizing impulse FS that line up special shape.3 present data of frame-synchronizing impulse FS heel recover to suppress sign indicating number RB, are 0 to 32 data bit string DB then, and each serial data comprises that 14 add 3 present data recovery inhibition sign indicating number RB, and they are arranged one by one.The first data bits DB(0) is called subcode signal or user code, is used to refer to the Play Control state of data and other for information about.Data bits DB(1) to DB(12) and DB(17) to DB(28) all be assigned to main channel sound data, remaining DB(13) to DB(16) and DB(29) to DB(32) the designated parity data that is used for to the main channel error correction.It should be noted that each 14 bit data bit string DB utilizes 8 to 14 modulation (EFM) technology to become 14 bit data after process is intersected when writing down by 8 bit data again.
The EFM method is a kind of an octet to be transformed into the method for 14 more favourable spread patterns, and it can prolong the minimum conversion time of modulation signal and suppress their low frequency component.
Fig. 2 is born again data, and wherein each 14 bit data bit string DB is demodulated to corresponding 8 bit data bytes with 14 to 8 demodulation techniques, and data recovery at present suppresses the position to be removed, and it comprises 98 frames that deducted check code in succession.Subcode signal comprises 8 bit data altogether, and label is P to W.The subcode signal P to W of frame 0 and frame 1 is used as the synchronizing signal with a sign indicating number bit pattern of being scheduled to.The P road is 1 Q-character, represents that present is music or intermittently.Low level P Q-character is represented music, and high level P Q-character is represented intermittently.Reading in operating period, Q-character is a pulse that frequency is 2HZ, therefore, P road Q-character is detected and counts, and just can make the position of the music of the appointment that will regenerate.
Also there is similar effect in the Q road, but carries out more complicated control.Specifically, the information in Q road is provided for the microprocessor that is contained in the playing device usually, makes behind the present selected melody of having reset to begin to play next melody immediately.R road to W road formed can point out to coil in song writer, composer and other data field for information about of typing.
As for the Q road, play first 2 parts as synchronous signal mode, follow 4 as control bit.Subsequently 72 is data as address bit to follow 4 again, and last 16 is CRC (CRC) sign indicating number.Above-mentioned data bit comprises that the mark road counts TNR and index code X.The mark road is counted TNR and is changed in 00 to 99 scope.Index code X also changes to 99 from 00.Data bit also comprises a time indication code, point out this section music and, also comprise another time indication code that indication (from present) is the residue singing time of music segments end to the end in company with perdurability intermittently, these time indication codes are formed two ten sign indicating numbers that advance, and represent minute, second and frame.In this embodiment, the second time indication code is to be used for the data of the one by one unit shorter than whole song on the access fine groove dish.When coiling recording musical when fine groove dish record numerical data and with this, the data structure in P road and Q road is the same in the subcode signal.
The detailed data structure of above-mentioned subcode signal discloses in following several patents: the unexamined publication number of Japanese patent application is 58-48,279; U.S. Patent Application Serial Number 416,684 and EPC application publication number 074,841.
Fig. 3 represents the record format of the numerical data on the main channel.Each digital data record comprises one 2352 byte or 18,816.In the record format of Fig. 1, these data have replaced DB(1)-(12) and DB(17)-(28) in sound data, make 192 or 24 byte datas allocate in each record frame.Therefore, every numerical data (2352 byte) is consistent with data volume in 98 frames, makes numerical data to come record according to the signal format same with the stereo music data (Fig. 1).Can not write down numerical data so do not upset the 98 frames circulation of subcode signal yet.
As shown in Figure 3, first byte of a numerical data is zero entirely, and secondly 10 bytes are 1 entirely, and another is zero byte entirely for heel.These 12 bytes are formed a numerical data and are represented initial title.This title is with minute information, a byte per second information, a byte sections information and a byte mode information of a byte.Minute, second and section byte have been stipulated the plot location, and the section byte is with p.s.s 75 section or frame count.Mode data is pointed out the kind of numerical data in this piece.2336 remaining bytes comprise for example numerical data of still image data.
Fig. 4 represents the circuit diagram of a writing circuit, is used for the numerical data that will be recorded in the fine groove dish is formatd.In Fig. 4, label 1 and 2 is represented two input ends, and each input end is all accepted 16 bit digital data.Utilize first traffic pilot 3 that digital data conversion is become a channel form and delivers to error correcting encoder (ENC) 4.Error correcting encoder 4 adopts the mutual cross method of Reed Solomon sign indicating numbers to sound PCM(pulse code modulation (PCM)) signal (being the sound equipment numerical data) encodes so that error correction.Cross method is that the order of sound equipment numerical data is rearranged mutually, and each symbol (8 bit data) is included in two different error correction code systems.Then the output signal of error correcting encoder 4 is delivered to second traffic pilot 5.
Also be useful on second scrambler 6 and the 3rd scrambler 7 that is used for R to W road subcode signal of P road and Q road subcode signal among Fig. 4.These output signals are delivered to second traffic pilot 5 after mixing in the 3rd traffic pilot 8.The output signal of second traffic pilot 5 is sent to a modulator (MOD) 9 again, and the latter becomes 14 bit data (EFM) to the conversion of signals from second traffic pilot 5.This 14 bit data is mixed with the frame synchronizing signal (FS) that synchronous generator (SYNCGEN) 10 produces again simultaneously, delivers to output terminal 11 again.
Second scrambler 6 is added to 16 CRC sign indicating numbers on the Q road subcode signal.The 3rd scrambler 7 utilizes another Reed-Solomon sign indicating number and the cross method different with main channel to provide the error correcting code of using for R to W road subcode signal.
Should note being sent to traffic pilot 3,5,8 after time clock shown in Fig. 4 and timing signal are produced by timing generator 12, these signals all are unified on the basis of the master clock frequency that is produced by oscillator 13.
Fig. 5 is that of Play System who is used for handling fine groove dish regenerated signal simplifies circuit block diagram.
The optical regeneration signal is sent to input end 20 earlier.Regenerated signal after the shaping is sent to detuner 22, clock regeneration circuit 23 and sync detection circuit 24.Clock regeneration circuit 23 utilizes the PLL(phaselocked loop) circuit reads the bit clock frequency signal synchronous with playback of data.In addition, sync detection circuit 24 detects frame synchronizing signals, so that produces and the frame clock of the data sync of taking a sample.The output signal of clock regeneration circuit 23 and sync detection circuit 24 (being bit clock and frame clock signal) is all delivered to detuner 22, P road, Q road, R to W road detecting device 30, error correction circuit 25 and demultplexer 26.
By detuner 22 demodulation, make this signal is demodulated to former form promptly by the form before 8 to 14 modulators, 9 modulation among Fig. 4 after 21 shapings of regenerated signal process shaping circuit.Each 8 output data of coming out from detuner 22 also need be intersected reduction processing, correction process and interpolation processing accordingly through the cross processing of carrying out with error correcting encoder 4.Error correction circuit 25 comprises the RAM(random access memory), RAM controller and error correction circuit, wherein RAM has deposited the numerical data of subcode signal and main channel in.The storage of above-mentioned subcode signal and numerical data should with the bit clock and the frame clock synchronization of clock regeneration circuit 23 and sync detection circuit 24.Equally, the numerical data of main channel and subcode signal is read, and is also synchronous with the readout clock that is produced by timing generator 31 on the output signal basis of crystal oscillator 32.
Error correction circuit 25 can be corrected beating and the signal after the error correction on the time basis is exported in main channel numerical data and the subcode signal.The main channel numerical data of coming from error correction circuit 25 outputs is sent to demultplexer 26, and numerical data is divided into two-way therein, and the digital data channel that separates appears at corresponding output terminal 27 and 28.Under the main channel signal was common numerical data situation, these data were in series to export from another output terminal 29 of error correction circuit 25.Error correction circuit 25 is delivered to dedicated decoders to subcode signal, makes this subcode signal obtain the processing of error-detecting and error correcting.
Subcode signal P road and Q track data that system controller 35 is accepted from code translator 30.Having one on the system controller 35 for example is the control input device 36 of keyboard, in addition, also has row display unit 37 on the system controller 35, is used for showing the timing code that is encoded in the Q road subcode signal.In input media 36 enterprising line unit dish input operations, just can from dish, bear the numerical data of the required address of representing by timing code again.Another kind method is, can send into system controller 35 to the order in the outer computer by the I/O interface, and the numerical data of required address is also supplied with by this computing machine.In addition, P road and Q track data appear on another output terminal 33, and R to W track data appears at another output terminal 34.R to W track data can be an auxiliary data, for example can be about explaining the still image of one section music.
Writing and read operation among the RAM of error correction circuit shown in Figure 5 25 is described referring to Fig. 6 and Fig. 7 A to 7E.For ease of the explanation, suppose that a frame comprises 5 symbols altogether, wherein 4 groups every group all in main channel and one group be used for subcode signal.
Fig. 6 represents three continuous frame t 1, t 2, t 3The content of middle RAM, the figure of Fig. 6 is represented address information.At frame t 1In, a frame of playback of data is the different address (5,10,14,17,19) that is written among the RAM.The subcode signal character then is written to address 19.At frame t 1In, the main channel numerical data that is written to address (4,9,13,16) in former frame is all passed through error correcting code c 1Error correction system.At this moment, any mistake in the numerical data is passed through error correcting code c in address (1,7,12,16) 2Correct.In addition, at frame t 1In, four symbol w of the numerical data of error correction in address (0,6,11,15) 1, w 2, w 3, w 4And a subcode signal symbol in the address 18 is read from this RAM.
At next frame t 2In, the address is the error correction of (1,7,12,16) and four symbol w of intersection reduction number digital data 5, w 6, w 7, w 8Symbol s with subcode signal 2All read from RAM (address 19).Frame t 1In the numerical data that is stored in the address (5,10,14,17) use error correcting code c now 1Correct.Simultaneously, the address is the numerical data error correcting code c of (2,8,13,17) 2Correct.One frame of playback of data is written to address (6,11,15,18,20).
The write operation of this RAM with playback of data clock signal synchronous basis on carry out.The read operation of RAM is then based on the clock signal of coming of being derived by crystal oscillator output, this make the numerical data of reading from this RAM and subcode signal all must be on time shaft identical compensation (elimination of beating).In Fig. 7 A, a constant cycle l/fa(fs=44.1KHE there is the readout time of the numerical data from RAM).
Shown in Fig. 7 B, read the symbol s of subcode signal 1Time point and have a time to depart from readout time of numerical data.At this moment, numerical data w 21, w 18, w 15And w 12All be written in the address ram (5,10,14,17), shown in Fig. 7 C.Shown in Fig. 7 D, the symbol S of subcode signal 2, be written into address 19.It should be noted that the write time is not overlapping with readout time.Shown in Fig. 7 E, at frame t 1In, all be in RAM does not carry out time interval of access, not use error correcting code c 1, c 2Carry out error correction.
In the above-described embodiment, can be with a FIFO(first in first out) buffer circuits 40 is as a part that has the RAM of subcode signal in the error correction circuit 25.Fig. 8 is the circuit block diagram of this buffer circuits 40.In Fig. 8, FIFO(first in first out) buffer register 41 is accepted the subcode signal of regeneration from input end 42.By writing address generator 43 and reading address generator 44 and provide for respectively FIFO buffer register 41 to write the address and read the address.FIFO buffer register 41 has sequentially been stored the input data and the content of buffering has been exported by this way, the data of promptly receiving earlier than after the data output earlier of receiving, and can respond to writing the address and reading the address independently.
Write address generator 43 from input end 45 accept one with the subcode signal of regenerating synchronous write the incoming frame clock.Reading address generator 44 accepts to read the frame clock by crystal oscillator 32 output signals through what frequency division formed.Fifo buffer circuit 41 output subcode signal, the phase fluctuation (beat) of the latter on time shaft also uses and the same mode of main channel numerical data has been eliminated.Also have an address monitor 47 among Fig. 8, monitor the difference that writes the address and read the address with it.Address monitor 47 can detect the underflow of FIFO buffer register 41 or the possibility of overflow.The output signal of address monitor 47 can make and write the address and temporarily forbid changing so that control the operation that writes and read address generator 43 and 44.
Fig. 9 shows the circuit diagram of the second kind of embodiment that adopts the memory buffer among Fig. 8.With suitable parts among the representative of label identical among Fig. 5 and Fig. 5.
In Fig. 9, label 51 is represented a fine groove dish, remembers the digital signal that above-mentioned form is arranged thereon spirally.Utilize Spindle Motor 52 that fine groove dish 51 is pivoted.Spindle Motor servo circuit 53 these Spindle Motors 52 of control make fine groove dish 51 keep constant linear velocity rotation.Optical head 54 comprises the lasing light emitter that produces laser beam, is used for reading the record data on the fine groove dish 51, also comprises beam splitter, an optical system such as object lens and the element that is used for accepting fine groove dish 51 catoptrical reception light.Optical head 54 feeds motor 55 by screw thread and can move on the radial direction of fine groove dish 51, and screw thread feeds motor 55 and driven by screw drive circuit 56.Optical head 54 can move on both direction, and a direction is perpendicular to the surface that note has the fine groove dish 51 of signal.Other direction is exactly a radial direction, and moving respectively of this two direction controlled by focusing servo circuit 56 and tracking servo circuit 58, optical head 54 constantly is operated on the best focus and when playing can accurately follows the tracks of this Shu Jiguang.
The signal that bears again from optical head 54 is sent to the RF(radio frequency) amplifier 59.Also provide a cover to have cylindrical lens and the focus error detection circuit of optical detection square array combination and the tracking error testing circuit that adopts 3 laser to optical head 54.The output signal of RF amplifier 59 is delivered to clock extracting circuit 23.The clock of output data and clock extracting circuit 23 all is sent to frame synchronousing signal detector 24.All be sent to detuner 22 and spindle servo circuit 53 by the bit clock of clock extracting circuit 23 extractions and by the frame synchronizing signal that frame synchronousing signal detector 24 detects.
Detuner 22 is separated subcode signal from the signal that enters.The subcode signal of telling is delivered to system controller 60 by the buffer circuit among above-mentioned Fig. 8 40.System controller 60 has the CPU(CPU (central processing unit)), be used for that rotation, the screw thread of control example such as fine groove dish 51 feeds and the operations such as read-write of optical head 54.When system controller 60 received the order of microcomputer 66 by interface 65, system controller 60 was just carried out according to subcode signal and read the needed control and treatment of wanting numerical data from fine groove dish 51.
Main channel numerical data by detuner 22 is sent to RAM62 and error correction circuit 63 by RAM controller 61.Beating in RAM controller 61, RAM62 and 63 pairs of main channel numerical datas of error correction circuit, loss of data and deliberate intersection are corrected.On RAM controller 61, also be connected to the D/A(numeral to simulation) converter.A part of this D/A converter not being used as it in the fine groove disc system originally provides.So the numerical data of regeneration is sent to this data converting circuit 64.Data converting circuit 64 is also received the regeneration subcode signal by buffer circuits 40.The data of regeneration are converted into the data-signal of serial.Serial signal is delivered to interface 65, delivers to system controller 60 by the control data of microcomputer 66 by interface 65.Microcomputer 66 provides the address that need read and exports some drive controlling command signals (for example start up command signals) to interface 65 and system controller 60.
Figure 10 is an example of the serial data signal of data converting circuit 64 outputs.Serial signal adopts the unit of 32 words, and initial 4 is preamble, and secondly 4 is the service bit of sound data, and subsequent 20 is the digital sound sample data.Sample data is from least significant bit (LSB) (LSB).Digital sound sample data back adds 4 again.Among these 4, " V " position is a Q-character, and whether this digital sound sample data that expression belongs to this word is effective, and " U " position is the subcode signal part, and " C " position is used for recognizing a channel, and " P " position is a check bit.It should be noted that " U " position that all adds subcode signal on each word format, so that sequentially transmit subcode signal.
In this embodiment, buffer circuits 40 has been eliminated the time jitter (beating) that subcode signal may occur.Along the correction of time shaft be with RAM controller 61 and RAM62 in the identical mode of mode that the main channel digital signal is carried out carry out.
In more detail, RAM controller 61 produce one with the regenerated signal of the frame synchronizing signal of a detection synchronous write clock.Digital signal is written to RAM62 writing on the benchmark of clock.Use the readout clock of deriving to read this digital signal again from RAM62 by the signal of crystal oscillator output.This writes clock and readout clock also is used for writing in buffer circuits 40 and from wherein reading subcode signal.Therefore, although when writing down and physically read, phase fluctuation may occur, by the not free fluctuating component (beating) of the subcode signal of reading from buffer circuits 40.So the time relationship of subcode signal and main channel digital signal can be synchronous.
In the present embodiment, microcomputer 66 is carried out a sense order and is gone to read a predetermined address.Address code is sent into system controller 60 by interface 65.This address code is represented the timing code in Q road.System controller 60 control screw drive circuit 56 and the subcode signal of being regenerated by optical head 54 according to supervision move to a position of just in time reading facing to target to optical head 54.In the present embodiment, the reproduction that is recorded in the data on the fine groove dish 51 is to begin on a position of several of target read-out positions, so that when accessing operation, although had the mistake of regeneration in the past, still can guarantee reading and regenerating of subcode signal.Object block can be followed the tracks of with arbitrary method in two kinds of methods, and Here it is makes the subcode signal of regeneration consistent with specific address or since an adjacent correct subcode signal regeneration, then frame synchronizing signal is counted.

Claims (4)

1, a kind of broadcast disc system, the disc recording auxiliary figure data that main numerical data arranged and be used to make things convenient for master data to produce again wherein, it is characterized in that: this system comprises:
A) device, be used for producing with from dish more from birth the data cell of signal synchronous write clock;
B) be used to produce the device of readout clock with constant frequency;
C) memory buffer, from dish more from birth main numerical data and the auxiliary figure data all by with write this memory buffer from the said mode that writes clock synchronization that writes clock-generating device, and from this memory buffer by reading main numerical data and auxiliary figure data with the synchronous mode of readout clock; And
D) on the auxiliary figure data basis of reading by said memory buffer, the device of main numerical data play position in the search dish.
2, a kind of broadcast disc system records main numerical data and auxiliary figure data in the dish, the latter is the generation again that is used for convenient main numerical data, and the present invention is characterized in that: this system comprises:
A) device be used for producing with from dish more from birth the data cell of signal synchronous write clock;
B) be used to produce the device of readout clock with constant frequency;
C) memory buffer, from dish more from birth main numerical data be by writing this memory buffer with the mode that writes clock synchronization, and from this memory buffer by reading this main numerical data with the synchronous mode of readout clock;
D) first in first out buffer register, from the auxiliary figure data of dish regeneration by being written to this first in first out buffer register with the mode that writes clock synchronization, and from this first in first out buffer register by reading the auxiliary figure data with the synchronous mode of readout clock;
E) on the time basis of the auxiliary figure data of from said first in first out buffer register, reading, the device of main numerical data play position in the search dish.
3, according to the system of claim 1 or claim 2, it is characterized in that: main digital data record form is that this digitally coded acoustic signal also can be recorded in this dish with the extensive format match of digitally coded acoustic signal.
4, according to the system of claim 1 or claim 2, it is characterized in that: writing regularly of main numerical data of said memory buffer and (perhaps) register and auxiliary figure data do not overlap with main numerical data and the reading regularly of auxiliary figure data that said memory buffer and (perhaps) register come.
CN 85103577 1985-05-08 1985-05-08 Readout system of data-storage Expired CN1010624B (en)

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Application Number Priority Date Filing Date Title
CN 85103577 CN1010624B (en) 1985-05-08 1985-05-08 Readout system of data-storage

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CN 85103577 CN1010624B (en) 1985-05-08 1985-05-08 Readout system of data-storage

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CN85103577A true CN85103577A (en) 1986-11-05
CN1010624B CN1010624B (en) 1990-11-28

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1308930C (en) * 2004-03-09 2007-04-04 三洋电机株式会社 Optical disk recording/playback apparatus and optical disk evaluation method
CN101517647B (en) * 2006-09-22 2011-10-05 松下电器产业株式会社 Buffering control method and buffering control device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1308930C (en) * 2004-03-09 2007-04-04 三洋电机株式会社 Optical disk recording/playback apparatus and optical disk evaluation method
CN101517647B (en) * 2006-09-22 2011-10-05 松下电器产业株式会社 Buffering control method and buffering control device
US8139453B2 (en) 2006-09-22 2012-03-20 Panasonic Corporation Buffering control method, and buffering control device

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