CN85101451A - Video tape recorder with banded magnetic recording media - Google Patents
Video tape recorder with banded magnetic recording media Download PDFInfo
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- CN85101451A CN85101451A CN85101451.8A CN85101451A CN85101451A CN 85101451 A CN85101451 A CN 85101451A CN 85101451 A CN85101451 A CN 85101451A CN 85101451 A CN85101451 A CN 85101451A
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Abstract
(PAL, NTSC SECAM) have a kind of banded magnetic recording media video recorder of unified circuit designing thought to three kinds of S-SYSTEMs.Signal is carried out high-speed figure handle, after several mould conversions, be stored on the recording medium, composite colour television signal is carried out the sampling frequency (F of digitized analog to digital converter (aw)
c), and the subcarrier frequency (Z that in chrominance channel, carries out Digital Signal Processing
t), all be the fixed frequency that three kinds of standards all are suitable for.
Description
The present invention relates to a video tape recorder with banded magnetic recording media, in this machine, carrier chrominance signal from demodulation composite colour television signal separate after, be converted to the low carrier signal of frequency ratio standard colourity carrier frequency; Composite video signal is carried out frequency modulation(FM); The composite video signal sum of carrier chrominance signal that has reduced carrier frequency and frequency modulation is stored on the recording medium by the magnetic head system,, reads the back by the magnetic head system from this medium and change back composite colour television signal at playback time.This machine also has control circuit, and it is used to control the motor of magnetic recording media and magnetic head system.
Three kinds of video recorder systems of now common usefulness, VHS, Video 2000 and Betamax constitute in above-mentioned mode just.For the VHS system, in phase-aoternation line system (PAL), it is 627KHZ that " low " colourity is paid carrier frequency; And in the standard of NTSC (NTSC), this frequency is 629KHZ; These two " low " colourities are paid 40 and 40,125 times of horizontal frequency that the carrier frequency rate is respectively PAL and TSC-system formula.In playback, the coupling of these carrier frequency and horizontal frequency separately makes its energy compensating band speed deviation even can reach the levels of precision of the homophase regeneration that makes former colourity carrier frequency.
Therefore, clearly, also need adjunct circuit the circuit of in video tape recorder, in TV, using always.In common video tape recorder, these adjunct circuits mainly are made of discrete component, have only the monolithic integrated circuit of a spot of execution analog function.Catalogue of the present invention be to improve integrated level, promptly use three kinds of colour television standards, the design philosophy of the novel unified circuit that PAL, NTSC and SECAM are suitable for, increase the scope of using monolithic integrated circuit, that is to say and only need carry out minor modifications just applicable to the circuit designing thought of standard separately.Specifically, these only revise to overall circuit design seldom influence, so can provide an optimal circuit design philosophy that three kinds of colour television standards all are suitable for.
Solution of the present invention is based on such mentality of designing, carry out signal processing in the various video recorder systems with high-speed digital circuit, but not that the output signal of these digital circuits form with numeral is stored on the tape, but, before storage, these digital signals are changed back corresponding analog signal.According to the present invention, first analog to digital converter provides the sampled signal of a fixed frequency to all three kinds of colour television standards.Another basic mentality of designing of the present invention is, the Digital Signal Processing in chroma channel all is to carry out on a fixing carrier frequency to all three kinds of colour television standards, and this carrier frequency is the integral frequency harmonizing wave of sampling frequency.
So the signal processing in video and the playback procedure is all finished by digital circuit, this makes the integrated level of video tape recorder to improve greatly.
Now, describe the present invention and its other advantage in detail by the reference accompanying drawing.
Fig. 1 is the block diagram of the embodiment of way circuit of the present invention;
Fig. 2 is the block diagram of chrominance circuit embodiment of the present invention;
Fig. 3 is the block diagram of video processing circuit embodiment of the present invention;
Fig. 4 is the block diagram of the optimum implementation of numerical frequency wave detector required in Fig. 3 circuit;
Fig. 5 is the block diagram of the line bonus circuit that needs in Fig. 2 circuit for treatment S ECAM signal;
Fig. 6 represents the block diagram and the frequency response curve of the best first index zone bandpass filter;
Fig. 7 represents that an optimum signal forms the block diagram and the frequency response curve of band pass filter;
Fig. 8 represents the block diagram and the frequency response curve of first inserter an of the best;
Fig. 9 is the block diagram of the sine-wave producer an of the best.
Fig. 1 has represented overall embodiment of the present invention with the block diagram form.By the first change over switch u1, the analog input of high-speed AD converter aw links to each other with composite colour television signal input fse when video mode R, perhaps links to each other with the output of the two-way amplifying device ZV of the KS of magnetic head system when manner of playback P.Here, simply shown the KS of magnetic head system with two magnetic heads.Because analog to digital converter aw is at a high speed, preferably adopts instantaneous (flash) transducer, it is the multi-bit parallel numeric word of speed that its output has provided with the pulse repetition frequency FC of sampled signal fc.Sampled signal fc is produced by sampling oscillator os, and to all three kinds of colour television standard PAL, NTSC and SECAM, this oscillator all vibrates on a fixing frequency.In optimum implementation, this frequency is in about scope from 18MHZ to 20MHZ, for example, and 18MHZ.
At video mode R, the numeric word that appears at the output of analog to digital converter aw has been represented digitized composite colour television signal fs '.Handle this signal in three high-speed digital circuit db, dc and dm, these digital circuits connect each other and parallel processing signal at least partially.Digital circuit db mainly handles composite video signal, and isolates synchronizing signal from vision signal, so its output provides pure digital luminance signal LS.It also isolates carrier chrominance signal cs from composite colour television signal fs '.In digital circuit dc, handle carrier chrominance signal according to corresponding standard.Digital circuit dm accepts the correction signal cr feed, and the control signal Sm of magnetic head motor and drive is provided.These three fast digital circuits db, dc, dm also are synchronous by the sampled signal of fixed frequency.
Fig. 1 also shown by being connected of the synchronous control unit Se of sampled signal fc and video tape recorder operating key, and the signal that comes from operating key or command transfer to high-speed digital circuit db, dc, dm.
The output of db and two digital circuits of dc is connected respectively to the second digital to analog converter dw2 and the first digital to analog converter dw1, and analog adder aa forms the above-mentioned analog signal that deposits magnetizing mediums in to the output signal addition of digital to analog converter and dw2.At video mode R, analog adder aa is connected to amplifier ZV through the second change over switch u2.By line VL digital circuit db according to the working method of video tape recorder be video or reset can control amplifier ZV gain characteristic.At manner of playback P, the input of analog to digital converter aw is connected to amplifier ZV through the first change over switch u1, and simultaneously, the output of analog adder aa is connected to the Ausgang sa of composite colour television signal through the second change over switch u2.
In the expression of Fig. 1, transmission line analog signal and digital data transmission line have been made differentiation.The former draws with common solid line; The latter represents with band shape, represents bus, which comprises at least the as many parallel lead with the figure place of numeric word to be processed.
Fig. 2 represents an embodiment of chroma processin circuit with the block diagram form.Complete clear for what narrate, signalling channel is from analog to digital converter aw in circuit diagram, and signal is added to analog to digital converter aw from change over switch u1.The circuit of Fig. 2 both had been applicable to that the video mode also was applicable to manner of playback, just changed the circulating direction of some other operating parameters rather than signal.
The output of analog to digital converter aw is connected with the first input end of the first and second digital multiplier m1 and m2, and second input of multiplier m1 and m2 is linked cosine output ca and the sinusoidal output sa that first frequency can be put controlled digital sine wave generator sg1 respectively.By the first Digit Delay Element V1 that a generation equates with the delay of the one 90 ° of digital phase shifter h1, the output of the first multiplier m1 is connected to the first input end of the first digital adder a1; And, the output of the second multiplier m2 is connected to second input of the first digital adder a1 by the one 90 ° of phase-shifter h1.For the VHS system, at video mode R, the frequency configuration input fe of primary sinusoid generator sg1 is the first digital signal ds1, and this frequency equals 1/4th poor with separately colourity carrier frequency of sampling frequency FC; In manner of playback, input fe is the second digital signal ds2, and this frequency equals the certain multiple sum of 1/4th and the line frequency of sampling frequency FC, and this multiple is 40 in the TSC-system formula, and this multiple is 40,125 in PAL and Sequential Color and Memory system formula.So the different colour television standards according to the TV signal of transmitting make corresponding colourity carrier frequency or line frequency enter primary sinusoid generator sg1.Two register r1 in Fig. 2, r2 has represented this process, and r1 and r2 calculate, store digital signal ds1 according to selected standard three kinds of different systems PAL, NTSC indicating from input, the SECAM, and ds2 also provides them.Again horizontal synchronizing pulse SS is defeated by the second register r2.In video and manner of playback, for sine-wave generator sg1, sg2, the difference of digital signal ds1, ds2 is used, and finishes with the third and fourth electronic commutator u3 and u4.
In Video 2000 and Betamax system, must come selected digital signal ds1, ds2 according to " low " colourity carrier frequency separately.
By two multiplier m1, m2, delay unit v1,90 ° of phase-shifter h1, the parallel circuit that adder a1 and digital sine wave generator sg1 form is represented a digital orthogonal mixer, for all three kinds of colour television standards, this frequency mixer changes over accurately 1/4th of sampling frequency FC with the colourity carrier frequency of composite colour television signal.In the embodiment of Fig. 2, this sampling frequency FC is exactly carrier frequency Zt.
The input of index zone bandpass filter nb1 is linked in the output of adder a1, and the passband of filter nb1 is provided with according to each colour television standard.The same with r2 as register r1, index zone bandpass filter nb1 also has one input is set, and does not draw in Fig. 2 in order to simplify.By digital sampling device dZ(decimator), the output of index zone bandpass filter nb1 is connected to the first input end of the 3rd multiplier m3, the sampling frequency f1 of dz is 1/3rd of sampling frequency FC.The input that digital signal forms band pass filter fb is linked in the output of the 3rd multiplier m3, and the output process digital comb filter kf of fb is connected to the input of the first digital interpolator ip1, and interpolater ip1 is synchronous by clock signal fc.In the video mode, switch es connects, so that digital comb filter kf only works when manner of playback P.
The effect of the sampler dz and the first interpolater ip1 is that processing carrier chrominance signal parallel circuit is worked under a more suitably lower clock frequency f1, rather than at high sampling frequency FC.Its result makes these works of treatment that time enough be arranged, and has reduced the required circuit quantity of comb filter widely.
Equal the second Digit Delay Element v2 of the 2 90 ° of phase-shifter h2 by the second digital standard band pass filter nb2 and retardation, the output of interpolater ip1 is connected to the first input end of the 4th digital multiplier m4, and the output of interpolater ip1 being connected to the input of the 2 90 ° of phase-shifter h2 by the second index zone bandpass filter nb2, the output of the second phase-shifter h2 is connected to the first input end of the 5th digital multiplier m5.Second input of the 4th and the 5th multiplier m4 and m5 is connected respectively to cosine output ca and the sinusoidal output Sa that second frequency can be put sine-wave generator sg2, and the input that the output of m4 and m5 is defeated by the first digital to analog converter dw1 through second adder a2.
At video mode R, the frequency configuration input fe of the second sine-wave generator sg2 is the second digital signal ds2; At manner of playback P, frequency configuration input fe is the first digital signal ds1.
Corresponding parallel circuit v1 behind analog to digital converter aw, h1, m1, m2, a1 are the same with sg1, Delay Element v2,90 ° of phase-shifter h2, two multiplier m4 and m5, adder a2 and sine-wave generator sg2, and these have also formed an orthogonal mixer.The difference of two frequency mixers is that the arrangement of previously described frequency mixer parallel circuit is the mirror image that second frequency mixer parallel circuit arranged, this point we can say that this is a key character of the present invention, this has simplified whole circuit of chrominance channel widely, because, otherwise the complex filters that just need be able to change.And in second orthogonal mixer of forming by parallel circuit v2, h2, m4, m5, a2 and sg2 of conventional design, treat mixed frequency signal for two that at first produce phase difference and just in time be 90 °, then respectively with cosine wave and sinusoidal wave mixed frequency from sine-wave oscillator sg2, add up mutually at last; And first orthogonal mixer at first with input signal respectively with sine wave and cosine wave mixing from sine-wave oscillator, and only at this moment, from the cosine multiplying signal, produce orthogonal signalling.
Except frequency configuration input fe, primary sinusoid generator sg1 also has phase control end fr, and fr links to each other with the output of DPLL digital phase-locked loop pr.DPLL digital phase-locked loop pr is digital line synchronizing signal SS and from digital horizontal deflection oscillator h.Signal compare.Therefore, sine-wave generator is similar to a simulaed phase locked loop (PLL) oscillator, and its frequency stability is equivalent to conventional crystal oscillator.
Second input of the 3rd multiplier m3 links to each other with the output of the automatic coloured controlled stage ac of numeral, and the signal input part of ac is connected to the output of comb filter kf, and the clock of ac is input as horizontal synchronizing pulse SS.
Colored controlled stage ac remains steady state value with the amplitude of burst signal, so that when video, obtain optimizing level control, and in the fluctuation of playback time compensation magnitude, the amplitude fluctuation that causes of tape performance change for example.It also improves or reduces the amplitude of burst signal according to different colour television standards.
Video tape recorder has two magnetic heads usually, alternately contacts with recording medium.In colored controlled stage ac, determine the Control Parameter of two magnetic heads respectively, to compensate system's difference of two passages.For this reason, point out magnetic head with contact with tape for additional signal (not shown) of colored controlled stage input.
The signal that is operated in the sampling frequency f1 that has reduced forms band pass filter fb, in the colourity branch road, sets up a standard pass-band performance accurately; And band pass filter nb1 only plays a smart slightly preliminary election, thereby is easy to realize.
At playback time, comb filter kf has increased the crosstalk attenuation between the adjacent track part of recording medium; When video, the employing carrier chrominance signal usual method of phase change line by line increases this crosstalk attenuation.According to different television systems, the change line by line of carrier chrominance signal phase place is carried out in such a manner, promptly at playback time, crosstalk components is just cancelled each other in a suitable comb filter.In Fig. 2, during video, these phase changes are by add what an appropriate signals produced on the frequency configuration input fe of sine-wave generator sg2; Playback time adds that by the frequency configuration input fe at sine-wave generator sg1 the signal of a correspondence offsets this phase change.
Fig. 3 represents an embodiment block diagram of video processing circuit.It is different with chroma processin circuit, can not solve video and these two tasks of resetting with a single passage.The first subchannel r is used to the R that records, and the second subchannel P is used for resetting.Sampled signal still is signal fc, and its fixed frequency FC is preferably big in 18 to 20MHZ scope, and analog to digital converter aw still is positioned at the top of signalling channel.Except multiplier m1, the m2 of control chart 2, also the output of analog to digital converter aw the 5th electronic commutator u5 that feeds, switch u5 is that R or P determine that signal removes subchannel r or removes subchannel P according to selected working method.
In subchannel r, the output of analog to digital converter aw has been added to the input of low pass filter tp, the upper cut-off frequency of tp is 3MHZ, the output of tp enters digital synchronous separator stage ha, and entering the input of digital vco Vo through digital preemphasis and limiter stage Pb, oscillator Vo is as a frequency modulator.Three digital signal ds3 is defeated by digital vco Vo, and ds3 determines the carrier frequency of oscillator according to different television systems.The output of oscillator Vo is connected to the input of the second digital to analog converter dw2 through the first digital high-pass filter hp1 and the 6th electronic commutator u6, and the low cut-off frequency of filter hp1 is approximately 1.5MHZ.
In the second subchannel P, by change over switch u5 the output signal of analog to digital converter aw is added to the filter of second digital high-pass and subtracts device hp2, the low cut-off frequency of hp2 is approximately 1.5MHZ.The input coupling of the output of hp2 and the second digital to analog converter dw2, in the particular of Fig. 3, being achieved as follows of this coupling, the output of frequency detector fd is connected to the input of digital sampling (decimating) low pass filter dt, the upper cut-off frequency of dt is approximately 3MHZ, and the clock signal f2 that has half sampling frequency FC/2 is added to low pass filter dt, so numeric word appears at the output of filter dt with this clock rate f2.And then that digital sampling low pass filter dt is digital deemphasis and noise reduction level du, the output of du is connected to the first input end of the 3rd adder a3 through the first input and output path of the 7th electronic commutator u7, and is connected to the first input end of digital correlator KL through the second input and output path of the 7th electronic commutator.Second input of correlator KL is connected to the output of the 3rd adder a3, and second input of adder a3 is linked in the output of correlator KL.The output of change over switch u7 also is connected with the input of delay-level VS, and the delay that postponing VS provides equals a line period of this television system.Be connected to the output of the 3rd adder a3 with the second synchronous digital interpolator ip2 of sampled signal fc, through the 6th electronic commutator u6, the output of interpolater ip2 is connected to the input of the second digital to analog converter dw2.The control input end of change over switch u7 is connected to the output of dropout detector dk, and the input of dk encourages by the second high pass filter hp2.
Dropout detector dk is a comparison circuit, and when incoming level was lower than a predetermined value, it started change over switch u7, is used for the signal of last scan line of self-dalay level VS to replace this weak from recording medium, the signal that noise is very big.
Reducing noise is also finished by correlator KL.In this custom circuit, the noise that the skew of the trace of the line signal of lining by line scan produces reduces by filter, when skew is big, the moving detector of filter is disconnected, to prevent changing the interference that produces by the high speed vertical image.
The block diagram of the optimum implementation of the frequency detector fd of Fig. 4 presentation graphs 3.The input of this wave detector is connected to the subtrahend input S of subtracter st and first signal input part of electronics multichannel intermediate switch kr through the 3rd Delay Element V3 and the first digital absolute value level bb1, and the retardation of the 3rd Delay Element V3 equals the 3 90 ° of digital phase shifter h3.The 3 90 ° of digital phase shifter h3 is between the input of the input of frequency detector and the second digital absolute value level bb2.The output of the second digital absolute value level bb2 is connected to the minuend input m of subtracter st and the secondary signal input of multichannel intermediate switch Kr.The control input end of K switch r is connected to the symbol output Va of subtracter st, two signal output parts of Kr are linked dividend input dd and the divisor input dr of digital divider d respectively, the output of divider is connected to the address input end of read-only memory rm, and read-only memory rm is storing the arc-tangent value of first half-quad.
The highest significant position of the output signal of the output signal of the 3rd Delay Element V3 and the 3 90 ° of phase-shifter h3 is given to first and second inputs of the first XOR assembly ex1 respectively, the output of XOR assembly ex1 is added to the first input end of the second XOR assembly ex2, and second input of the second XOR assembly ex2 is connected to the symbol output of subtracter st.
An inverter among the first multichannel inverter Vi1 is linked in each output of read-only memory rm, and all inputs of multichannel inverter Vi1 are connected to the first input end of each switch of the first variable connector vu1.Second input of these switches is connected to the output of multichannel inverter Vi1, and the common control input end of these switches is connected to the output of the second XOR gate ex2, and the output of the vu1 of first variable connector is linked digital differentiator dg.
High-order one side in the variable connector vu1 output signal position, output by the second XOR assembly ex2 replenishes later on as time high bit, the output of the first XOR assembly ex1 is as next most significant bit, and the sign bit of the 3rd Delay Element V3 output signal as highest order.Digital differentiator dg is received in the output of variable connector vu1.
Intermediate switch kr is controlled by the symbol output va of subtracter st by this way, a signal is added in always the dividend input dd of divider d, this signal less than or equal signal at most at divisor input dr, so that divider d has the fixedly output of figure place, it can not have opposite situation, but say, if allow a bigger number to be removed, under the situation of the limit, may reach unlimited by a less number.By two absolute value level bb1 and bb2, the output signal of Delay Element V3 and 90 ° of phase-shifter h3 has been removed their symbol.Because this result and the measure of just having described to divider d, read-only memory rm only need be included in first half-quad, that is, and and from those arc-tangent value of 0 ° to 45 °.Therefore make the capacity of read-only memory reduce to minimum.
By two XOR assembly ex1 and ex2, the memory cell number that needs is added to 360 ° of angles also has been added in the output signal of read-only memory rm.The output of variable connector VU1 has provided the phase of input signals detection signal that will carry out frequency detecting, obtains the frequency detecting signal by differentiator dg from this phase detection signal.
Not the signal that produces two quadrature in phases by parallel circuit V3, h3, but obtain these signals by horizontal (transversal) filter of odd.This odd is very important, because if the number of times of filter is given, during 1/4 symmetry of the clock frequency of frequency band and transversal filter, an especially little amplitude error is arranged in its Frequency Response.
Parallel circuit V3 and h3 are input as 8, are 7 later at intermediate switch kr, are output as 10.In these cases, the required chip area of Mos integrated circuit of the frequency detector of Fig. 4 is estimated as 6mm
2
Fig. 5 represents to comprise the embodiment of Fig. 2 device of the line bonus circuit of treatment S ECAM signal.The first digital filter df1 is connected to the output of the first index zone bandpass filter nb1, and the characteristic of filter df1 can be from bell the bell of playback time that be transformed in when video, for simply this property list not being shown among Fig. 5.Additional character frequency detector fd ' is connected to the output of the first digital filter df1, and wave detector fd ' is digital frequency modulator fm afterwards, and the frequency of modulator fm can be second value of playback time from first value transform in when video partially.Only during the carrier chrominance signal existence, start modulator fm by horizontal synchronization pulse ss.Is the second digital filter df2 after the frequency modulator fm, bell (conversion characteristics of not drawing the figure) that the characteristic of filter df2 can be when playback time bell be transformed to video.When the Sequential Color and Memory system formula, the output of filter df2 is connected to the input of the second index zone bandpass filter nb2 through the first input and output path of the 8th electronic commutator u8; When PAL or TSC-system formula, the second input and output path of change over switch u8 is connected the output of the first interpolater ip1 with the input of the second index zone bandpass filter nb2.
In the Sequential Color and Memory system formula, work be not parallel circuit dz, m3, fb, kf and ip1, but parallel circuit df1, fd ', fm and the df2 of top firm what is said or talked about.Other parallel circuit figure of Fig. 5 is identical with Fig. 2.
Fig. 6 represents the block diagram and the Frequency Response of the best design of the first index zone bandpass filter nb1.Compare with other digital filter that can be used as this band pass filter, consider the number of used adder ad and subtracter sb, the digital filter of Fig. 6 has very superior structure.Its transfer function is:
H（Z）＝ (（1＋Z
－10）（1－Z
－8）（1＋Z
－6）)/(（1＋Z
－2）
3)
As shown in, the digital filter of Fig. 6 is made up of adder ad, subtracter sb and Delay Element v, the retardation of each Delay Element equals a multiple in filter sampled signal cycle.This multiple equal with Z be the end each index on the occasion of.
Shown in the block diagram of Fig. 6, realize (a 1+Z
-6) parallel circuit in the back of sampler dz, the frequency F1 of the sampled signal f1 of sampler dz equal sampled signal fc frequency Fc 1/3rd.When frequency Fc was 18MHZ, then to be operated in frequency Fc/3 be 6MHZ to this parallel circuit.Therefore, the dz back with symbols Z
*And the parallel circuit of index-2 expression, if the delay that provides is 2Fc/3, just equal 6Fc.
It is that the standardization decay g of unit is as the frequency response curve of function that is the frequency F of unit with dB with MHZ that Fig. 6 has provided.The maximum of curve is at 4.5MHZ, and it equals above-mentioned carrier frequency zt.
Fig. 7 is block diagram and the frequency response curve that the signal of Fig. 2 or Fig. 5 forms the best design of band pass filter fb.Except above-mentioned elementary cell ad, sb and v, this digital filter also contains multiplier mp, and mp has produced the invariant 0.375 of transfer function H (Z).This transfer function is:
H（Z）＝（1-Z
-2）
5（0.375+Z
-2）（1+0.375Z
-2）
This digital filter, the adder as required and the number of subtracter also have a superior structure.Its characteristic is to the 1.5MHZ symmetry, this be since filter to be the sampled signal f1 of Fc/3 with the frequency synchronous, so the carrier frequency of 4.5MHZ also becomes 1/3rd.
Fig. 8 is the block diagram and the frequency response curve of the first interpolater ip1 best design, and its transfer function is
H（Z）＝ (（1＋Z
－2）（1－Z
－4）（1＋Z
－6）
2)/(（1＋Z
－2）
2)
Digital multiplier m at Fig. 8 digital filter input
XWith each digital input code e be transformed to three unit sequence e, o ,-e.This three unit sequence is equivalent to realize (1-Z
-2).
The diagram of the digital filter frequency response curve of Fig. 8 has been interrupted, and has promptly compressed between 3.0MHZ and 4.0MHZ.This digital filter is synchronous by sampled signal fc, if with the sampling frequency of 18MHZ then minimal attenuation (odB) at 4.5MHZ.
The block diagram that has the optimum implementation of two the sine-wave generator sg1 of related with it respectively multiplier m2 and m5 and sg2 among Fig. 9 presentation graphs 2 and Fig. 5.A generator like this comprises a j bit digital accumulator ak, j=14 in the embodiment of Fig. 9.As everyone knows, accumulator is synchronous add circuit, when it receives each clock pulse, on the result who is obtained when being added to same number with previous clock pulse.Frequency configuration input fe is two digital signal ds1 or the ds2 that takes out from one of two register r1, r2 of Fig. 2 or Fig. 5.The clock signal that is added on the accumulator ak is sampled signal fc.
Q littler than (j-2) position in the output signal of accumulator ak position is to feed by each inverter of the second multichannel inverter vi2, and q is less than or equal to j-2 here.Q=6 in the embodiment of Fig. 9 is so comprised that power is 2
6To 2
11These positions (supposition use straight binaries).
The input of each inverter is connected to the first input end of each switch of the second variable connector vu2, and second input of these switches is connected to the output of each inverter, and the common control input end of these switches is connected to the output of (j-1) position.The address input end of additional read-only memory rm ' is linked in the output of the second variable connector vu2, the sine value of the in store first quartile of memory rm ', and its output is connected to the first input end of multiplier m2 or m5.Second input of multiplier is a signal input part, the output of multiplier is connected to each inverter of the 3rd multichannel inverter vi3, the input of these inverters is connected to the first input end of each switch of the 3rd variable connector vu3, and second input of these switches is connected to the output of these inverters.The common control input end of these switches of the 3rd variable connector vu3 is connected to the j position output of accumulator ak, and the output of the 3rd variable connector vu3 provides the input signal that has been multiplied each other by sine wave.
Two multichannel inverter vi2, vi3 and two variable connector vu2, vu3 also are used for obtaining second to four-quadrant sine value from the first quartile sine value that is kept at read-only memory rm '.With similar method (in Fig. 9, not drawing), can obtain cosine value at the cosine output Ca of sine-wave generator sg1, sg2.Be provided with an additional read-only memory, two additional multichannel inverters and two additional variable connectors for this reason.Yet, also can utilize the relation of SIN function and cosine function, that is to say that both have 90 ° of phase differences, so the additional read-only memory of Fig. 9 only need store the sine value of first quartile.
In Fig. 2 to Fig. 9, the connection between all each circuit is all drawn with single line.This does not just mix for the strip line with the expression bus.Because, principle in according to the present invention, the parallel circuit among Fig. 2 to Fig. 9 all are the parallel circuits with the parallel mode processing digital signal, except indivedual exceptions, interconnecting between each parallel circuit must be thought bus, the control line of for example various change over switches and variable connector.In Fig. 9, the numeral of the number of lead tiltedly to draw in the bus.
As described in beginning, the present invention can finish with monolithic integrated optical circuit. Can make a monolithic integrated optical circuit to whole circuit as required, perhaps be divided into several integrated circuits. Because all parallel circuits all are digital circuits, adopting insulated-gate type field effect transistor is that so-called MOS technology is advantageous particularly, but the high speed bipolar digital circuit technique also is suitable for.
The principle of using in chrominance channel is namely carried out the displacement digital processing by the quadrature mixing to the subharmonic of clock frequency, and do not consider that colourity pays the dependence of carrier frequency to standard, so make it to use same fixing sampling frequency to all colour television standards, namely produce the single clock generator that sampled signal only need have a fixed frequency, this is a very big superiority. Because this clock generator is generally a crystal oscillator, so only need a single crystal just much of that, if link together and pay carrier frequency clock frequency and the quadruple colourity relevant with standard, but then need three crystal oscillator and oscillators with three twin crystals that are respectively applied to PAL, NTSC and SECAM-system formula. Thereby the application of present principles is not limited to video tape recorder, and it can be successfully used to the digital processing to the colour TV signal of any multi-standard.
Claims (10)
1, the video tape recorder that has banded magnetic recording media, in this machine: carrier chrominance signal from demodulation composite colour television signal separate after, be converted to the low carrier signal of frequency ratio standard colourity carrier frequency; Composite video signal is carried out frequency modulation(FM); Composite video signal (bs ') sum of the carrier chrominance signal that has reduced carrier frequency (CS ') with frequency modulation is stored on the recording medium by the magnetic head system, when resetting (P), after reading from this medium by the magnetic head system, it is changed back composite colour television signal (fs); This machine also has control circuit (dm), and it is used to control the motor of magnetic recording media and magnetic head system (ks);
It is characterized in that:
A high-speed AD converter (aw) links with composite colour television signal input (fse) or magnetic head system (ks) through first electronic commutator (u1), simultaneously, all be with the sampled signal of the fixed frequency analog to digital converter (aw) of feeding for all three kinds of colour television standards (PAL, NTSC, SECAM);
Be separated into carrier chrominance signal (cs) and composite video signal (bs), these signals are become the digital processing of digital chrominance signal and digital composite video signal, separate synchronizing signal from composite video signal (bs), these synchronizing signals are become the digital processing of digital synchronization signal (ss) and produce motor control figure signal (sm), all these work are all by high-speed digital circuit (db, dc, dm) and finish in the parallel processing mode at least partially;
To all three kinds of colour television standards, the digital processing of carrier chrominance signal (cs) all is to finish on a fixing carrier frequency (zt), this fixing carrier frequency (zt) approaches the standard carrier frequency, and is the integral multiple of the frequency (FC) of sampled signal (fc);
Feed the respectively first and second digital to analog converter (dw of the digital chrominance signal (cs) handled and the composite video signal (LS) handled
1, dw
2), the output of each digital to analog converter is connected to the input of an analog adder (aa);
The output of analog adder (aa) is through the second electronic commutator (u
2) be connected with the composite colour television signal output (fsa) or the magnetic head system (ks) of video tape recorder.
2, claim 1 described video tape recorder wherein comprises a digital chrominance circuit (dc), it is characterized in that:
Be provided with a shared pathway that is used for video mode (R) and manner of playback (P);
The fixed frequency scope of sampled signal (fc) is 18MHZ approximately from 18MHZ to 20MHZ and preferably;
The output of analog to digital converter (aw) is connected to the first and second digital multiplier (m
1, m2) first input end, second input of multiplier (m1, m2) is connected respectively to cosine output (ca) and the sinusoidal output (sa) that second frequency can be put controlled digital sine wave generator (sg1);
First Digit Delay Element (v1) that the output of first multiplier (m1) equals the one 90 ° of digital phase shifter (h1) through retardation is connected to first output of first digital adder (a1), and the output of second multiplier (m2) is connected to second input of first adder (a1) through the one 90 ° of phase-shifter (h1), the output of adder (a1) (decimator) is connected to the first input end of the 3rd digital multiplier (m3) through the first digital standard band pass filter (nb1) and a digital sampler (dz), the sampling frequency of dz (f1) is a subharmonic, and it is preferably 1/3rd of fixing sampling frequency (Fc);
The output of the 3rd multiplier (m3) is connected to the input that digital signal forms band pass filter (fb), the output of filter (fb) is connected to input by synchronous first digital interpolator (ip1) of sampled signal (fc) through digital comb filter (kf), comb filter (kf) only when the video mode by electronic switch (es) bypass;
The output of digital interpolator (ip1), equal second Digit Delay Element (v2) of the 2 90 ° of phase-shifter (h2) retardation through the second digital standard band pass filter (nb2) and retardation, be connected to the first input end of the 4th digital multiplier (m4), simultaneously, be connected to the input of the 2 90 ° of phase-shifter (h2) through the second index zone bandpass filter (nb2), the output of the 2 90 ° of phase-shifter (h2) is connected to the first input end of the 5th digital multiplier (m5);
Second input of the 4th and the 5th multiplier (m4, m5) is connected respectively to cosine output (ca) and the sinusoidal output (sa) that second frequency can be put digital sine wave generator (sg2);
The output of the 4th and the 5th multiplier (m4, m5), each is connected with an input of second digital adder (a2), and the output of adder (a2) is connected to the input of first digital to analog converter (dw1);
Second input of the 3rd multiplier (m3) is connected to the numeral output of controlled stage (ac) automatically, and the signal input part of ac is connected to the output of comb filter (kf), simultaneously lock-out pulse (ss) is added to the input end of clock of ac;
For the VHS standard, first digital signal (ds1) equals 1/4 sampling frequency (FC) and colourity is separately paid the poor of carrier frequency, ds1 is added to the frequency configuration input (fe) of primary sinusoid generator (sg1) when the video mode; Second digital signal (ds2) equals the certain multiple sum of 1/4 and associated line frequency of sampling frequency (FC), at this multiple of TSC-system formula is 40, at PAL and this multiple of Sequential Color and Memory system formula is 40.125, when manner of playback (P), ds2 is added to the frequency configuration input (fe) of primary sinusoid generator (sg1);
The phase control of primary sinusoid generator (sg1) input (fr) be the phase control signal that comes from digital phase control circuit (pr), and phase-control circuit (pr) compares digital synchronization signal (ss) and from the signal of digital horizontal deflection oscillator (ho);
When video mode (R), the frequency configuration of second sine-wave generator (sg2) input (fe) is second digital signal (ds2); When manner of playback (P), input (fe) is first digital signal (ds1).
3, claim 1 described video tape recorder comprises a digital video signal processing circuit (db), it is characterized in that:
Be provided with first subchannel (r) and second subchannel (p) that is used for manner of playback (P) that is used for video mode (R);
The fixed frequency of sampled signal (fc) approximately from 18MHZ to 20MHZ, is preferably 18MHZ;
During video (R), in first subchannel (r),
The output of analog to digital converter (aw) is connected to the wave digital lowpass filter (tp) that upper cut-off frequency is about 3MHZ, digital synchronous separator stage (ha) is supplied with in the output of filter (tp), and be connected to the input of digital vco (vo) by digital deemphasis and limiting stage (pb), oscillator (vo) is as a frequency modulator, vo accepts three digital signal (ds3), and three digital signal (ds3) decides its carrier frequency according to the standard of this TV;
The output of oscillator (vo), first digital high-pass filter (hp1) that is about 1.5MHZ through lower-cut-off frequency is connected to the input of second digital to analog converter (dw2);
During manner of playback (P), in second subchannel (P),
The output of analog to digital converter (aw), second digital high-pass filter (hp2) that is about 1.5MHZ through lower-cut-off frequency, be connected to the input of numerical frequency wave detector (fd), the input that second digital to analog converter (dw2) is coupled in the output of numerical frequency wave detector (fd).
4, claim 3 described video tape recorders is characterized in that:
Between the input of the output of frequency detector (fd) and second analog to digital converter (dw2), be provided with following line bonus circuit according to the direction of signal flow:
A sampling (decimating) wave digital lowpass filter (dt), its upper cut-off frequency is approximately 3MHZ, and it is that to equal the clock signal (f2) of sampling frequency half (FC/2) by frequency synchronous,
Digital deemphasis and noise suppressed level (du),
The first input and output path of the 7th electronic commutator (u7),
First input of the 3rd digital adder (a3),
By synchronous second digital interpolator (ip2) of sampled signal (fc);
The output of second high pass filter (hp2) is delivered to the control input end of the 7th change over switch (u7) through dropout detector (dk), and the output of change over switch (u7) is connected to the input of the delay-level (vs) that retardation equals a line period;
The output of delay-level (vs) is connected to second input of the 7th change over switch (u7) and the first input end of digital correlator (kL), second input of digital correlator (kL) is connected to the output of the 3rd adder (a3), and the output of KL is added to second input of the 3rd adder (a3).
5, claim 3 or 4 described video tape recorders, its numerical frequency wave detector (fd) is characterised in that:
The input of this numerical frequency wave detector (fd), equal the 3rd Delay Element (v3) and the first digital absolute value level (bb1) of the 3 90 ° of digital phase shifter (h3) by retardation, be connected to the subtrahend input (s) of subtracter (st) and first signal input part of electronics multichannel intermediate switch (kr);
The 3 90 ° of phase-shifter (h3) is positioned between the input of the input of frequency detector (fd) and the second digital absolute value level (bb2), the output of the second digital absolute value level (bb2) is connected to the minuend input (m) of subtracter (st), and is connected to the secondary signal input of multichannel intermediate switch (kr);
The control input end of multichannel intermediate switch (kr) is connected to the mark signal output (va) of subtracter (st), and two signal output parts of kr are connected respectively to the dividend input (dd) and the divisor input (dr) of digital divider (d), and the output of divider (d) is linked the address input end of the read-only memory (rm) of preserving first half-quad tangent value;
The highest significant position of the 3rd Delay Element (v3) output signal and the highest significant position of the 3 90 ° of phase-shifter (h3) output signal are connected respectively to first and second inputs of the first XOR assembly (ex1), the output of the first XOR assembly (ex1) is connected to the first input end of the second XOR assembly (ex2), and second input of the second XOR assembly (ex2) is connected to the symbol output (va) of subtracter (st);
Each output of read-only memory (rm) is connected in the inverter of the first multichannel inverter (vi1), the input of multichannel inverter is also connected to the first input end of each switch of first variable connector (vu1), and second input of these switches is connected to the output separately of these inverters, and the common control input end of these switches is connected to the output of the second XOR assembly (ex2);
High-order one side of variable connector (vu1) output signal, output by the second XOR assembly (ex2) replenishes later on as time high bit, the output of the first XOR assembly (ex1) is as next most significant bit, and the sign bit of the 3rd Delay Element v3 output signal as highest order;
Digital differentiator (dg) is received in the output of variable connector (vu1).
6, claim 2 described video tape recorders comprise an adjunct circuit that is used for the Sequential Color and Memory system formula, it is characterized in that:
The output of the first index zone bandpass filter (nb1) is connected to first digital filter (df1), the characteristic of filter (df1) can be when video bell when (R) be transformed to playback (P) bell, the output of first digital filter (df1) is connected to additional character frequency detector (fd ');
Additional character frequency detector (fd ') is digital frequency modulator (fm) afterwards, the frequency deviation of modulator (fm) can be from second value of first value transform of video when (R) when resetting (P), and only during the carrier chrominance signal existence, start modulator (fm) by horizontal synchronization pulse ss;
Digital frequency modulator (fm) is second digital filter (df2) afterwards, its characteristic can be when resetting (P) bell bell when being transformed to video (R), the output of filter (df2) is connected to the input of the second index zone bandpass filter (nb2) through the first input and output path of the 8th electronic commutator (u8) when the Sequential Color and Memory system formula; When PAL or TSC-system formula, the second input and output path of change over switch (u8) is connected the output of first interpolater (ip1) with the input of the second index zone bandpass filter nb2.
7, claim 2 or claim 6 described video tape recorders is characterized in that, the first index zone bandpass filter (nb1) has following transfer function for the frequency (FC) of sampled signal (fc):
H（Z）＝ (（1＋Z－10）（1－Z－8）（1＋Z－6）)/(（1＋Z－2）3) ，
Wherein, (a 1+Z
-6) be to realize (a 1+Z by sampler (dz) back
※-2) parallel circuit realize that this must be to go up and could set up in the frequency of the sampled signal of sampler (dz) (f1) (F1).
8, claim 2,6 or 7 described video tape recorders is characterized in that, signal formation band pass filter (fb) has following transfer function for the frequency (F1) of its sampled signal (f1):
H（Z）＝（1-Z
-2）
5（0.375+Z
-2）（1+0.375Z
-2）。
9, any one described video tape recorder in claim 2 or the claim 6 to 8 is characterized in that, first interpolater (ip1) has following transfer function for sampling frequency (FC):
H（Z）＝ (（1＋Z
－2）（1＋Z
－4）（1＋Z
－6）
2)/(（1＋Z）
2) ，
Wherein, (a 1-Z
-2) be to realize with a digital multiplier (mx).
10, from 1 to 9 the described video tape recorder of any one claim, all be the minimum feature that is combined as with digital sine wave generator (sg1, sg2), (sg2) among the digital sine wave generator among Fig. 2 (sg1) and Fig. 5 has relevant multiplier (m2 and m5) respectively;
First or second digital signal (ds1, ds2) and sampled signal (fc) are added on the j bit digital accumulator (ak);
Q little position of ratio (j-2) position in the output signal of accumulator ak, be to send by each inverter of the second multichannel inverter (vi2), here q is less than or equal to j-2, the input of anti-phase (vi2) is connected to the first input end of each switch of second variable connector (vu2), and second input of these switches is connected to the output separately of each inverter, and the common control input end of these switches is connected to (j-1) bit accumulator output;
The output of second variable connector (vu2) is connected to the address input end of additional read-only memory (rm '), memory (rm ') is storing the sine value of first quartile, and its output is connected to the first input end of second multiplier (m2) or the 5th multiplier (m5);
The output of the second or the 5th multiplier (m2, m5), each is connected on the inverter of the 3rd multichannel inverter (vi3), the input of these inverters is also connected to the first input end of each switch of the 3rd variable connector (vu3), and second input of these switches is connected to the output of these inverters, the common control input end of these switches is connected to the j position output of accumulator (ak), and the output of the 3rd variable connector (vu3) is connected to the input of the one 90 ° of phase-shifter (h1) or second adder (a2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN85101451.8A CN1003906B (en) | 1985-04-01 | 1985-04-01 | Video recorder with magnetic recording medium in the form of tape |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN85101451.8A CN1003906B (en) | 1985-04-01 | 1985-04-01 | Video recorder with magnetic recording medium in the form of tape |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN85101451A true CN85101451A (en) | 1987-01-17 |
| CN1003906B CN1003906B (en) | 1989-04-12 |
Family
ID=4791851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN85101451.8A Expired CN1003906B (en) | 1985-04-01 | 1985-04-01 | Video recorder with magnetic recording medium in the form of tape |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1003906B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111275952A (en) * | 2019-02-01 | 2020-06-12 | 奥克斯空调股份有限公司 | Wireless communication system and air conditioner direct current motor power supply system using same |
-
1985
- 1985-04-01 CN CN85101451.8A patent/CN1003906B/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111275952A (en) * | 2019-02-01 | 2020-06-12 | 奥克斯空调股份有限公司 | Wireless communication system and air conditioner direct current motor power supply system using same |
| CN111275952B (en) * | 2019-02-01 | 2021-05-18 | 奥克斯空调股份有限公司 | Wireless communication system and air conditioner direct current motor power supply system using same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1003906B (en) | 1989-04-12 |
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