Summary of the invention
The purpose of this utility model provides a kind of wireless digital single channel or multi-channel video, voice, data move transmitting device, can select different frequency ranges multi-channel video, voice-and-data being stopped that carrying out the real non-destructive consumption under environment and the high-speed moving state transmits easily with the speed that is not less than 6Mpbs, this device is provided with and encrypts mouth simultaneously, by the change at any time of external key, guarantee the safety of whole link.
For achieving the above object, the utility model provides single channel and two kinds of transmitting devices of multichannel, and concrete technical scheme is as follows:
A kind of wireless digital single channel video, voice, data move transmitting device, it is characterized in that: comprise single channel front end digital collection transmitter and terminal digital receiver composition; Single channel front end digital collection transmitter is by MPEG-II encoder (1), packing data machine (2), multiplexer (3), COFDM modulator (5), upconverter (6), tunable oscillator (7), power amplifier (8), transmitting antenna (9), single-chip microcomputer (10) is formed, plug into field camera or the A/V output of A/V signal is provided of MPEG-II encoder (1) input wherein, packing data machine (2) input connects the IP data, byte stream, bit stream output, MPEG-II encoder (1) output and packing data machine (2) output connect multiplexer (3) input, multiplexer (3) output connects COFDM modulator (5) input, COFDM modulator (5) and tunable oscillator (7) output connect frequency converter (6) input, upconverter (6) output connects power amplifier (8) input, antenna (9) is penetrated in power amplifier (8) output sending and receiving, and single-chip microcomputer (10) output connects MPEG-II encoder (1) respectively, multiplexer (3), COFDM modulator (5) input;
Terminal numeral receiver circuit is by reception antenna (11A), AGC amplifies and low-converter (13), qpsk demodulator (18)/COFDM demodulator (14), deciphering module (19), demodulation multiplexer (20), MPEG-II decoder (15), data transit plate (21) and center processor (16) are formed, its annexation is that reception antenna (11A) output connects AGC amplification and low-converter (13) input, AGC amplifies and low-converter (13) output connects QPSK (18) or COFDM demodulator (14) input, the output of QPSK/COFDM demodulator connects demultiplexing output and connects MPEC-II decoding input, MPEC-II decoding output analogue AV signal, data transit plate output IP data, byte stream and bit stream, center processor connect the AGC amplifier respectively, down-conversion, the QPSK/COFDM demodulator, demodulation multiplexer, the input of MPEG-II decoder.
A kind of wireless digital multi-channel video, voice, data move transmitting device, it is characterized in that: comprise multichannel front end digital collection transmitter and terminal digital receiver composition; Multichannel front end digital collection transmitter comprises that front end receives and gather emission two parts;
A, the circuit of front end receiving unit comprises reception antenna (11), radio frequency distributor (12), AGC amplifies and low-converter (13), COFDM demodulator (14), MPEG-II decoder (15), center processor (16), its annexation is that reception antenna output connects the input of radio frequency distributor, the output of radio frequency distributor connects AGC amplification and low-converter input, AGC amplifies and low-converter output connects the input of COFDM demodulator, the output of COFDM demodulator connects the input of MPEG-II decoder, and center processor meets AGC respectively and amplifies and low-converter, the COFDM demodulator, the input of MPEG-II decoder;
B, gather radiating portion and comprise digital switcher (22), MPEG-II encoder (1), packing data machine (2), multiplexer (3), encrypting module (4), COFDM modulator (5), upconverter (6), tunable oscillator (7), power amplifier (8), transmitting antenna (9), single-chip microcomputer (10), its annexation is a plurality of inputs that the MPEG-II decoder output of a plurality of front end receiver parts connects digital switcher, A/V in field camera or other circuit exports the MPEG-II encoder input of plugging into, the input of packing data machine connects the IP data, byte stream, bit stream output, digital switcher, the output of MPEG-II encoder and packing data machine connects the multiplexer input, multiplexer output connects the encrypting module input, encrypting module output connects COFDM modulation input, COFDM modulator and tunable oscillator output connect the frequency conversion input, up-conversion output connects the power amplifier input, antenna is penetrated in power amplifier output sending and receiving, and single-chip microcomputer output connects the MPEG-II encoder respectively, multiplexer, the input of COFDM modulator;
Terminal numeral receiver circuit is by reception antenna (11A), AGC amplifies and low-converter (13), qpsk demodulator (18)/COFDM demodulator (14), deciphering module (19), demodulation multiplexer (20), MPEG-II decoder (15), data transit plate (21) and center processor (16) are formed, its annexation is that reception antenna (11A) output connects AGC amplification and low-converter (13) input, AGC amplifies and low-converter (13) output connects QPSK (18) or COFDM demodulator (14) input, the output of QPSK/COFDM demodulator connects demultiplexing output and connects MPEC-II decoding input, MPEC-II decoding output analogue AV signal, data transit plate output IP data, byte stream and bit stream, center processor connect the AGC amplifier respectively, down-conversion, the QPSK/COFDM demodulator, demodulation multiplexer, the input of MPEG-II decoder.
The utility model is by front end digital collection transmitter, numeral transfering the letter retransmitter and terminal digital receiver are formed, front end digital collection transmitter is divided into two kinds in single channel front end digital collection transmitter and multichannel front end digital collection transmitter, single channel front end digital collection transmitter can be gathered one road video at most, two-way voice and a circuit-switched data signal are simultaneously to multichannel front end digital collection transmitter or the emission of terminal digital receiver, multichannel front end digital collection transmitter can be with the video of self gathering on the basis that receives a plurality of single channel front end digital collection transmitters, voice, data-signal one number of terminals word receiver emission in the same way, all front end digital collection transmitters all can be transmitted radiofrequency signal to the terminal digital receiver by numeral transfering the letter retransmitter when distance terminal digital receiver is far away, so just can satisfy the long-range needs that pass on.
Operation principle of the present utility model is that the AV signal is by external camera acquisition, the MPEGII encoder compresses that enters single channel front end digital collection transmitter is encoded into TS stream, with convert to through packing data machine packing bit stream, byte stream, IP data-signal behind the TS stream together multiplexing after, through secret key encryption, become the IF signal through the COFDM modulators modulate again, by upconverter and tunable oscillator the IF signal is changed to required RF frequency, amplify through power amplifier, launch to terminal digital receiver or numeral transfering the letter retransmitter by transmitting antenna.When the packing data machine, when multiplexer and encrypting module are unwanted, the RF signal of single channel front end digital collection transmitter can be received by the reception antenna of multichannel front end digital collection transmitter, enter a plurality of front end receiving units of multichannel front end digital collection transmitter respectively through the radio frequency distributor, a front end receiving unit is sent 1 road RF signal into the AGC amplifier, be downconverted into the medium-frequency IF signal, solve TS by the COFDM demodulator again and flow to decoder into MPEGII, exporting one the tunnel looks, audio signal is given monitor, simultaneously the MPEGII decoder is also exported one road TS and is flow to the digital switcher of gathering radiating portion and mix switching, digital switcher switches the TS that and flows, and enters multiplexer and carries out multiplexing; Bit stream, byte stream, IP data-signal also can be converted to TS stream by the packing data machine and send into multiplexer simultaneously; The video of the camera acquisition of directly plugging into, the voice signal TS stream of output behind MPEGII encoder compresses coding is also sent into multiplexer, output one tunnel high speed TS flowed after all entered multiplexer multichannel TS stream signal multiplexing, become the IF signal through the user key encryption with the COFDM modulators modulate, by upconverter and tunable oscillator the IF signal is changed to required frequency RF signal, go out by transmission antennas transmit through power amplifier.The RF signal of numeral transfering the letter retransmitter reception antenna receiving front-end digital collection transmitter, through AGC amplifier and low-converter, output IF signal, pass through the COFDM demodulator again, output TS stream directly enters qpsk modulator and is modulated into the IF signal, by upconverter and tunable oscillator the IF signal is changed to required RF frequency again, amplify the back through power amplifier and launch by the emission sky.Terminal digital receiver RF signal advances the AGC amplifier by reception antenna, be downconverted into the medium-frequency IF signal, (the terminal digital receiver is if then select the COFDM demodulator when directly receiving signal from front end digital collection transmitter for use by QPSK or COFDM demodulator again, qpsk demodulator is selected in reception during from the signal of numeral transfering the letter retransmitter for use) solve TS stream, become TS stream and data-signal output through demultiplexing again after sending into the decoder module decryption key, TS stream is sent into the MPEG-II decoder and is decompressed, and the output simulation is looked, audio signal.When the signal of current terminal number word collection transmitter and the emission of numeral transfering the letter retransmitter is multichannel, should disposes radio frequency distributor and a plurality of terminal digital receiver and be received demonstration and utilization.
The beneficial effects of the utility model are: adopt the modulation system of Coded Orthogonal Frequency Division Multiplexing (COFDM), overcome multipath and disturbed and reduced the error rate, can guarantee video, voice-and-data is in high-speed mobile and stop the stable wireless transmission of realization in the environment; Adopt the digital compression coded system, the video image of available less bandwidth for transmission clear and smooth; Tranmitting frequency is controlled by external controller, and the receiving terminal frequency is provided with by software, all can adjust at any time; IP data, bit stream, byte stream convert after the transport stream transport stream with video, voice in time-multiplexed mode, and compound is that one tunnel high-speed transfer code stream transmits, and has saved resource; Front end and terminal are equipped with encrypting module, can externally change key, the fail safe that improves whole transmission channel at any time; By multichannel front end digital collection transmitter the TS of different single channel front end digital collection transmitter collections stream signal is carried out numeral switching and multiplexing, can be from the situation of the same love scene of arbitrarily angled reaction; The terminal digital receiver can receive the signal of single channel front end digital collection transmitter, multichannel front end digital collection transmitter and numeral transfering the letter retransmitter, by different combinations, can satisfy the needs of different environments for use flexibly.
Embodiment
The Chinese of relevant English place abbreviation is explained in the utility model:
MPEG-II: one of (moving image and acoustic coding) international standard of motion picture expert group promulgation;
AGC amplifier: automatic gain control amplifier;
RS-232: a kind of single-ended standard that in the low rate serial communication, increases communication distance;
SDI: serial digital interface;
QPSK: quadrature phase modulation system;
COFDM: Coded Orthogonal Frequency Division Multiplexing (COFDM) modulation system;
RF: radiofrequency signal;
IF: intermediate-freuqncy signal;
TS stream: transmitting data stream;
IS stream: digital TV transmission stream;
I/O signal: input/output signal;
A/D converter: analog/digital signal conversion device;
D/A converter: digital/analog signal transducer;
A/V: audio/video signal;
L: L channel;
R: R channel;
V: video.
In Fig. 1, the utility model is by front end digital collection transmitter, numeral transfering the letter retransmitter and terminal digital receiver are formed, front end digital collection transmitter is divided into two kinds in single channel front end digital collection transmitter and multichannel front end digital collection transmitter, single channel front end digital collection transmitter can be gathered one road video at most, two-way voice and a circuit-switched data signal are simultaneously to multichannel front end digital collection transmitter or the emission of terminal digital receiver, multichannel front end digital collection transmitter can be with the video of self gathering on the basis that receives a plurality of single channel front end digital collection transmitters, voice, data-signal one number of terminals word receiver emission in the same way, all front end digital collection transmitters all can send radiofrequency signal to the terminal digital receiver by numeral transfering the letter retransmitter when distance terminal digital receiver distance is far away.
In Fig. 2, shown in single channel front end digital collection transmitter by MPEG-II encoder (1), packing data machine (2), multiplexer (3), encrypting module (4), COFDM modulator (5), upconverter (6), tunable oscillator (7), power amplifier (8), transmitting antenna (9), single-chip microcomputer (10) is formed, packing data machine (2) wherein, multiplexer (3), encrypting module (4) is a selectable unit, its connected mode is plug into A/V output in field camera or other circuit of MPEG-II encoder input, the input of packing data machine connects data-signal output, output of MPEG-II encoder and the output of packing data machine connect the multiplexer input, multiplexer output connects the encrypting module input, encrypting module output connects the input of COFDM modulator, COFDM modulator and tunable oscillator output connect the frequency conversion input, up-conversion output connects the power amplifier input, antenna is penetrated in power amplifier output sending and receiving, and single-chip microcomputer output connects the MPEG-II encoder respectively, multiplexer, the input of COFDM modulator.
In Fig. 3, shown in multichannel front end digital collection transmitter receive and gather emission two parts by front end and form: the circuit of front end receiving unit comprises reception antenna (11), radio frequency distributor (12), AGC amplifies and low-converter (13), COFDM demodulator (14), MPEG-II decoder (15), center processor (16), its annexation is that reception antenna output connects the input of radio frequency distributor, the output of radio frequency distributor connects the input of AGC amplifier, the output of AGC amplifier connects the down-conversion input, down-conversion output connects the input of COFDM demodulator, the output of COFDM demodulator connects the input of MPEG-II decoder, and center processor meets AGC respectively and amplifies and low-converter, the COFDM demodulator, the input of MPEG-II decoder; The circuit of gathering radiating portion comprises digital switcher (17), MPEG-II encoder (1), packing data machine (2), multiplexer (3), encrypting module (4), COFDM modulator (5), upconverter (6), tunable oscillator (7), power amplifier (8), transmitting antenna (9), single-chip microcomputer (10), its annexation is an input of the MPEG-II decoder output digital switcher of a front end receiver part, A/V in field camera or other circuit exports the MPEG-II encoder input of plugging into, the input of packing data machine connects data-signal output, digital switcher, the output of MPEG-II encoder and packing data machine connects the multiplexer input, multiplexer output connects the encrypting module input, encrypting module output connects COFDM modulation input, COFDM modulator and tunable oscillator output connect the frequency conversion input, up-conversion output connects the power amplifier input, antenna is penetrated in power amplifier output sending and receiving, and single-chip microcomputer output connects the MPEG-II encoder respectively, multiplexer, the input of COFDM modulator.
In Fig. 4, shown in numeral transfering the letter retransmitter by reception antenna (11), AGC amplifies and low-converter (13), COFDM demodulator (14), qpsk modulator (17), upconverter (6), tunable oscillator (7), power amplifier (8), transmitting antenna (9), center processor (16) is formed, its annexation is that reception antenna output connects AGC amplification and low-converter input, AGC amplifies and low-converter output connects the input of COFDM demodulator, the output of COFDM demodulator connects the qpsk modulator input, qpsk modulator and tunable oscillator output connect the frequency conversion input, up-conversion output connects the power amplifier input, antenna is penetrated in power amplifier output sending and receiving, and center processor connects the AGC amplifier respectively, down-conversion, the COFDM demodulator, the qpsk modulator input.
In Fig. 5, shown in terminal numeral receiver circuit by reception antenna (11), AGC amplifies and low-converter (13), qpsk demodulator (18)/COFDM demodulator (14), deciphering module (19), demodulation multiplexer (20), MPEG-II decoder (15), center processor (16) is formed, its annexation is that reception antenna output connects AGC amplification and low-converter input, AGC amplifies and the low-converter input and output connect QPSK/COFDM demodulation input, QPSK/COFDM demodulation output connects the deciphering module input, deciphering module output connects the demultiplexing input, demultiplexing output connects MPEC-II decoding input, MPEC-II decoding output analogue AV signal, center processor connects the AGC amplifier respectively, down-conversion, the QPSK/COFDM demodulator, demodulation multiplexer, the input of MPEG-II decoder.
In Fig. 6, shown in single channel front end digital collection transmitter MPEG-II encoder (1) by A/D converter (SAA711) 1., MPEG-II source encoder (PCM1800E) 2., MPEG-II channel encoder (TMS320VC5421) 3., scm software solidify integrated package (AT89C2015) 4., center processor (FL4472) 5. constitutes; Packing data machine (2) by bit stream, byte stream, IP data packet device (BL2005I36) 6., package transmission stream transformer (BL2005I37) 7. constitutes; Multiplexer (3) by buffer (IDT72V2113) 8., buffer (IDT72V2113)
Digital signal processor (TMS320C5402) 9., memory (IDT72V2113) 10., master control logic circuit (XC9571)
Scm software solidifies integrated package (AT89C2051-24C3)
Constitute; Encrypting module (4) is made of digital encryption device (BL2005I31) ; COFDM modulator (5) is made of carrier wave conversion, multistage modulation, the error correction of outer sign indicating number, ISN error correction, interweaving encoding, COFDM modulation, AGC amplification, IF amplifier integrated block (L64733134) ; Upconverter (6) is made of balanced mixer (PH1002) and high-frequency amplifier (BTR91A) ; Tunable oscillator (7) is made of oscillator (BL2005I38) ; Power amplifier (8) is by high-frequency amplifier (BTR91A) , high-frequency amplifier (BTR581) , distributor (3db)
Power amplifier (2N5212)
Power amplifier (2N5212)
And synthesizer (V)
Constitute; Transmitting antenna (9) is by omnidirectional transmitter antenna (BL2005313B)
Constitute; Single-chip microcomputer (10) is by Single-chip Controlling software (AT89C2051-24PI)
Constitute; Its annexation is that the IS that 2. IS
stream output pin 13~16 1. connects flows
input pin 4,6,7,11, the signal that 5. signal
storage processing pin 18~21 connects is stored processing pin 108,109,111,112,2. IS
stream output pin 27~35 connects IS stream input pin 45~53 3., the signal that 5. signal
storage processing pin 2,3,5,8,10,14,16~20 connects is
stored processing pin 88~98, and TS
stream output pin 33~42 3. connects
TS
stream input pin 21~30, the signal that 5. signal
storage processing pin 2,4,6~9,15,17~23 connects is stored processing pin 52~61,65~68,5. software control pin 117~121 is connected with 4.
software output pin 14~18,6. package
signal output pin 12~16 connects package
signal input pin 4~9 7., 7. TS
stream output pin 26~35 connects TS
stream input pin 21~30 8., 8. and
TS
stream output pin 11~20 connect 9. TS
stream input pin 30~39 and 71~80 respectively,
logic control pin 2~5,7,8 connects respectively
Logic control pin 10~15 and 21~26, TS output pin 115~124 9. connects TS
stream input pin 21~30 10., logic control pin 95~98,102~107 connects
Logic control pin 83~92,10. TS
stream output pin 11~20 connects the TS
stream input pin 24~33 of ,
logic control pin 2~5,7,8 connects respectively
Logic control pin 62~67, the TS of
stream output pin 12~23 connects the
TS input pin 48,49,51~60 of , the
IF output pin 82 of connects the
IF input pin 1 of , data processing and software control pin 97~100 connect
Software output pin 14~18, the
vibration input pin 2 of meets , grounding
leg 4 ground connection, radio
frequency output pin 3 connects the input of , the output pin of connects the input pin of , the output pin of the input pin , of the output pin Jie of connects
Input pin 1,
Output pin 3,4 connect respectively
With
Input pin,
pin 2 ground connection,
With
Output pin connect respectively
Input
pin 1 and 2,
Output pin 3
connect
4 ground connection.
In Fig. 7, shown in the reception antenna (11) of multichannel front end digital collection transmitter front ends receiving unit by isotropic receiving antenna (BL2005313A)
Form; Radio-frequency allotter (12) is by radio frequency shunt (ADA4302-4)
Form; (GH4112) forms by High frequency amplification, down coversion, L10RF integrated package for AGC amplification and low-converter (13); COFDM demodulator (14) COFDM demodulation, decoding, deinterleaving integrated package (L64781)
Form; MPEG-II decoder (15) is by decompress(ion), decoding integrated package (GM71V8163C)
Separate output integration block (D451616AG5) with D/A conversion, A/V
Form; Center processor (16) is by center processor integrated package (sti5518)
Form; Gather the digital switcher (22) of radiating portion by digital switcher (BL2005I35)
Form; MPEG-II encoder (1) by A/D converter (SAA711) 1., MPEG-II source encoder (PCMl800E) 2., MPEG-II channel encoder (TMS320VC5421) 3., scm software solidify integrated package (AT89C2015) 4., center processor (FL4472) 5. forms; Data baling press (2) by bit stream, byte stream, IP data packet device (BL2005I36) 6., package transmission stream transformer (BL2005I37) 7. forms; Multiplexer (3) by buffer (IDT72V2113) 8., buffer (IDT72V2113)
Buffer (IDT72V2113)
Digital signal processor (TMS320C5402) 9., memory (IDT72V2113) 10., master control logic circuit (XC9572)
Scm software solidifies integrated package (AT89C205)
Form; Encrypting module (4) consists of digital encryption device (BL2005I31) ; COFDM modulator (5) consists of carrier wave conversion, multi-level modulation, outer code error correction, ISN error correction, interweaving encoding, COFDM modulation, AGC amplification, IF amplifier integrated block (L64733134) ; Upconverter (6) consists of balanced mixer (PH1002) and high-frequency amplifier (BTR91A) ; Tunable oscillator (7) consists of oscillator (BL2005I38) ; Power amplifier (8) is by high-frequency amplifier (BTR91A) , high-frequency amplifier (BTR581) , distributor (3db)
Power amplifier (2N5212)
Power amplifier
And synthesizer (V)
Form; Transmitting antenna (9) is by omnidirectional transmitter antenna (BL2005313B)
Form; Single-chip microcomputer (10) is by Software in Single Chip Microcomputer Control (AT89C2051-24C2)
The annexation of front end receiving unit is
RF output connect
RF input,
1 a road RF output pin front end connecing multichannel front end digital collection emitter connect the RF input pin 3 of receiving portions , the dual IF output pin 11,12 of connects
Intermediate frequency input pin 61,62, online input pin 3 frequently connects
Pin 176,
TS output pin 51~54,58 connect
TS input pin 30~33,38, data store to be processed pin 21,22,28~30 and are connect
Data store to process pin 128~132,
Data store to process pin 2~5,9~15,17~20 and connect
Data store to process pin 114~126,128,131,
Data store to process pin 2~7,9,10,12~18,23~28,93,94 and connect
Data store to process pin 42~47,53~56,73~79,82~88, TS stream output pin 65~72,74,77 connects multichannel front end digital collection emitter and gathers radiating portion
TS stream input pin 22~31; The annexation that gathers radiating portion is
TS stream output pin 53~62 connect
TS stream input pin 21~30, 6. package
signal output pin 12~16 connects package
signal input pin 4~9 7., 7. TS
stream output pin 26~35 connects TS
stream input pin 21~30 8., 1. IS
stream output pin 13~16 connects IS
stream input pin 4 2., 6, 7, 11, the signal that 5. signal
storage processing pin 18~21 connects is stored
processing pin 108, 109, 111, 112, 2. IS
stream output pin 27~35 connects IS stream input pin 45~53 3., signal is stored and is processed
pin 2, 3, 5, 8, 10, 14, 16~20 signals that connect are 5. stored
processing pin 88~98, 3. IS
stream output pin 33~42 connects
TS
stream input pin 21~30, signal is stored and is processed
pin 2,4,6~9,15,17~23 and connect 5. signal and store and process pin 52~61,65~68, software control pin 117~121 5. is connected with 4.
software output pin 14~18,8.,
With
Buffer
memory output pin 11~20 connect respectively 9. buffer
memory input pin 30~39,45~54 and 71~80,
logic control pin 2~5,7,8 connects respectively
Logic control pin 10~15,18~24 and 26~31, TS output pin 115~124 9. connects TS
stream input pin 21~30 10., logic control pin 95~98,102~107 connects
Logic control pin 83~92,10. TS
stream output pin 11~20 connects the TS
stream input pin 24~33 of ,
logic control pin 2~5,7,8 connects respectively
Logic control pin 62~67,
Software control pin 44~48 with
Software output pin 23~27 connects, and the TS
stream output pin 12~23 of connects the
TS input pin 48,49,51~60 of , and the
IF output pin 82 of connects the
IF input pin 1 of , and data are processed and software control pin 97~100 connects
Software output pin 14~18, the
vibration input pin 2 of meets , grounding
leg 4 ground connection, radio
frequency output pin 3 connects the input of , the output pin of connects the input pin of , the output pin of the input pin , of the output pin Jie of connects
Input pin 1,
Output pin 3,4 connect respectively
With
Input pin,
pin 2 ground connection,
With
Output pin connect respectively
Input
pin 1 and 2,
Output pin 3
connect 4 ground connection.
In Fig. 8, shown in the reception antenna (11) of numeral transfering the letter retransmitter by isotropic receiving antenna (BL2005313A)
Constitute; (GH4112) constitutes by high frequency amplification, down-conversion, L10RF integrated package for AGC amplification and low-converter (13); COFDM demodulator (14) COFDM demodulation, decoding, deinterleaving integrated package (L64781)
Constitute; Qpsk modulator (17) is by D/D isolator (74HC245)
RS coding, interweaving encoding, filtering phase shift, QPSK modulation, AGC, IF amplifier integrated block (BCM3033)
Constitute; Upconverter (6) is made of balanced mixer (PH1002) and high-frequency amplifier (BTR91A) ; Tunable oscillator (7) is made of oscillator (BL2005I38) ; Power amplifier (8) is by high-frequency amplifier (BTR91A) , high-frequency amplifier (BTR581) , distributor (3db)
Power amplifier (2N5212)
Power amplifier
And synthesizer (V)
Constitute; Transmitting antenna (9) is by omnidirectional transmitter antenna (BL2005313B)
Constitute; Center processor (16) is by center processor integrated package (sti5518)
Constitute.Its annexation is
The dual IF output pin 11,12 of RF input , of RF Shu Chu Jie connect
Intermediate frequency input pin 61,62, online frequency input pin 3 connects
Pin 176,
TS output pin 51~54,58 connect
TS input pin 27~29,31~35, data storage is handled pin 21,22,28~30 and is connect
Data storage handle pin 28,29~31,33,
TS output pin 2~10,12~14 connect
TS input pin 50~60,62,
IF output pin 84 connect the IF input pin 1 of , data storage is handled pin 97~100 and is connect
Data storage handle pin 142~146, the vibration input pin 2 of meets , grounding leg 4 ground connection, radio frequency output pin 3 connects the input of , the output pin of connects the input pin of , the output pin of the input pin , of the output pin Jie of connects
Input pin 1,
Output pin 3,4 connect respectively
With
Input pin, pin 2 ground connection,
With
Output pin connect respectively
Input pin 1 and 2,
Output pin 3 connect
4 ground connection.
In Fig. 9, shown in the reception antenna (11) of terminal digital receiver by isotropic receiving antenna (BL2005313A)
Constitute; (GH4112) constitutes by high frequency amplification, down-conversion, L10RF integrated package for AGC amplification and low-converter (13); Qpsk demodulator (18) by the QPSK demodulation, separate RS, deinterleaving integrated package (BCM3118)
Constitute; Deciphering module (19) is by digital decrypted device (BL2005I32)
Constitute; Demodulation multiplexer (20) is by buffer (IDT72V2113)
Digital signal processor (TMS320C5402)
Master control logic circuit (XC9572)
Memory (IDT72V2113)
Memory (IDT72V2113)
Constitute; MPEG-II decoder (15) is by decompress(ion), decoding integrated package (GM71V8163C)
Separate output integration block (D451616AG5) with D/A conversion, A/V
Constitute; Data transit plate (21) is by transport stream transit plate (BL200580B)
Constitute; Center processor (16) is by center processor integrated package (sti5518)
Constitute.Its annexation is
The dual IF output pin 11,12 of RF input , of RF Shu Chu Jie connect
Intermediate frequency input pin 61,62, online frequency input pin 3 connects
Pin 176,
IS output pin 49~51,53~57 connect
IS input pin 21~27, data storage is handled pin 33,35,37,40,41 and is connect
Data storage handle pin 15~18,20,
TS output pin 43~52 connect
TS input pin 21~30,
Buffer memory output pin 11~20 connect
Buffer memory input pin 30~39, logic control pin 2~5,7,8 connects
Logic control pin 21~26,
TS flow 1 output pin 115~124 and connect
TS flows input pin 21~30, and TS flows 2 output pins 125~134 and connects
TS flows input pin 21~30, and logic control pin 95~98,102,104~108 connects
Logic control pin 83~85,92~98,
TS stream output pin 11~20 connects
TS flows input pin 30~39, and logic control pin 2~5,7,8 connects
Logic control pin 62~67,
TS stream output pin 11~20 connects
TS flows input pin 34~36,42~49, and logic control pin 2~5,7,8 connects
Logic control pin 73~78,
Data storage handle pin 2~5,9~15,17~20 and connect
Data storage handle pin 114~126,128,131,
Data storage handle pin 2~7,9,10,12~18,23~28,93,94 and connect
Data storage handle pin 42~47,53~56,73~79,82~88.