CN2807631Y

CN2807631Y - E1/V.35 protocol conversion equipment

Info

Publication number: CN2807631Y
Application number: CN 200520113491
Authority: CN
Inventors: 石美荣
Original assignee: Individual
Current assignee: Individual
Priority date: 2005-07-14
Filing date: 2005-07-14
Publication date: 2006-08-16
Anticipated expiration: 2015-07-14

Abstract

The utility model discloses E1/V. 35 protocol conversion equipment which is characterized in that a chip of an E1/V. 35 protocol converter adopts a large-scale integrated circuit FPGA which has advantages of simple circuit and stable and reliable performance. The E1/V. 35 protocol conversion equipment has advantages of abundant interface and strong versatility. A front panel of a machine case is provided with an eight-bit function switch and eight state indicator lights. The utility model has perfect working mode setting and a state indication function.

Description

The E1/V.35 protocol conversion device

Technical field

The utility model relates to a kind of communication Protocol Conversion equipment.

Background technology

Present E1/V.35 protocol conversion device mostly is to adopt the puppy parc conversion chip, the peripheral circuit complexity, and interface is single, configuration is difficult, and versatility is poor.

Summary of the invention

A kind of E1/V.35 protocol conversion device that the utility model designs in order to solve the problems of the technologies described above just based on large scale integrated circuit FPGA.

The technical scheme that its technical problem that solves the utility model adopts is:

A kind of E1/V.35 protocol conversion device, comprise cabinet, mainboard, E1/V.35 protocol conversion chip, functional switch and interface circuit, it is characterized in that: E1/V.35 protocol conversion chip adopts large scale integrated circuit FPGA customization, and inside comprises E1 and protocol conversion module V.35, E1 interface module, V.35 interface module, state input module and state output module; The E1 holding wire links to each other with mainboard with RJ-45 connector by the BNC connector on the cabinet rear board, and V.35 holding wire links to each other with mainboard by the DB25 joint on the cabinet rear board, can realize E1 and the V.35 conversion and the bridge joint of agreement easily.

E1/V.35 protocol conversion chip FPGA has 8 state input pins to link to each other with 8 bit function switches on the case front panel respectively on the mainboard, is used to dispose mode of operation, the interface type of E1/V.35 protocol conversion device.E1/V.35 protocol conversion chip FPGA has 8 state output pins to link to each other with 8 indicator lights on the case front panel respectively on the mainboard, the operating state and the alarm of indication E1/V.35 protocol conversion device.

The beneficial effects of the utility model are to adopt large scale integrated circuit, and circuit is simple, and are stable, reliable; Rich interface, highly versatile; Master clock, optional from clock and three kinds of clock modes of external clock is provided; Possess perfect alarm and state deixis.

Description of drawings

Fig. 1 is the utility model main board functional module schematic diagram.

Fig. 2 is the utility model case front panel structural representation.

Fig. 3 is the utility model cabinet rear panel structure schematic diagram.

Embodiment

Below in conjunction with drawings and Examples the utility model is further specified.

Shown in Fig. 1,2 and 3, be that a specific embodiment HR2000A:E1/V.35 of the utility model protocol conversion chip adopts large scale integrated circuit FPGA customization, inside comprises E1 and protocol conversion module V.35, E1 interface module, V.35 interface module, state input module and state output module; The E1 holding wire links to each other with mainboard with RJ-45 connector by the BNC connector on the cabinet rear board, and V.35 holding wire links to each other with mainboard by the DB25 joint on the cabinet rear board.E1/V.35 protocol conversion chip FPGA has 8 state input pins to link to each other with signal ground to eight resistance of R8 by R1 respectively on the mainboard, link to each other with power supply to eight switches of K8 by the K1 on the case front panel again simultaneously, wherein K switch 1 to K8 is that SW1.1 among the 8 bit switch group SW1 is to eight functional switches 1 of SW1.8.Specific targets are as follows:

1, major function:

● adopt large scale integrated circuit FPGA, circuit is simple, and is stable, reliable;

● one road E1 interface is provided, and impedance is 75 Ω/adjustable mode of 120 Ω;

● being BNC connector during E1 interface 75 Ω, is RJ-45 connector during 120 Ω, the inner setting;

● V.35 or the RS232 interface this equipment work is in the 2M transparent mode, provides 1 the tunnel;

● V.35 interface can connect DCE or DTE equipment, and the RS232 interface is the DCE working method;

● master clock, optional from clock and three kinds of clock modes of external clock is provided;

● possess perfect alarm and state deixis;

● adapt to multiple power environment-48VDC/220VAC;

2, technical parameter

● 2.12048Kbit/s (E1) electrical specification of interface

● nominal rate: 2048Kbit/s ± 50ppm;

● interface code type: HDB3;

● interface impedance: 75 Ω (imbalance) and 120 Ω (balance) mode are adjustable;

● digital interface electrical characteristic: meet the ITU-TG.703 suggestion;

● jitter transfer function: meet the ITU-TG.823 suggestion;

● input jitter tolerance: meet the ITU-TG.823 suggestion;

● output jitter: meet the ITU-TG.823 suggestion;

2048Kbit/s digital interface physical electrical characteristic conforms ITU-TG.703 suggestion;

● interface type: BNC 5---75 Ω, and RJ-45 6---120 Ω;

2.2V.35 interface

● nominal rate: 2048Kbit/s;

● no flow control, transparent transmission;

● the interface electric property meets V.35/V.11 requirement;

● interface type: DB25 hole seat;

● working method: DCE can connect the equipment of DTE or DCE working method;

2.3RS232 interface

● interface rate: asynchronous speed≤115200bit/s is (as 9.6K, 19.2K);

● interface level: RS232 level;

● working method: DCE;

● interface type: DB25;

2.4 power supply 3

● voltage: exchange AC220V AC 180V～240V;

● direct current DC-48V DC-36V～-72V;

● power consumption :≤5W.

3, SW1 functional switch 1 configuration

Table 1:SW1 functional switch 1

Switch		ON	OFF	Explanation
Switch		ON	OFF	Explanation	SW1	1	RS232	V.35
2	Clock module		See Table 2			1	RS232	V.35
2				3
4				3		It is anti-phase to send out clock	Send out the clock homophase	Only V.35 interface is effective
4	5	The receipts clock is anti-phase	Receive the clock homophase			It is anti-phase to send out clock	Send out the clock homophase
6	5	The receipts clock is anti-phase	Receive the clock homophase	The local terminal loopback		Operate as normal
6	7	Standby				Operate as normal
8	7	Standby				Software control	Hardware controls	For this equipment is invalid switch

Table 2: clock module is provided with table

SW1.2	SW1.3	Clock module	Explanation
SW1.2	SW1.3	Clock module	Explanation	ON	ON	Master clock
ON	OFF	External clock	Work in V.35 interface clock, do not have this clock pattern during RS232	ON	ON	Master clock
ON	OFF			OFF	OFF
OFF	ON			OFF	OFF	From clock	Work in and receive the E1 clock

4, indicator light 2 explanations

Table 3:HR2000A indicator light 2 implications:

Title	Color	The indicator light meaning	Normal condition
Title	Color	The indicator light meaning	Normal condition	PWR	Green	The device power supply (DPS) relay indicating light	Chang Liang
RA	Yellow	Opposite end E1 OOF alarm indicator	Go out	PWR	Green	The device power supply (DPS) relay indicating light	Chang Liang
RA	Yellow	Opposite end E1 OOF alarm indicator	Go out	E1	Green	E1 normally connects indicator light	Chang Liang
LOF	Red	E1 OOF indicator light	Go out	E1	Green	E1 normally connects indicator light	Chang Liang
LOF	Red	E1 OOF indicator light	Go out	TD	Green	V.35 or RS232 send out the data indicator light	Flicker or Chang Liang
RD	Green	V.35 or RS232 send out the data indicator light	Flicker or Chang Liang	TD	Green	V.35 or RS232 send out the data indicator light	Flicker or Chang Liang
RD	Green	V.35 or RS232 send out the data indicator light	Flicker or Chang Liang	LL	Yellow	Local terminal loopback indicator light	Go out
RL	Yellow	The remote loopback indicator light	Go out	LL	Yellow	Local terminal loopback indicator light	Go out

Claims

1, a kind of E1/V.35 protocol conversion device, comprise cabinet, mainboard, E1/V.35 protocol conversion chip, functional switch, indicator light and interface circuit, it is characterized in that: E1/V.35 protocol conversion chip adopts large scale integrated circuit FPGA customization, and inside comprises E1 and protocol conversion module V.35, E1 interface module, V.35 interface module, state input module and state output module; The E1 holding wire links to each other with mainboard with RJ-45 connector by the BNC connector on the cabinet rear board, and V.35 holding wire links to each other with mainboard by the DB25 joint on the cabinet rear board.

2, E1/V.35 protocol conversion device according to claim 1 is characterized in that: E1/V.35 protocol conversion chip FPGA has 8 state input pins to link to each other with 8 bit function switches on the case front panel respectively on the mainboard.