CN2779615Y - Wafer package - Google Patents
Wafer package Download PDFInfo
- Publication number
- CN2779615Y CN2779615Y CNU2005200015291U CN200520001529U CN2779615Y CN 2779615 Y CN2779615 Y CN 2779615Y CN U2005200015291 U CNU2005200015291 U CN U2005200015291U CN 200520001529 U CN200520001529 U CN 200520001529U CN 2779615 Y CN2779615 Y CN 2779615Y
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- Prior art keywords
- wafer
- encapsulation body
- fuel plate
- wire structure
- internal connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The utility model relates to a wafer packaging body, which comprises at least one wafer, an inner connecting line structure, a plurality of second connecting cushions and at least one plate-shaped element, wherein a plurality of first connecting cushions are arranged on one surface of the wafer, the inner connecting line structure is matched with the wafer and the first connecting cushions of the wafer are electrically connected with the inner connecting line structure. The second connecting cushions are matched with the inner connecting line structure, and the plate-shaped element is buried in the inner connecting line structure. In addition, a plurality of electrodes are arranged on two opposite surfaces of the plate-shaped element, and the second connecting cushions are electrically connected with the first connecting cushions via the inner connecting line structure and the plate-shaped element. The plate-shaped element is buried in the inner connecting line structure of the wafer packaging body, the plate-shaped element can be used for conducting an upper line and a lower line, the use of traditional peripheral electrode type passive elements can be reduced and thus the electrical quality of the wafer packaging body can be raised. The plate-shaped element can be also an active element, and the function of the wafer packaging body is enhanced.
Description
Technical field
The utility model relates to a kind of wafer encapsulation body, particularly relates to a kind ofly having the flush type fuel plate, and can improve the wafer encapsulation body of electrical quality.
Background technology
Along with electronic technology development with rapid changepl. never-ending changes and improvements, be many-sided requirements such as high speed processingization, multifunction, high productive setization (integration), miniaturization and and low priceization of strengthening electronic element, so the wafer package technology is also and then towards microminiaturization and densification development.Existing known ball pin trellis array (Ball Grid Array, BGA) encapsulation technology often adopts base plate for packaging (packagesubstrate) as the carrier (carrier) of integrated circuit (IC) wafer (IC chip) and utilize chip bonding (flip chip bonding) or routing joining technique electrical connection technologies such as (wire bonding), wafer is electrically connected to the end face of base plate for packaging, and many soldered balls (solder ball) are disposed at the bottom surface of base plate for packaging in face array (area array) mode.Therefore, wafer is able to a plurality of soldered balls via the internal wiring of base plate for packaging and bottom thereof, and is electrically connected to the electronic installation of next level, for example printed circuit board (PCB) etc.
Yet, because existing known BGA encapsulation technology must be utilized the base plate for packaging of high wiring density (high layoutdensity), and electric connection technology such as collocation chip bonding or routing joint, thereby cause the signal transmission path long.Therefore, developed at present a kind of bumpless formula increase the layer (Bumpless Build-Up a Layer, BBUL) wafer package technology, it has omitted the processing procedure of chip bonding or routing joint, and directly on wafer, make a multi-layer internal connection line (multi-layered interconnection structure), and, on multi-layer internal connection line, make electrical contacts such as soldered ball or stitch, in order to be electrically connected to the electronic installation of next level with the face array way.
Seeing also shown in Figure 1ly, is the generalized section that existing known bumpless formula increases the layer wafer packaging body.Should existing known bumpless formula increase layer wafer packaging body 100, comprise a supporting bracket (stiffener) 110, a wafer 120, an internal connection-wire structure 130, a sealing (encapsulant) 140 and a plurality of soldered ball 150, wherein, this supporting bracket 110 has an opening (opening) 110a, and wafer 120 is disposed in the opening 110a.In addition, sealing 140 is between the inwall of wafer 120 and opening 110a.This wafer 120 has a plurality of connection pads 122 on its active surface (active surface), and internal connection-wire structure 130 is to be disposed on the active surface of wafer 120, and electrically connects with connection pad 122.
More specifically, this internal connection-wire structure 130, comprise a plurality of dielectric layers (dielectric layer) 132, a plurality of line layer 134 and a plurality of conductions duct (conductive via) 134a, wherein these line layers 134 are to be overlapped in regular turn on wafer 120 and the supporting bracket 110, and these line layers 134 is to electrically connect with the connection pad 122 of wafer 120 via conduction duct 134a near wafer.In addition, 132 of these dielectric layers are disposed at respectively between the two adjacent line layers 134, and these conductions duct 134a runs through one of these dielectric layers 132 respectively, and electrically connect two line layers 134 at least.In addition, existing known bumpless formula increases layer wafer packaging body 100, more comprise a plurality of connection pads 160 and a welding cover layer (solder mask layer) 170, wherein, those connection pads 160 are to be disposed on the internal connection-wire structure 130, and welding cover layer 170 is to be disposed on the internal connection-wire structure 130, and exposes these connection pads 170.Moreover those soldered balls 150 are to be disposed at respectively on the connection pad 170.
From the above, though existing known bumpless formula increases layer wafer packaging body 100 and has better reliability degree and electrical property efficiency, yet along with the increase of wiring density and dwindling of line-spacing (line pitch), the cross-talk of the high-frequency signals that it transmitted (cross talk) phenomenon is also just more and more serious.In other words, the existing known bumpless formula electrical quality that increases layer wafer packaging body 100 also will be affected along with the increase of wiring density and dwindling of line-spacing.
This shows that above-mentioned existing wafer encapsulation body obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem that wafer encapsulation body exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that above-mentioned existing wafer encapsulation body exists, the design people is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of wafer encapsulation body of new structure, can improve general existing wafer encapsulation body, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the utility model that has practical value finally.
Summary of the invention
The purpose of this utility model is, overcome the defective that existing wafer encapsulation body exists, and provide a kind of new structure wafer encapsulation body, technical problem to be solved is to make it have the flush type fuel plate, and can improve electrical quality, thereby be suitable for practicality more.
The purpose of this utility model and to solve its technical problem be to adopt following technical scheme to realize.In order to reach aforesaid goal of the invention or other purposes, the utility model proposes a kind of wafer encapsulation body, it comprises at least one wafer, an internal connection-wire structure, a plurality of second connection pad and at least one fuel plate (panel-shape component), wherein, this wafer is to have a plurality of first connection pads on surface thereof, and internal connection-wire structure is to be disposed on the wafer, and these first connection pads of wafer are to electrically connect mutually with internal connection-wire structure.These second connection pads are to be disposed on the internal connection-wire structure, and fuel plate is to imbed (embedded) in internal connection-wire structure.In addition, fuel plate has a plurality of electrodes in it two relatively on the surface, and these second connection pads are via internal connection-wire structure and fuel plate and be electrically connected to these first connection pads of wafer.
The utility model compared with prior art has tangible advantage and beneficial effect.By technique scheme, the utility model wafer encapsulation body has following advantage at least: the utility model is that fuel plate is embedded in the internal connecting layer of wafer encapsulation body, and fuel plate not only can be as the usefulness of levels line conduction, more can reduce the use of the passive device of traditional peripheral electrode formula, and then can improve the electrical quality of wafer encapsulation body.In addition, fuel plate more can be an active member, can increase the function that wafer encapsulation body of the present utility model has.
In sum, the wafer encapsulation body of the utility model special construction, it has the flush type fuel plate, and can improve electrical quality, and in like product, do not see have the similar structures design to publish or use and really genus innovation, no matter it structurally or bigger improvement all arranged on the function, have large improvement technically, and produced handy and practical effect, and more existing wafer encapsulation body has the multinomial effect of enhancement, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solutions of the utility model, for can clearer understanding technological means of the present utility model, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present utility model can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the generalized section that existing known bumpless formula increases the layer wafer packaging body.
Fig. 2 is the generalized section according to the wafer encapsulation body of the utility model first embodiment.
Fig. 3 is the generalized section according to the wafer encapsulation body of the utility model second embodiment.
Fig. 4 is the generalized section according to the wafer encapsulation body of the utility model the 3rd embodiment.
Fig. 5 is the generalized section according to the wafer encapsulation body of the utility model the 4th embodiment.
100: existing known bumpless formula increases the layer wafer packaging body
110: supporting bracket 110a: opening
120: wafer 122,160: connection pad
130: internal connection-wire structure 132: dielectric layer
134: line layer 134a: the conduction duct
140: sealing 150: soldered ball
170: welding cover layer 200: wafer encapsulation body
210: supporting bracket 210a: opening
220: wafer 222,238: connection pad
230: internal connection- wire structure 232a, 232b, 232c: dielectric layer
234a, 234b: line layer 236: conduction duct
240: fuel plate 242: element layer
244: electrode 250: fin
260: electrical contact 270: welding cover layer
280: sealing 300: wafer encapsulation body
330: internal connection- wire structure 332a, 332b, 332c, 332d: dielectric layer
334a, 334b, 334c: line layer 336: conduction duct
340: fuel plate 410: wafer
412: connection pad 510: wafer
512: connection pad
Embodiment
For further setting forth the utility model is to reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, to according to its embodiment of wafer encapsulation body, structure, feature and the effect thereof that the utility model proposes, describe in detail as after.
[first embodiment]
Seeing also shown in Figure 2ly, is the generalized section according to the wafer encapsulation body of the utility model first embodiment.The wafer encapsulation body 200 of present embodiment comprises a supporting bracket 210, at least one wafer 220, an internal connection-wire structure 230, at least one fuel plate 240 and a plurality of connection pad 238, wherein:
This supporting bracket 210 has at least one opening 210a, and wafer 220 is to be disposed in the opening 210a.What deserves to be mentioned is,, between wafer 220 and supporting bracket 210, more can insert a sealing 280 in order to make wafer 220 can be fixed in the opening 210a.In addition, the material of supporting bracket 210 for example is glass, metal or circuit base plate, yet the material of supporting bracket 210 more can be other dielectric materials or electric conducting material.
This internal connection-wire structure 230, be to be disposed on supporting bracket 210 and the wafer 220, and wafer 220 is to electrically connect mutually with the internal wiring of internal connection-wire structure 230, wherein internal connection-wire structure 230 for example is that the bumpless formula increases layer (Bumpless Build-Up Layer, BBUL), meaning is that the electric connection between supporting bracket 210 and the wafer 220 is not by existing known chip package projection, and directly passes through the internal wiring (not shown) of internal connection-wire structure 230.Generally speaking, this internal connection-wire structure 230 comprises multilayer dielectric layer 232a, 232b and 232c, and multilayer line layer 234a and 234b, wherein, these dielectric layers 232a, 232b and 232c and these line layers 234a and 234b are interconnected on supporting bracket 210 and wafer 220.In addition, a plurality of conductions duct 236 is to run through these dielectric layers 232a, 232b and 232c, and line layer 234a and 234b are electrically connected to each other via these conduction ducts 236, and these conduction ducts 236 and these line layers 234a and 234b are the internal wirings that constitutes internal connection-wire structure 230.In addition, wafer 220 has a plurality of connection pads 222, and line layer 234a is the connection pad 222 that is electrically connected to wafer 220 via these conduction ducts 236.
This fuel plate 240, please continue to consult shown in Figure 2, it is to bury underground in internal connection-wire structure 230, and fuel plate 240 for example is tabular active member (panel-shape active component) or tabular passive device (panel-shape passive component).In addition, this tabular active member for example is tabular semiconductor element, and tabular passive device for example is tabular capacity cell, tabular resistive element, tabular inductance element or integrated tabular passive device etc.What deserves to be mentioned is that this fuel plate 240 more can have active member part and passive device part simultaneously, and constitutes an integrated fuel plate.In addition and since fuel plate 240 can manufacture of semiconductor or the ceramic post sintering processing procedure made, so the material of fuel plate 240 can be silicon or pottery.
This fuel plate 240 comprises an element layer 242 and a plurality of electrode 244, and wherein, these electrodes 244 are to intersperse among two relatively on the surface of element layer 242 respectively, and for example these electrodes 244 are distributed in two relatively on the surface of element layer 242 with array way respectively.Because these electrodes 244 are to intersperse among two relatively on the surface of element layer 242, so this fuel plate 240 not only can have more electrode 244, more can be used as the usefulness of levels line conduction.In other words, compared to the passive device that has known peripheral electrode formula now, the fuel plate 240 of present embodiment can provide higher electrode density.
With regard to present embodiment, this fuel plate 240 is to be electrically connected to wafer 220 and internal connection-wire structure 230 respectively.In other words, this fuel plate 240 is to be electrically connected to wafer 220 and internal connection-wire structure 230 respectively via these conduction ducts 236.Or this fuel plate is also configurable between two line layers of internal connection-wire structure 230, and is via fuel plate 240 be electrically connected to each other (as shown in Figure 3) between two line layers of internal connection-wire structure 230.In addition, these connection pads 238 are to be disposed on the surface away from wafer 220 of internal connection-wire structure 230, and these connection pads 238 are to be electrically connected to wafer 220 via internal connection-wire structure 230 with fuel plate 240.These connection pads 238 can belong to the conductive layer of same patterning, and its processing procedure is to be same as these line layers 234a and 234b.
What deserves to be mentioned is that in that additional configuration electrical contact 260 is not to the situation of connection pad 238, these connection pads 238 can be applicable to fill up the signal output-input interface of lattice array (LGA) type.In addition, also configurable a plurality of electrical contacts 260 on these connection pads 238, and the electrical contact 260 of present embodiment is conducting sphere (conductive ball), so that the signal output-input interface of sphere grid array (BGA) type to be provided.In addition, in another embodiment of the present utility model, this electrical contact 260 can also be a conduction stitch (conductive pin), and so that the signal output-input interface of pin lattice array (PGA) type to be provided, still such embodiment does not represent with drawing.
When these connection pads 238 weld an electrical contact 260 respectively, an also configurable welding cover layer 270 on internal connection-wire structure 230, it exposes these connection pads 238, and the surface lines of protection internal connection-wire structure 230.In addition, in order to improve the radiating efficiency of wafer encapsulation body 200, wafer encapsulation body 200 more comprises a fin (heat spreader) 250, it is configured on the surface away from internal connection-wire structure 230 of supporting bracket 210 and wafer 220, promptly conducts so far area greater than the surface of the fin 250 of wafer 220 in order to the high heat that wafer 220 is produced.Moreover the wafer encapsulation body 200 of present embodiment is not defined for the single-chip module, and (multi-chipmodule, MCM), the quantity of fuel plate 240 also is not limited to single simultaneously, also can be a plurality of more to can be used for polycrystalline sheet module.
From the above, when replacing a plurality of existing known peripheral electrode formula passive device within fuel plate 240 is embedded in wafer encapsulation body 200, the structure dress density of wafer encapsulation body 200 can improve.In addition, fuel plate 240 more can be used as the usefulness of levels line conduction, makes wafer 220 can be electrically connected to these connection pads 238 via fuel plate 240.What deserves to be mentioned is, when fuel plate 240 is tabular capacity cell, because fuel plate 240 is belows of directly being located at wafer 220, so wafer encapsulation body 200 has less voltage fluctuation (voltage fluctuation), and can improve the electrical property efficiency of wafer encapsulation body.
[second embodiment]
Seeing also shown in Figure 3ly, is the generalized section according to the wafer encapsulation body of the utility model second embodiment.This second embodiment is similar to first embodiment, and its difference is that fuel plate is between two line layers.In the wafer encapsulation body 300 of second embodiment, internal connection-wire structure 330 comprises line layer 334a, 334b and 334c and dielectric layer 332a, 332b, 332c and 332d, and wherein these dielectric layers 332a, 332b, 332c and 332d and line layer 334a, 334b and 334c are interconnected on substrate 210 and wafer 220.In addition, a plurality of conductions duct 336 is to run through one of these dielectric layers 332a, 332b, 332c and 332d respectively, and these line layers 334a, 334b and 334c are via these conduction ducts 336 and be electrically connected to each other.
It should be noted that this fuel plate 240 is to be disposed between the line layer 334a and 334c of internal connection-wire structure 330, and this line layer 334a is electrically connected to line layer 334c via fuel plate 240.In other words, be to be electrically connected to each other between two line layers of internal connection-wire structure 230 via fuel plate 240.
[the 3rd embodiment]
Seeing also shown in Figure 4ly, is the generalized section according to the wafer encapsulation body of the utility model the 3rd embodiment.The 3rd embodiment is similar to first embodiment, its difference is: in the wafer encapsulation body 400 of the 3rd embodiment, internal connection-wire structure 230 is to be disposed on the wafer 410, and fuel plate 240 is the connection pads 412 that electrically connect internal connection-wire structure 230 and wafer 410 respectively.In other words, present embodiment there is no the supporting bracket 210 of similar Fig. 2 and the structure of sealing 280.
[the 4th embodiment]
Seeing also shown in Figure 5ly, is the generalized section according to the wafer encapsulation body of the utility model the 4th embodiment.The 4th embodiment is similar to second embodiment, and its difference is: in the wafer encapsulation body 400 of the 4th embodiment, internal connection-wire structure 330 is to be disposed on the wafer 510, and the connection pad 512 of wafer 510 is directly to be connected with internal connection-wire structure 330.It should be noted that present embodiment there is no the supporting bracket 210 of similar Fig. 3 and the structure of sealing 280.
In sum, since the utility model be with fuel plate bury underground to the bumpless formula increase the layer (BBUL) type wafer encapsulation body in, and fuel plate is to dispose a plurality of electrodes respectively on the lower surface thereon, therefore wafer encapsulation body of the present utility model has higher wiring density, and above-mentioned fuel plate also can be used as the usefulness of conducting of the inside levels circuit of internal connection-wire structure.In addition, when the fuel plate with capacitive function be applied to the bumpless formula increase the layer (BBUL) type wafer encapsulation body the time, wafer encapsulation body of the present utility model can have less voltage fluctuation and cross-talk phenomenon.In addition, because fuel plate is below or the adjacent wafer that can directly be located at wafer, thereby can shorten the signal transmission path between fuel plate and the wafer, and then can promote the electrical property efficiency of the integral body of wafer encapsulation body.
The above, it only is preferred embodiment of the present utility model, be not that the utility model is done any pro forma restriction, though the utility model discloses as above with preferred embodiment, yet be not in order to limit the utility model, any those skilled in the art, in the scope that does not break away from technical solutions of the utility model, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solutions of the utility model content, foundation technical spirit of the present utility model is to above any simple modification that embodiment did, equivalent variations and modification all still belong in the scope of technical solutions of the utility model.
Claims (10)
1, a kind of wafer encapsulation body is characterized in that it comprises:
At least one wafer has most first connection pads on surface thereof;
One internal connection-wire structure is disposed on this wafer, and those first connection pads of this wafer are to electrically connect mutually with this internal connection-wire structure;
Most second connection pad are disposed on the surface away from this wafer of this internal connection-wire structure; And
At least one fuel plate, be embedded in this internal connection-wire structure, and this fuel plate has most electrodes in distributing it respectively two relatively on the surface, and those second connection pads are those first connection pads that are electrically connected to this wafer via this internal connection-wire structure and this fuel plate.
2, wafer encapsulation body according to claim 1, it is characterized in that wherein said fuel plate two relatively the surface be to be electrically connected to this wafer and this internal connection-wire structure respectively, and each those electrode is to be electrically connected to this wafer or this internal connection-wire structure.
3, wafer encapsulation body according to claim 1, those electrodes that it is characterized in that wherein said fuel plate are to be distributed in it two relatively on the surface with array way.
4, wafer encapsulation body according to claim 1 is characterized in that wherein said internal connection-wire structure comprises:
A most dielectric layer;
Those dielectric layers are run through in most conduction ducts respectively; And
Most line layers, wherein those line layers and those dielectric layers are interconnected, and one of those line layers are to conduct electricity one of ducts and be electrically connected to another of those line layers via those.
5, wafer encapsulation body according to claim 4 is characterized in that wherein said fuel plate is to be disposed between those line layers, and one of those line layers are to be electrically connected to another of those line layers via this fuel plate.
6, wafer encapsulation body according to claim 1 is characterized in that it more comprises a supporting bracket, and this supporting bracket has an opening, and this wafer is to be disposed in this opening, and this internal connection-wire structure is to be disposed on this wafer and this supporting bracket.
7, wafer encapsulation body according to claim 1 is characterized in that wherein said fuel plate is tabular active member.
8, wafer encapsulation body according to claim 1 is characterized in that wherein said fuel plate is tabular passive device.
9, wafer encapsulation body according to claim 1 is characterized in that wherein said fuel plate has active member part and passive device part.
10, wafer encapsulation body according to claim 1 is characterized in that the material of wherein said fuel plate comprises silicon or pottery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2005200015291U CN2779615Y (en) | 2005-01-25 | 2005-01-25 | Wafer package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2005200015291U CN2779615Y (en) | 2005-01-25 | 2005-01-25 | Wafer package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2779615Y true CN2779615Y (en) | 2006-05-10 |
Family
ID=36753702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2005200015291U Expired - Lifetime CN2779615Y (en) | 2005-01-25 | 2005-01-25 | Wafer package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2779615Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345201B (en) * | 2007-07-13 | 2012-10-17 | 株式会社迪思科 | Wafer processing method |
-
2005
- 2005-01-25 CN CNU2005200015291U patent/CN2779615Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345201B (en) * | 2007-07-13 | 2012-10-17 | 株式会社迪思科 | Wafer processing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20150125 Granted publication date: 20060510 |