CN2713481Y - Electric loop contact fault detector - Google Patents
Electric loop contact fault detector Download PDFInfo
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- CN2713481Y CN2713481Y CN 200420036988 CN200420036988U CN2713481Y CN 2713481 Y CN2713481 Y CN 2713481Y CN 200420036988 CN200420036988 CN 200420036988 CN 200420036988 U CN200420036988 U CN 200420036988U CN 2713481 Y CN2713481 Y CN 2713481Y
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Abstract
The utility model provides an electric loop contact fault detector, comprising a JK flip-flop whose J end and K end keep high-level signal input, a first nand gate circuit whose control end incepts the abnormal signals of the electric return circuit joint, a first electronic switch whose control end is connected to the Q end of the JK flip-flop and whose input end is connected to the output end of the first nand gate circuit, a second electronic switch whose control end is connected to the Q negligence end of the JK flip-flop and whose input end is connected to the input end of the first nand gate, an RS flip-flop whose S end is connected to the output ends of the first and second electronic switches and whose R end is connected to a constant voltage source and is earthed by a first reset switch and whose Q end outputs warning signals. The electric loop contact fault detector can ensure to catch various soft-hard abnormal faults of the detected joints. In addition, the compact conformation of the detector needs a few devices; therefore the detecting reliability is improved and the checking cost is reduced.
Description
Technical field
The utility model relates to the fault checkout equipment, particularly a kind of device that electric control loop contact unusual fluctuation fault is detected of being suitable for.
Background technology
Electric control loop is made of some switching contacts (for example the contact of the auxiliary contact of all kinds of switches, relay etc.), solenoid (for example relay, contactor etc.) and control power supply usually, wherein, open and close contact and can connect into different logical circuits, thereby realize all kinds of automatic controls by serial or parallel connection.
Open and close contact unusual fluctuation fault and be in the electric control system common faults the most, can be divided into two types of hard fault and soft faults usually.So-called hard fault, be meant that fault that trouble spot, back can not eliminated automatically takes place for those, for such fault, as long as utilizing the checkout equipment of multimeter and so on checks one by one to the break-make situation in loop, the switching situation of contact, can find the trouble spot, therefore detection difficulty is less, and workload is also little.So-called soft fault is meant that fault that eliminate automatically trouble spots, back takes place for those, and such fault is referred to as " ghost " fault again, for such fault, take place owing to have at random, so the trouble spot is difficult to catch, and brings a lot of difficulties to cause investigation.
Summary of the invention
The purpose of this utility model provides a kind of electric loop contact failure detector, and this device is by monitoring and record contact or the contact group that unusual fluctuation may take place, thereby catches out the detected contact of generation soft or hard unusual fluctuation fault.
Above-mentioned purpose of the present utility model is achieved through the following technical solutions:
A kind of electric loop contact failure detector comprises:
JK flip-flop, its J end and K end keep the high level signal input;
First NAND gate circuit, its input end receives the unusual fluctuation signal of electric loop contact;
First electronic switch, its control end are connected to the Q end of described JK flip-flop and the output terminal that input end is connected to described first NAND gate circuit;
Second electronic switch, its control end are connected to the non-end of Q of described JK flip-flop and the input end that input end is connected to described first Sheffer stroke gate;
Rest-set flip-flop, its S end is connected to the output terminal of described first and second electronic switches, and the R end is connected to constant pressure source and through the first reset switch ground connection, Q holds output alarm signal.
Reasonable is in above-mentioned electric loop contact failure detector, further to comprise:
Rectification circuit, its input end links to each other with switching contact to be measured;
First on-off circuit, its control end links to each other with the output head anode of described rectification circuit;
The photoelectricity coupled circuit, its input end is connected to the output terminal of described first on-off circuit, and output terminal is connected to the input end of described first NAND gate circuit.Be more preferably, described rectification circuit is unidirectional bridge rectifier, described first on-off circuit comprises triode, its base stage is connected to the output head anode of described unidirectional bridge rectifier and through the voltage stabilizing diode ground connection of reversal connection through resistance, its collector is connected to the described output head anode of described unidirectional bridge rectifier, and its emitter is connected to the input end of photoelectricity coupled circuit through a diode.
Reasonablely be, in above-mentioned electric loop contact failure detector, further comprise clock pulse signal generation circuit, its output terminal is connected to the CLK end of described JK flip-flop, and comprises second reset switch that is connected in the loop.
Reasonablely be, in above-mentioned electric loop contact failure detector, further comprise second NAND gate circuit, second switch circuit and dichromatic LED, the input end of described second NAND gate circuit is connected to the S end of described rest-set flip-flop, output terminal is connected to the control end of described second switch circuit, and one of them of described dichromatic LED is connected to the Q end of described rest-set flip-flop and another is connected to the output terminal of described second switch circuit.
Electric loop contact failure detector of the present utility model utilizes the latch function of rest-set flip-flop, it is hereby ensured the various soft or hard unusual fluctuation faults that capture detected contact.In addition, the compact conformation of above-mentioned detection device, required component number is few, has therefore improved detecting reliability on the one hand, has reduced the detection cost on the other hand again.
Description of drawings
Fig. 1 is the electrical schematic diagram according to the electric loop contact failure detector of the utility model preferred embodiment.
Embodiment
According to Circuit theory and electromagnetic principle, in secondary circuit, when the loop is in channel status, rated voltage loads on the relay coil two ends, each the series connection contact that constitutes the loop all is in closure state, and this moment, the potential difference (PD) at each circuit-closing contacts two ends all was zero, when some contact opens wherein, relay coil will lose excitation, and the two ends of meanwhile cut-offfing contact will produce the pulse voltage of a rising edge.On the contrary, when the loop is in off state, the relay coil two ends just do not have voltage, and have a contact to be in off-state in the loop this moment, if certain junction closure action can apply excitation to coil, then before this junction closure, the potential difference (PD) at contact two ends equals circuit controls power source voltage value, and when it became closure by disconnection, relay coil will obtain excitation, the potential difference (PD) at these contact two ends has been equivalent to produce the pulse voltage of a negative edge in the moment vanishing simultaneously.
Therefore, normally in service at secondary circuit, if the voltage at certain contact two ends is undergone mutation, illustrate that then variation has taken place the state that cut-offs of this contact.Pick-up unit of the present utility model is at These characteristics, by the loop contact of the monitoring of rising edge or negative edge pulse voltage signal being determined break down.
Below by accompanying drawing preferred embodiment of the present utility model is described.
As shown in Figure 1, the pick-up unit of this preferred embodiment is made up of three parts, and wherein, the conversion of signals that part i is responsible for detected switching contact two ends is the electric signal with appropriate level; Part ii is responsible for making the switching contact two ends signal constant under the normal condition to be decided to be high level signal or low level signal, and makes the level signal upset be low level signal or high level signal when the unusual fluctuation fault occurring; III partly is responsible for correspondingly overturning level signal when the unusual fluctuation fault occurring and keeps this rollover states constant.Below these parts are described one by one.
Referring to Fig. 1, part i comprises unidirectional bridge rectifier B1, triode N3, voltage stabilizing diode Z1, diode one triode photoelectrical coupler IC1, wherein, the voltage signal at detected contact two ends inserts two input ends of single-phase bridge rectifier B1, ground connection of output terminal, another exports rectified signal as output head anode, triode N3 is equivalent to an on-off element, itself and voltage stabilizing diode Z1, resistance R etc. constitute first on-off circuit, the base stage of triode N3 is connected to the rectified signal output terminal of unidirectional bridge rectifier B1 on the one hand through resistance R 1 as control end, on the other hand through the voltage stabilizing diode Z1 of reversal connection ground connection, therefore base stage has constant voltage when contact is in normal condition, the collector of triode N3 is equivalent to input end, it is connected directly to the rectified signal output terminal of rectifier, the emitter of triode N3 is equivalent to output terminal, it is connected to the input end of diode one triode photoelectrical coupler IC1, and the output terminal of photoelectrical coupler IC1 is connected to two input ends of the first NAND gate circuit IC2C.Here, photoelectrical coupler IC1 constitutes the photoelectricity coupled circuit as photo-electric conversion element and with other auxiliary circuit.
In the present embodiment, if the contact two ends are ac voltage signal, then need only two input ends that the contact two ends inserted single-phase bridge rectifier B1, if the contact two ends are d. c. voltage signal, then as long as positive pole is connected to the LP001 end, negative pole is connected to the LP002 end and gets final product.Therefore pick-up unit of the present utility model is suitable for handling various types of voltage signals.In addition, owing to adopt on-off circuit and photoelectricity coupling scheme, therefore can adapt to the voltage signal of different brackets, input impedance is big, can not exert an influence to detected system.
For opening the contact situation, the contact two ends are high voltage, so rectifier B1 output HIGH voltage, voltage stabilizing diode Z1 operate as normal (reverse breakdown), and triode N3 conducting, photoelectrical coupler IC1 operate as normal, the input end of gate circuit IC2C is a high level.At this moment, if input signal is no-voltage (be equivalent to input signal and produced a negative edge pulse) by high-voltage variable, then photoelectrical coupler IC1 quits work, and causing the level of NAND gate circuit IC2C input end is high level by the low level upset immediately.For closing the contact situation, contact two ends no-voltage, so rectifier B1 output no-voltage, voltage stabilizing diode Z1 quits work, and triode N3 turn-offs, and photoelectrical coupler IC1 quits work, and the input end of gate circuit IC2C is a high level.At this moment, if input signal becomes high voltage (be equivalent to input signal and produced a rising edge pulse) by no-voltage, then the level of gate circuit IC2C input end will be a low level by the high level upset immediately.
Therefore, when the contact open and-shut mode changes (fault), will cause the level of gate circuit IC2C input end that once inside out takes place thereupon.
Refer again to Fig. 1, part ii mainly comprises the signal processing circuit of being made up of the first NAND gate circuit IC2C, JK flip-flop IC7A, the first and second electronic switch IC3A, IC3C, wherein, the input end of NAND gate circuit IC2C and output terminal are connected to the input end of the second electronic switch IC3C and the input end of the first electronic switch IC3A respectively, the output terminal of the first and second electronic switch IC3A, IC3C is connected together altogether, the control end that the Q end of JK flip-flop IC7A and the non-end of Q are connected to the first and second electronic switch IC3A and IC3C respectively.
Because the first and second electronic switch IC3A, IC3C are by Q end and the non-end control of Q of same JK flip-flop IC7A, so being in one all the time opens and the assembled state of another shutoff, therefore regardless of the output level of the first NAND gate circuit IC2C, can make that the output terminal of electronic switch is exported high level all the time under the original state by selecting suitable electronic switch break-make combination.For this reason,, the J of JK flip-flop IC7A end and K end make J=K=1 (being that J and K end keeps the high level input signal) thereby being connected to constant pressure source altogether, and by making the JK flip-flop upset to obtain required Q and Q NOT logic combined value in CLK end input clock pulse.
In the present embodiment, the clock pulse signal of JK flip-flop CLK end is provided by the clock pulse signal generative circuit shown in Fig. 1 bottom, as shown in Figure 1, in this circuit, reverser IC1A, IC1B and resistance R 19 are cascaded, and capacitor C 1 is connected in parallel on the two ends of series element, one end of these connection in series-parallel elements is connected to constant pressure source through the second reset switch K2, the other end is connected to the CLK end of JK flip-flop IC7A, when reset switch K2 was closed, the processing of process connection in series-parallel element produced the output pulse signal with suitable waveform and amplitude.It is worthy of note; for the one of ordinary skilled in the art; the various circuit that produce clock pulse signal all are known, so the generative circuit of clock pulse signal shown in the present embodiment only has illustrative nature, should not be construed as the restriction to the utility model spirit and protection domain.
Referring to Fig. 1, the III part mainly comprises the basic rest-set flip-flop of being made up of two Sheffer stroke gate IC2A, IC2B, wherein, the input end of the Sheffer stroke gate IC2A that is connected with the IC3C output terminal with electronic switch IC3A is equivalent to the S end, its output terminal is equivalent to the Q end, Sheffer stroke gate IC2B is connected to constant pressure source and is equivalent to the R end through the input end of the first reset switch K1 ground connection through resistance R 15, and its output terminal is connected to another input end of Sheffer stroke gate IC2A, is equivalent to the non-end of Q.Under original state, make rest-set flip-flop put 0 by loading a negative pulse, thereby keep low level output to load undersuing up to the S end at the Q end at the R end; When causing the upset of electronic switch output end signal for low level signal when the unusual fluctuation fault occurring, rest-set flip-flop puts 1, thereby makes the Q end keep the output of output high level to load undersuing up to the R end.
In the present embodiment, the III part also comprises the second NAND gate circuit IC2D, triode N2 and dichromatic LED D, wherein, the input end of the second NAND gate circuit IC2D and the S of above-mentioned rest-set flip-flop end connect altogether, triode N2 is equivalent to an on-off element, itself and other element constitutes the second switch circuit, the base stage of triode N2 is connected to the output terminal of Sheffer stroke gate IC2D through resistance R 14 as control end, collector is equivalent to input end, it is connected to constant pressure source, emitter is equivalent to output terminal, dichromatic LED D is used to indicate the state of loop contact, wherein green LED links to each other with triode N2 with the indication normal condition, and red light emitting diodes is connected to the Q end of above-mentioned rest-set flip-flop with indicating fault status.In addition, for fault-signal is carried out Computer Processing, as shown in Figure 1, the output terminal of Sheffer stroke gate IC2A is connected with capacitor C 4 with the resistance R of series connection 16, thereby by being connected on the voltage stabilizing diode Z2 output+5V voltage signal on terminal A between capacitor C 4 and the terminal A.
The principle of work of present embodiment pick-up unit is below described.
Before being detected, the loop contact at first carries out the initialization setting, that is, the output terminal that makes electronic switch is a high level, and the Q end of rest-set flip-flop is low level, the output terminal of the second Sheffer stroke gate IC2D is a low level, so the green light of dichromatic LED D lights and red light extinguishes.
After pick-up unit was connected working power, the state of Sheffer stroke gate IC2D and IC2A input end and Sheffer stroke gate IC2A output terminal (being the Q end of rest-set flip-flop) was uncertain.If the input end of Sheffer stroke gate IC2D and IC2A is a low level, then can presses reset switch K2 and make JK flip-flop IC7A upset, thereby the input end of Sheffer stroke gate IC2D and IC2A is placed high level state; If the output terminal of Sheffer stroke gate IC2A (being the Q end of rest-set flip-flop) for high level, then can be pressed reset switch K1 to make above-mentioned rest-set flip-flop put 0, the Q end is placed low level state.
After finishing initialization and being provided with, can detect the loop contact.When the unusual fluctuation fault appears in the loop contact, processing through part i, energizing signal will appear in the input end at the first Sheffer stroke gate IC2C, because the break-make assembled state of electronic switch IC3A, IC3C does not become, therefore the high level signal upset on Sheffer stroke gate IC2D and the IC2A input end (being the S end of rest-set flip-flop) is low level signal, make the level upset of Sheffer stroke gate IC2D output terminal be high level thus, triode N2 turn-offs, and the green light of dichromatic LED extinguishes; The level upset of Sheffer stroke gate IC2A output terminal (being the Q end of rest-set flip-flop) is for high level and keep high level state constant, and the red light of dichromatic LED is lighted; And hold output+5V voltage signal at A by voltage stabilizing diode Z2.
Claims (5)
1, a kind of electric loop contact failure detector is characterized in that, comprises:
JK flip-flop, its J end and K end keep the high level signal input;
First NAND gate circuit, its input end receives the unusual fluctuation signal of electric loop contact;
First electronic switch, its control end are connected to the Q end of described JK flip-flop and the output terminal that input end is connected to described first NAND gate circuit;
Second electronic switch, its control end are connected to the non-end of Q of described JK flip-flop and the input end that input end is connected to described first Sheffer stroke gate;
Rest-set flip-flop, its S end is connected to the output terminal of described first and second electronic switches, and the R end is connected to constant pressure source and through the first reset switch ground connection, Q holds output alarm signal.
2, electric loop contact failure detector as claimed in claim 1 is characterized in that, further comprises:
Rectification circuit, its input end links to each other with switching contact to be measured;
First on-off circuit, its control end links to each other with the output head anode of described rectification circuit;
The photoelectricity coupled circuit, its input end is connected to the output terminal of described first on-off circuit, and output terminal is connected to the input end of described first NAND gate circuit.
3, electric loop contact failure detector as claimed in claim 2, it is characterized in that, described rectification circuit is unidirectional bridge rectifier, described first on-off circuit comprises triode, its base stage is connected to the output head anode of described unidirectional bridge rectifier and through the voltage stabilizing diode ground connection of reversal connection through resistance, its collector is connected to the described output head anode of described unidirectional bridge rectifier, and its emitter is connected to the input end of photoelectricity coupled circuit through a diode.
4, as any described electric loop contact failure detector in the claim 1～3, it is characterized in that, further comprise clock pulse signal generation circuit, its output terminal is connected to the CLK end of described JK flip-flop, and comprises second reset switch that is connected in the loop.
5, electric loop contact failure detector as claimed in claim 4, it is characterized in that, further comprise second NAND gate circuit, second switch circuit and dichromatic LED, the input end of described second NAND gate circuit is connected to the S end of described rest-set flip-flop, output terminal is connected to the control end of described second switch circuit, and one of them of described dichromatic LED is connected to the Q end of described rest-set flip-flop and another is connected to the output terminal of described second switch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420036988 CN2713481Y (en) | 2004-06-30 | 2004-06-30 | Electric loop contact fault detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420036988 CN2713481Y (en) | 2004-06-30 | 2004-06-30 | Electric loop contact fault detector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2713481Y true CN2713481Y (en) | 2005-07-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420036988 Expired - Fee Related CN2713481Y (en) | 2004-06-30 | 2004-06-30 | Electric loop contact fault detector |
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|---|---|
| CN (1) | CN2713481Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771758A (en) * | 2016-12-30 | 2017-05-31 | 华润水泥技术研发有限公司 | The positioner and method of failure in cabinet control loop |
| CN111474461A (en) * | 2020-03-31 | 2020-07-31 | 南京优倍电气有限公司 | Circuit device for detecting failure of switch of functional safety product |
| CN111813088A (en) * | 2020-07-16 | 2020-10-23 | 国核自仪***工程有限公司 | DI channel diagnostic circuit and method |
-
2004
- 2004-06-30 CN CN 200420036988 patent/CN2713481Y/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771758A (en) * | 2016-12-30 | 2017-05-31 | 华润水泥技术研发有限公司 | The positioner and method of failure in cabinet control loop |
| CN106771758B (en) * | 2016-12-30 | 2023-09-12 | 华润水泥技术研发有限公司 | Positioning device and method for faults in control loop of electrical switch cabinet |
| CN111474461A (en) * | 2020-03-31 | 2020-07-31 | 南京优倍电气有限公司 | Circuit device for detecting failure of switch of functional safety product |
| CN111813088A (en) * | 2020-07-16 | 2020-10-23 | 国核自仪***工程有限公司 | DI channel diagnostic circuit and method |
| CN111813088B (en) * | 2020-07-16 | 2021-10-01 | 国核自仪***工程有限公司 | DI channel diagnostic circuit and method |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050727 Termination date: 20130630 |