CN2708504Y - Wafer packaging structure - Google Patents

Wafer packaging structure Download PDF

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Publication number
CN2708504Y
CN2708504Y CN 200420064702 CN200420064702U CN2708504Y CN 2708504 Y CN2708504 Y CN 2708504Y CN 200420064702 CN200420064702 CN 200420064702 CN 200420064702 U CN200420064702 U CN 200420064702U CN 2708504 Y CN2708504 Y CN 2708504Y
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CN
China
Prior art keywords
pin
lead frame
wafer
forms
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 200420064702
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Chinese (zh)
Inventor
杜亮宏
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Individual
Original Assignee
Individual
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Publication date
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Priority to CN 200420064702 priority Critical patent/CN2708504Y/en
Application granted granted Critical
Publication of CN2708504Y publication Critical patent/CN2708504Y/en
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Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The utility model relates to a wafer packaging structure, which is primarily made by the way that a semiconductor wafer is packaged to form a packaging body after the semiconductor wafer is electrically connected to a conducting wire frame. The utility model is characterized in that the wafer is provided with a semiconductor integrated circuit and forms a plurality of electrodes which are electrically connected with the conducting wire frame which is provided with a plurality of pins; each pin at least forms a bearing surface with quite a large area and is electrically connected to the corresponding electrodes through gold wires which are composed of metal conducting wires to respectively form a signal channel for providing the transmission of signals. The packaging body is formed by the way that high molecular materials are wrapped on the whole wafer and the conducting wire frame, and is matched with the pins of the conducting wire frame to form a plurality of through holes corresponding to the bearing surfaces of the pins of the conducting wires; thus a plurality of ball pins with the guiding electrical characteristic can penetrate through the through holes to be welded to the corresponding bearing surfaces, and a signal channel for joining circuit boards together is formed.

Description

Chip package structure
Technical field
The utility model relates to a kind of chip package structure, particularly forms ball pin trellis array (Ball Grid Array, encapsulating structure BGA), and can simplify encapsulating structure, and shorten the signal transmission range.
Background technology
General semiconductor wafer need see through encapsulation process, in order to protecting this wafer, and installs simultaneously the pin that is electrically connected is provided.In the known encapsulation process, a kind of about bga structure, shown with reference to figure 4, it mainly is with after being electrically connected a basal plate 20 with semiconductor wafer 10, form a packaging body 30 with epoxy resin encapsulation again and constitute, wherein, this wafer 10 has the electrode 101 that several electric outputs are gone into, see through the basal plate 20 that gold thread 202 routings stick together to wafer 10 bottoms, and corresponding each signal be electrically connected passage.In addition, in the basal plate 20, its each signal be electrically connected passage, can form a ball pin 302 in basal plate 20 bottoms, can be welded in thus in the circuit of circuit board, form the signal path that is connected circuit board.
In addition, in the known encapsulation process, also utilize little outer pin package (thin smalloutline package, TSOP) encapsulating structure, it utilizes the signal source of a lead frame connecting wafer, after encapsulation, sees through the part that lead frame extends packaging body again, therefore be soldered on the circuit board, form wafer and set firmly and be electrically connected in the circuit board in the pairing circuit.
Summary of the invention
In the aforementioned chip package structure commonly used, it utilizes known TSOP encapsulating structure, it utilizes lead frame to extend outside the packaging body, directly form its electrical path, has characteristic simple in structure, but oversize because form the signal channel path, and be unfavorable for the data transmission of high frequency, and the distribution of its pin position also causes the excessive problem of footprint area.In addition, utilize known bga structure, see through the ball pin and form the signal passage, though can improve the problem that the TSOP encapsulating structure is caused, in order to form the electrical connecting interface layer between wafer and the ball pin, a basal plate must be formed on its bottom.Compared to lead frame, the cost of manufacture of basal plate or process complexity are higher, and want to dwindle the distribution area of ball pin, will make its cost or complexity increase.Therefore, the utility model is created based on the shortcoming of chip package structure commonly used.
The utility model is a kind of chip package structure, with restriction and the shortcoming in one of reality solution or several aforementioned related art.
For achieving the above object, the utility model provides a kind of chip package structure, it is mainly at ball pin trellis array (Ball Grid Array, BGA) in the chip package structure, see through the loading end that lead frame forms the ball pin, in order to as the electrical connecting interface layer between wafer and the ball pin, and in the packaging body of encapsulation coating wafer and connecting structure for electrical equipment, form the perforation of corresponding loading end, and reach the purpose that its ball pin is set.
Based on aforementioned the utility model chip package structure, it can reach following effect and effect:
Because chip package structure of the present utility model, its wafer sees through the BGA structure, can shorten the signal transmission path, thereby more be applicable to the transmission of high-frequency signals.
According to chip package structure of the present utility model, its wafer sees through the BGA structure, thereby can reduce the area that wafer after the encapsulation occupies circuit board.
In the chip package structure of the present utility model, its wafer directly is carried on the lead frame, and sees through the perforation structure that encapsulation build balling-up pin is followed lead frame, therefore, saves basic unit's circuit board commonly used, and simplifies package body structure and process thereof.
See through chip package structure of the present utility model, the lead frame of its wafer exposes in this packaging body surface, therefore, can promote the radiating efficiency of wafer.
The purpose of this utility model and function will be more clear after being described further in conjunction with following accompanying drawing.
Description of drawings
Accompanying drawing is shown to be provided as the specific embodiment that specifically presents each element described in this specification, and explains that main purpose of the present utility model is to promote understanding of the present utility model.
Fig. 1 is the generalized section of the utility model chip package structure one embodiment.
Fig. 2 is the floor map of the utility model chip package structure about lead frame.
Fig. 3 is the floor map of the utility model chip package structure about packaging body.
Fig. 4 is the generalized section of chip package structure commonly used.
Among the figure
1 wafer, 11 electrodes
2 lead frames, 21 pins
21a loading end 22 gold threads
31 perforation of 3 packaging bodies
32 ball pin, 10 wafers
101 electrodes, 20 basal plates
202 gold threads, 30 packaging bodies
302 ball pin
Embodiment
Chip package structure provided by the utility model, mainly (BallGrid Array, BGA) in the chip package structure, the packaging body by encapsulation coating wafer and connecting structure for electrical equipment is provided with its ball pin at ball pin trellis array for it.
As shown in Figure 1, generalized section for a kind of preferred embodiment of the utility model chip package structure, its mainly be with semiconductor wafer 1 with after being electrically connected a lead frame 2, form a packaging body 3 with epoxy resin encapsulation again and constitute, being characterized as of its each element:
This wafer 1 has the semiconductor integrated circuit, and its bottom surface has several electrodes 11, and by each electrode 11 to be electrically connected this lead frame 2.
As shown in Fig. 2, this lead frame 2 has several pins 21 to cooperate each electrode 11 of this wafer 1 bottom, each pin 21 is a signal path (signal channel), and see through gold thread 22 that plain conductor constituted respectively to be electrically connected pairing electrode 11, make thus in the wafer 1 as signal export into several electrodes 11, can see through gold thread 22 respectively and be electrically connected to pairing pin 21 in this lead frame 2, and the transmission of signal is provided.In addition, in each pin 21 of this lead frame 2, have a loading end 21a at least, and this loading end 21a forms suitable area.
The pin 21 of aforesaid lead frame 2 cooperates this gold thread 22 and electrode 11, directly is connected across (lead on chip, form LOC) on the wafer and form with pin 21.
Each pin 21 1 ends court in the aforesaid lead frame 2 extends laterally the side that is exposed to this packaging body 3, and can promote heat radiation.
As Fig. 1 and shown in Figure 3, this packaging body 3 is by macromolecular material, such as epoxy resin etc., coat entire wafer 1 and lead frame 2 and constitute, it cooperates each pin 21 signal paths of lead frame 2, run through several perforation 31 of formation in the bottom surface, in order to the loading end 21a in corresponding each lead frame 2 pin 21, make several ball pin 32 can pass this perforation 31, and be soldered to each corresponding loading end 21a, each ball pin 32 is tin balls and have the electric characteristic of guiding, can be welded in the circuit of circuit board, forms the signal path that is connected circuit board.
In aforesaid chip package structure, this wafer 1 sees through several loading ends 21a that forms in the pin 21 of its lead frame 2, and formed several perforation 31 of corresponding each loading end 21a in this packaging body 3, make and several ball pin 32 can be implanted each perforation 31, and then to corresponding loading end 21a.Therefore, the signal path distance that formation is short, and the connecting structure for electrical equipment of simplification wafer 1 and each ball pin 32 formation.
The above is only in order to explain preferred embodiment of the present utility model; be not to be used for the utility model is done any pro forma restriction; so, allly doing relevant any modification of the present utility model or change in that identical spirit is following, all should be included in the scope of the utility model protection.

Claims (3)

1. chip package structure, it mainly is after semiconductor wafer is electrically connected a lead frame, encapsulation forms a packaging body again, it is characterized in that:
This wafer has the semiconductor integrated circuit, and forms several electrodes, in order to be electrically connected this lead frame;
This lead frame has several pins, and each pin forms a loading end with equivalent area at least, and each pin sees through the gold thread that plain conductor constituted and be electrically connected to corresponding electrode, and forms a signal path respectively, in order to the transmission of signal to be provided; And
This packaging body is made of macromolecular material coating entire wafer and lead frame, and each pin of cooperation lead frame, run through several perforation of the loading end that forms corresponding lead frame pin, make several ball pin can pass this perforation with guiding electrical characteristic, and being soldered to each corresponding loading end, formation can be connected the signal path of circuit board.
2. chip package structure according to claim 1, wherein, the pin of described lead frame cooperates this gold thread and electrode, directly is connected across form on the wafer and form with pin.
3. chip package structure according to claim 1, wherein, each pin one end court in the described lead frame extends laterally the side that is exposed to this packaging body, and can promote heat radiation.
CN 200420064702 2004-06-02 2004-06-02 Wafer packaging structure Expired - Fee Related CN2708504Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200420064702 CN2708504Y (en) 2004-06-02 2004-06-02 Wafer packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200420064702 CN2708504Y (en) 2004-06-02 2004-06-02 Wafer packaging structure

Publications (1)

Publication Number Publication Date
CN2708504Y true CN2708504Y (en) 2005-07-06

Family

ID=34852202

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200420064702 Expired - Fee Related CN2708504Y (en) 2004-06-02 2004-06-02 Wafer packaging structure

Country Status (1)

Country Link
CN (1) CN2708504Y (en)

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C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee