CN2641824Y - Composite chip contruction substrade - Google Patents
Composite chip contruction substrade Download PDFInfo
- Publication number
- CN2641824Y CN2641824Y CNU032727216U CN03272721U CN2641824Y CN 2641824 Y CN2641824 Y CN 2641824Y CN U032727216 U CNU032727216 U CN U032727216U CN 03272721 U CN03272721 U CN 03272721U CN 2641824 Y CN2641824 Y CN 2641824Y
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- Prior art keywords
- layers
- layer
- dielectric
- dielectric layers
- chip
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A composite chip construction substrate comprises a plurality of patterned leading-wire layers that are overlapped mutually in turn. Wherein the most outer layers of the patterned leading-wire layers are provided respectively with a plurality of jointing gaskets, moreover, a plurality of electric conducting layers are arranged between any two adjacent patterned leading-wire layers. Wherein at least one of the electric conducting layers is a ceramic conducting layer, and at least one of the remaining electric conducting layers is an organic conducting layer. In addition, a plurality of electric conducting holes drill through one of the electric conducting layers respectively, and electrically connects at least two patterned leading-wire layers. Wherein the ceramic conducting layer can improve the circuitry density of the chip construction substrate and reduce the enlaced length of the patterned leading-wire layers so as to be in line with the demand of high-density circuitry and high jointing count.
Description
Technical field
The utility model relates to a kind of chip packaging structure, and particularly relates to a kind of combined type chip support plate (Hybrid IC carrier).
Background technology
In recent years, along with making rapid progress of electronic technology, coming out one after another of high-tech electronic industry makes electronic product more humane, with better function constantly weed out the old and bring forth the new, and towards light, thin, short, little trend design.In the middle of semiconductor fabrication process, chip support plate (IC carrier) is one of structure arrangement that often uses at present.Wherein, chip support plate for example is a substrate (substrate), its mainly by multi-layered patterned conductor layer and multilayer dielectric layer alternately coincide the institute constitute, wherein dielectric layer is disposed between the wantonly two adjacent patterning conductor layers, and the patterning conductor layer can by the via that runs through dielectric layer (Plating Through Hole, PTH) or conductive hole (via) and being electrically connected to each other.Because chip support plate has advantages such as wiring is fine and closely woven, assembling is compact and functional, become the main flow of chip packaging substrate (package substrate).
Generally speaking, in the manufacturing process of current chip encapsulation, chip mainly engages the mode and the chip support plate electric connection of (wirebonding) or chip bonding (flip chip bonding) with routing.Please refer to Fig. 1, it illustrates existing a kind of generalized section of covering crystalline substance in conjunction with the chip packaging structure of kenel.This chip packaging structure 100 has a chip support plate 110 and a chip 120.Wherein, chip 120 is disposed on first 112 of chip support plate 110, and chip 120 is by the mode of a plurality of projections 126 with chip bonding, electrically connects with the joint sheet 116a of chip support plate 110.In addition, chip support plate 110 also has a plurality of contacts 118, it is disposed at second 114 of chip support plate 110, these contacts 118 for example are kenels such as soldered ball, stitch or conductive projection, and contact 118 is electrically connected to the projection 126 of correspondence respectively by the patterned line layer 130 of chip support plate 110, externally to connect the contact of a printed circuit board (PCB) (not illustrating) as chip 120.In addition, chip support plate 110 is according to the difference of dielectric material, and roughly can divide into organic dielectric substrate (organic dielectric substrate) and two kinds of ceramic dielectric substrates (ceramic dielectric substrate).The manufacture method of two kinds of substrates and electrical characteristic are all different, so the also restriction to some extent of its purposes.Wherein, organic dielectric substrate for example is glass epoxide base resin (FR-4, FR-5), two maleic acid vinegar imines (Bismaleimide-Triazine, BT) or epoxy resin materials such as (epoxy resin), the multilager base plate that it utilizes storehouse pressing method (lamination) and/or lamination method (build up) to be formed, with respect to the ceramic dielectric substrate, its cost of manufacture is cheap and have a lower dielectric constant, all the time, organic dielectric substrate is the main flow of base plate for packaging or printed circuit board (PCB).
Please refer to Fig. 2, it illustrates the generalized section of existing a kind of chip packaging substrate.Organic dielectric substrate 210 with six layers of (2-2-2) conductor layer is an example, dielectric layer 202 is disposed between the wantonly two adjacent patterning conductor layers 214, wherein dielectric layer 202 comprises a dielectric core layer (dielectric corelayer) 202 (c), and the upper surface of dielectric core layer 202 (c) for example forms two organic dielectric layers 202 (a), 202 (b) in regular turn with Layer increasing method, and the lower surface of dielectric core layer 202 (c) also forms two organic dielectric layers 202 (d), 202 (e) in regular turn with Layer increasing method.In addition, a plurality of vias 216 run through dielectric core layer 202 (c), and the two ends of via 216 electrically connect two patterning conductor layers 214 (c), 214 (d).In addition, a plurality of conductive holes 218 are embedded among the organic in addition dielectric layer 202 of dielectric core layer 202 (c) (a), 202 (b), 202 (d), 202 (e), and electrically connect wantonly two adjacent patterning conductor layer 214 (a), 214 (b), 214 (c) or 214 (d), 214 (e), 214 (f).Moreover, outermost patterning conductor layer 214 (a), 214 (f) also have a plurality of joint sheet 220a, 220b respectively, wherein joint sheet 220a connects the weld pad (not illustrating) of chip in order to correspondence, and the surface of joint sheet 220b also disposes a plurality of contacts 222, and these contacts 222 connect a printed circuit board (PCB) (not illustrating) in order to correspondence.
Please refer to Fig. 3, it illustrates the generalized section of existing another kind of chip packaging substrate.Organic dielectric substrate 230 with six layers of (1-4-1) conductor layer is an example, dielectric layer 232 is disposed between the wantonly two adjacent patterning conductor layers 234, wherein dielectric layer 232 comprises a dielectric core layer 232 (c), and on the dielectric core layer 232 (c), lower surface for example earlier forms two organic dielectric layers 232 (b), 232 (d) with storehouse pressing method, forms two organic dielectric layers 232 (a), 232 (e) of outermost layer more respectively with Layer increasing method.In addition, a plurality of vias 236 run through dielectric core layer 232 (c) and two organic dielectric layers 232 (b), 232 (d), and via electrically connects patterning conductor layer 234 (b), 234 (c), 234 (d), 234 (e) that appoint two-phase to change.In addition, a plurality of conductive holes 238 are embedded in the organic dielectric layer 232 (a), 232 (e) of outermost layer, and electrically connect two adjacent patterning conductor layer 232 (a), 232 (b) or 232 (e), 232 (f).Moreover, patterning conductor layer 234 (a), 234 (f) of outermost layer also have a plurality of joint sheet 240a, 240b respectively, wherein joint sheet 240a connects the weld pad (not illustrating) of chip in order to correspondence, and the surface of joint sheet 240b also disposes a plurality of contacts 242, and these contacts 242 connect a printed circuit board (PCB) (not illustrating) in order to correspondence.
As shown in Figure 1, it should be noted that existing chip support plate 110 with the fiber material of certain thickness (about 800 microns) and the dielectric core layer 132 that organic resin was constituted, increases the hardness of chip support plate 110.But, with the via 136 that machine drilling was formed, be subjected to the materials limitations of dielectric core layer 132, its aperture minimum is about about 250 microns, thereby the line density of patterned line layer 130,134 that causes being positioned at the two sides of dielectric core layer 132 can't increase relatively, and the spacing between adjacent two vias 136 also must be greater than 550 microns, the winding length of the patterning conductor layer 130,134 between joint sheet 116a, the 116b of feasible corresponding connection increases, and then influences the usefulness of the signal transmission of substrate.
Therefore, under the requirement of high-density line and high number of contacts, the winding length that how to improve the line density of chip packaging substrate and dwindle the patterning conductor layer is an emphasis of the present utility model.
The utility model content
In view of this, task of the present utility model is providing a kind of combined type chip packaging substrate exactly, in order to line density that improves chip packaging substrate and the winding length that dwindles the patterning conductor layer.
For finishing above-mentioned task of the present utility model, the utility model proposes a kind of combined type chip packaging substrate, comprise a plurality of patterning conductor layers at least, overlap mutually in regular turn, wherein the outermost layer person of these patterning conductor layers has a plurality of joint sheets respectively.In addition, a plurality of dielectric layers are disposed between any two adjacent these patterning conductor layers, and wherein these dielectric layers is a ceramic dielectric layers one of at least, and the dielectric layer of all the other is an organic dielectric layer one of at least.In addition, one of these dielectric layers are passed in a plurality of conductions duct respectively, and electrically connect at least two patterning conductor layers.
For reaching the above-mentioned purpose of the utility model, the utility model proposes a kind of chip packaging structure, at least comprise a combined type chip support plate, has one first and corresponding one second, this combined type chip support plate has a plurality of patterning conductor layers, overlap mutually in regular turn, wherein these patterning conductor layers has a plurality of joint sheets near first person, a plurality of dielectric layers are disposed between wantonly two adjacent these patterning conductor layers, wherein these dielectric layers is a ceramic dielectric layers one of at least, and the dielectric layer of all the other is an organic dielectric layer one of at least.In addition, a plurality of conductions duct pass respectively these dielectric layers one of at least, and electrically connect at least two patterned conductive layers.In addition, chip configuration is in first of the combined type chip support plate, and is electrically connected to the combined type chip support plate via joint sheet.
Described according to preferred embodiment of the present utility model, above-mentioned dielectric layer comprises a dielectric core layer, and ceramic dielectric layers is the dielectric core layer.In addition, the mode that chip for example engages with chip bonding or lead, and be electrically connected to the combined type chip support plate.
Based on above-mentioned, the utility model is because of adopting the composite dielectric structure of ceramic dielectric layers and organic dielectric layer, makes the aperture in the conduction duct in the ceramic dielectric layers dwindle, with the wiring density of raising patterning conductor layer.In addition, the spacing between two in the ceramic dielectric layers conduction duct is dwindled, so that the winding length of two patterning conductor layers shortens relatively, and then improves the usefulness that the signal of substrate transmits.Simultaneously, ceramic dielectric layers has higher hardness with respect to organic dielectric layer, so can increase the intensity of baseplate.
For above-mentioned purpose, the feature and advantage of the utility model can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, elaborate.
Description of drawings
Fig. 1 illustrates existing a kind of generalized section of covering crystalline substance in conjunction with the chip packaging structure of kenel.
Fig. 2 illustrates the generalized section of existing a kind of chip packaging substrate.
Fig. 3 illustrates the generalized section of existing another kind of chip packaging substrate.
Fig. 4 illustrates the schematic diagram of a kind of chip packaging structure of the utility model one preferred embodiment.
Fig. 5 illustrates the generalized section of a kind of chip packaging structure of another preferred embodiment of the utility model.
The drawing reference numeral explanation
100: the chip packaging structure
110: chip support plate
112: the first
114: the second
116a, 116b: joint sheet
118: contact
120: chip
126: projection
130,134: the patterning conductor layer
132: the dielectric core layer
136: via
138: conductive hole
210: chip packaging substrate
202 (a) are (c) (d) (e) (b): organic dielectric layer
214 (a) (b) (c) (d) (e) (f): the patterning conductor layer
216: via
218: conductive hole
220a, 220b: joint sheet
222: contact
230: chip packaging substrate
232 (a) are (c) (d) (e) (b): organic dielectric layer
234 (a) (b) (c) (d) (e) (f): the patterning conductor layer
236: via
238: conductive hole
240a, 240b: joint sheet
242: contact
300: the chip packaging structure
310: the combined type chip support plate
312: the first
314: the second
316a, 316b: joint sheet
318: contact
320: chip
326: projection
332 (c): ceramic dielectric layers
(b) (d) (e) for 332 (a): organic dielectric layer
334 (a) (b) (c) (d) (e) (f): the patterning conductor layer
336: via (conduction duct)
338: conductive hole (conduction duct)
400: the chip packaging structure
410: the combined type chip support plate
412: the first
416a, 416b: joint sheet
418: contact
420: chip
426: projection
432 (a): ceramic dielectric layers
432 (b) are (d) (c): organic dielectric layer
434 (a) are (c) (d) (e) (b): the patterning conductor layer
436: via (conduction duct)
438: conductive hole (conduction duct)
Embodiment
Please refer to Fig. 4, it illustrates the schematic diagram of a kind of chip packaging structure of the utility model one preferred embodiment.This chip packaging structure 300 has a combined type chip support plate 310 and a chip 320.Wherein, chip 320 is disposed on first 312 of combined type chip support plate 310, and chip 320 is the mode with chip bonding (or lead joint), and is electrically connected to the joint sheet 316a of combined type chip support plate 310.In addition, chip support plate 310 also has a plurality of contacts 318, is disposed at second 314 of combined type chip support plate 310, and these contacts 318 for example are kenels such as soldered ball, stitch or conductive projection.
As shown in Figure 4, with the six stacking combined type chip packaging substrates that close is example, dielectric layer 332 is disposed between the wantonly two adjacent patterning conductor layers 334, wherein dielectric layer 332 is ceramic dielectric layers 332 (c) one of at least, and the dielectric layer 332 of all the other is organic dielectric layer 332 (a), 332 (b), 332 (d), 332 (e) one of at least.In the preferred case, the surface for example forms two organic dielectric layers 332 (a), 332 (b) in regular turn with Layer increasing method on the ceramic dielectric layers 332 (c), and the surface also forms two organic dielectric layers 332 (d), 332 (e) in regular turn with Layer increasing method under the ceramic dielectric layers 332 (c), and so dielectric layer 332 will be distributed in the both sides of ceramic dielectric layers 332 (c) with will being symmetry.。In addition, a plurality of vias 336 (promptly conduct electricity duct) run through ceramic dielectric layers 332 (c), and the two ends of via 336 electrically connect two patterning conductor layers 334 (c), 334 (d).In addition, a plurality of conductive holes 338 (promptly conduct electricity duct) are embedded among the organic in addition dielectric layer 332 of ceramic dielectric layers 332 (c) (a), 332 (b), 332 (d), 332 (e), and electrically connect wantonly two adjacent patterning conductor layers 334.Moreover, patterning conductor layer 334 (a), 334 (f) of outermost layer also have a plurality of joint sheet 316a, 316b, the corresponding projection 326 that connects chip of joint sheet 316a, and the surface of joint sheet 316b also disposes a plurality of contacts 318, and these contact 318 corresponding printed circuit board (PCB)s that connect.
It should be noted that, the material of ceramic dielectric layers 332 (c) for example is a ceramic material, it utilizes the dielectric structure that high temperature/low temperature co-fired technology constituted, because ceramic dielectric layers 332 (c) has splendid electrical characteristic, low stray inductance (inductance) and decoupling capacitance advantages such as (decoupling capacitance), is applicable to the dielectric layer as the high-density lines line structure.Therefore, as shown in Figure 4, present embodiment is as the dielectric core layer with ceramic dielectric layers 332 (c), in order to improve the hardness of chip support plate 310, surface and the lower surface on ceramic dielectric layers 332 (c) and patterning conductor layer 334 and organic dielectric layer 332 (a), 332 (b), 332 (d), 332 (e) can coincide in regular turn, because the conduction duct 336 of ceramic dielectric layers 332 (c), therefore its aperture minimum is about about 95 microns, is positioned at the patterned line layer 334 (c) on the two sides of ceramic dielectric layers 332 (c), the line density of 334 (d) can increase relatively.In addition, the spacings of adjacent two conductions between the ducts 336 also can reach 180 microns, thus the winding length of the patterning conductor layer 334 between joint sheet 316a, the 316b of corresponding connections can shorten relatively, with the usefulness of the signal transmission of raising combined type chip support plate 310.
Fig. 5 illustrates the generalized section of a kind of chip packaging structure of another preferred embodiment of the utility model, with the five stacking combined type chip packaging substrates that close 410 is example, dielectric layer 432 is disposed between the wantonly two adjacent patterning conductor layers 434, wherein dielectric layer 432 is ceramic dielectric layers 432 (a) one of at least, and the dielectric layer 432 of all the other is organic dielectric layer 432 (b), 432 (c), 432 (d) one of at least.Wherein, dielectric layer 432 is the both sides that are distributed in ceramic dielectric layers 432 (a) with being asymmetry, and ceramic dielectric layers 432 (a) is for example away from organic dielectric layer 432 (d) of the bottom, and near first 412 of combined type chip support plate 410.In addition, the surface for example has a patterning conductor layer 434 (a) on the ceramic dielectric layers 432 (a), and this patterning conductor layer 434 (a) has a plurality of joint sheet 416a, the corresponding projection 426 that connects chip 420, and the surface also forms the organic dielectric layer 432 of multilayer (b), 432 (c), 432 (d) in regular turn with Layer increasing method under the ceramic dielectric layers 432 (a).In addition, a plurality of vias 436 (promptly conduct electricity duct) run through ceramic dielectric layers 432 (a), and the two ends of via 436 electrically connect two patterning conductor layers 434 (a), 434 (b).In addition, a plurality of conductive holes 438 (promptly conduct electricity duct) are embedded among the organic in addition dielectric layer 432 of ceramic dielectric layers 432 (a) (b), 432 (c), 432 (d), and electrically connect wantonly two adjacent patterning conductor layers 434.Moreover the patterning conductor layer 434 (e) of the bottom also has a contact 418 more than a plurality of joint sheet 416b and corresponding the connection, with the chip packaging structure 400 of pie graph 5.These contact 418 corresponding printed circuit board (PCB)s (not illustrating) that connect, wherein contact for example is soldered ball, stitch or conductive projection.
By above explanation as can be known, the combined type chip packaging substrate of the utility model mainly has multilayer dielectric layer and is disposed between the wantonly two adjacent patterning conductor layers, wherein dielectric layer is ceramic dielectric layers one of at least, and the dielectric layer of all the other is organic dielectric layer one of at least.In addition, a plurality of conductions duct (conductive hole and via) passes one of dielectric layer respectively, and electrically connects at least two patterning conductor layers.Wherein, the ceramic dielectric series of strata can be the dielectric core layer, the aperture in its conduction duct will be relatively less than the aperture of existing organic dielectric layer, and the spacing between the conduction duct of ceramic dielectric layers will be relatively less than the spacing of the via that has organic dielectric layer now.In addition, because ceramic dielectric layers has splendid thermal conductivity with respect to organic dielectric layer, therefore the heat energy that chip produced can increase the radiating effect of combined type chip support plate directly by the area of dissipation that ceramic dielectric layers provided, to avoid too much centralized heat energy in chip.Moreover, ceramic dielectric layers has splendid thermal endurance and higher young's modulus with respect to organic dielectric layer, therefore ceramic dielectric layers can overcome phenomenons such as warpage that organic dielectric layer Yin Gaowen produces, distortion, and the thickness of ceramic dielectric layers thinning relatively (less than 800 microns) is to dwindle the integral thickness of combined type chip support plate.
In sum, the combined type chip packaging substrate of the utility model has following advantage:
(1) ceramic dielectric layers is with respect to existing organic dielectric layer, and its conductive hole road has less aperture, therefore can increase the line density of patterned line layer relatively.
(2) ceramic dielectric layers is with respect to existing organic dielectric layer, and the spacing between its adjacent two conduction ducts can be dwindled relatively, so the winding length of the patterning conductor layer between the joint sheet of corresponding connection can shorten relatively.
(3) ceramic dielectric layers has advantages such as splendid electrical characteristic, low stray inductance and high decoupling capacitance with respect to organic dielectric layer, is applicable in the chip support plate of elevated track density and high pin number.
(4) ceramic dielectric layers has splendid thermal endurance and higher young's modulus with respect to organic dielectric layer, therefore ceramic dielectric layers can overcome phenomenons such as warpage that organic dielectric layer Yin Gaowen produces or distortion, and the thinning relatively of the thickness of ceramic dielectric layers is to dwindle the integral thickness of combined type chip support plate.
(5) ceramic dielectric layers has splendid thermal conductivity with respect to organic dielectric layer, so the heat energy that chip produced can increase the radiating effect of combined type chip support plate directly by the area of dissipation that ceramic dielectric layers provided.
Though the utility model discloses as above in conjunction with the preferred embodiments; yet it is not in order to limit the utility model; those skilled in the art is not in breaking away from spirit and scope of the present utility model; can make some and change and retouching, therefore protection range of the present utility model should be looked the accompanying Claim person of defining and is as the criterion.
Claims (5)
1. combined type chip packaging substrate is characterized in that it comprises at least:
A plurality of patterning conductor layers overlap in regular turn mutually, and wherein the outermost layer person of those patterning conductor layers has a plurality of joint sheets respectively;
A plurality of dielectric layers are disposed between wantonly two adjacent those patterning conductor layers, and wherein those dielectric layers is a ceramic dielectric layers one of at least, and remaining those dielectric layer is an organic dielectric layer one of at least; And
A plurality of conductions duct, pass respectively those dielectric layers one of at least, and electrically connect those patterning conductor layers one of at least.
2. combined type chip packaging substrate as claimed in claim 1 is characterized in that, those dielectric layers comprise a dielectric core layer, and this ceramic dielectric layers is this dielectric core layer.
3. combined type chip packaging substrate as claimed in claim 2 is characterized in that, those dielectric layers are distributed in the both sides of this dielectric core layer with being symmetry.
4. combined type chip packaging substrate as claimed in claim 2 is characterized in that, those dielectric layers are distributed in the both sides of this dielectric core layer with being asymmetry.
5. combined type chip packaging substrate as claimed in claim 1 is characterized in that, only the one side of this ceramic dielectric layers is provided with remaining those dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU032727216U CN2641824Y (en) | 2003-06-24 | 2003-06-24 | Composite chip contruction substrade |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU032727216U CN2641824Y (en) | 2003-06-24 | 2003-06-24 | Composite chip contruction substrade |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2641824Y true CN2641824Y (en) | 2004-09-15 |
Family
ID=34301187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU032727216U Expired - Lifetime CN2641824Y (en) | 2003-06-24 | 2003-06-24 | Composite chip contruction substrade |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2641824Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100505225C (en) * | 2006-06-19 | 2009-06-24 | 台湾积体电路制造股份有限公司 | Connected pad structure |
| CN102339810A (en) * | 2010-07-20 | 2012-02-01 | 宏宝科技股份有限公司 | Silicon based substrate and fabrication method thereof |
| US11974031B1 (en) | 2021-04-16 | 2024-04-30 | Apple Inc. | Hybrid sensor shift platform with multi-core substrate for camera |
-
2003
- 2003-06-24 CN CNU032727216U patent/CN2641824Y/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100505225C (en) * | 2006-06-19 | 2009-06-24 | 台湾积体电路制造股份有限公司 | Connected pad structure |
| CN102339810A (en) * | 2010-07-20 | 2012-02-01 | 宏宝科技股份有限公司 | Silicon based substrate and fabrication method thereof |
| CN102339810B (en) * | 2010-07-20 | 2015-07-22 | 因厄费博斯由勒有限责任公司 | Silicon based substrate and fabrication method thereof |
| US11974031B1 (en) | 2021-04-16 | 2024-04-30 | Apple Inc. | Hybrid sensor shift platform with multi-core substrate for camera |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20130624 Granted publication date: 20040915 |