CN2613047Y - 积体电路堆叠封装组件 - Google Patents

积体电路堆叠封装组件 Download PDF

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CN2613047Y
CN2613047Y CNU032403755U CN03240375U CN2613047Y CN 2613047 Y CN2613047 Y CN 2613047Y CN U032403755 U CNU032403755 U CN U032403755U CN 03240375 U CN03240375 U CN 03240375U CN 2613047 Y CN2613047 Y CN 2613047Y
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integrated circuit
layer
plural wires
sealing
lower floor
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辛宗宪
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Kingpak Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

一种积体电路堆叠封装组件。为提供一种封装方便、降低生产成本、降低打线距离、减小弧线、提高封装良率的半导体封装组件，提出本实用新型，它包括基板、下层积体电路、第一封胶层、上层积体电路及第二封胶层；基板设有上表面及下表面；基板上表面设有形成凹槽的凸缘层，于凹槽内设有复数个第一接点，凸缘层上设有复数个第二接点；下层积体电路设于基板上表面上，并位于凹槽内，且藉由复数条导线电连接至第一接点上；第一封胶层填充于凹槽内，以将下层积体电路及复数条导线包覆住；上层积体电路系设于第一封胶层上，藉由复数条导线电连接至凸缘层的第二接点；第二封胶层系覆盖于上层积体电路上以将上层积体电路及复数条导线包覆住。

Description

积体电路堆叠封装组件
技术领域
本实用新型属于半导体封装组件，特别是一种积体电路堆叠封装组件。
背景技术
在科技的领域，各项科技产品皆以轻、薄、短小为其诉求，因此，对于积体电路的体积系越小越理想，更可符合产品的需求。而以往积体电路即使体积再小，亦只能并列式地电连接于电路板上，而在有限的电路板面积上，并无法将积体电路的容置数量有效地提升，故欲使产品达到更为轻、薄、短小的诉求，将有其困难的处。
因此，将若干个积体电路予以叠合使用，可达到轻、薄、短小的诉求。然而，若干个积体电路叠合时，上层积体电路将会压到下层积体电路的导线，以致将影响到下层积体电路的讯号传递。
如图1所示，习知的积体电路堆叠封装组件包括有基板10、下层积体电路12、上层积体电路14、复数个导线16及间隔层18。
下层积体电路12系设于基板10上，上层积体电路14系藉由间隔层18叠合于下层积体电路12上方，使下层积体电路12与上层积体电路14形成适当的间距20，如此，复数个导线16即可电连接于下层积体电路12边缘，使上层积体电路14叠合于下层积体电路12上时，不致于压损复数个导线16。
然而，习知的积体电路堆叠封装组件存在如下缺点：
1、必须另外黏设间隔层18，不但制造上较为不便，且制造成本相对提高。
2、上层积体电路14必须打线于基板10，其打线距离较长，且所产生的线弧较大，较易产生断线的情形。
发明内容
本实用新型的目的是提供一种封装方便、降低生产成本、降低打线距离、减小弧线、提高封装良率的积体电路堆叠封装组件。
本实用新型包括基板、下层积体电路、第一封胶层、上层积体电路及第二封胶层；基板设有上表面及下表面；基板上表面设有形成凹槽的凸缘层，于凹槽内设有复数个第一接点，凸缘层上设有复数个第二接点；下层积体电路设于基板上表面上，并位于凹槽内，且藉由复数条导线电连接至第一接点上；第一封胶层填充于凹槽内，以将下层积体电路及复数条导线包覆住；上层积体电路系设于第一封胶层上，藉由复数条导线电连接至凸缘层的第二接点；第二封胶层系覆盖于上层积体电路上以将上层积体电路及复数条导线包覆住。
其中：
凸缘层系一体成型于基板上表面上。
基板下表面设有复数个第三接点。
基板下表面上复数个第三接点上形成球栅阵列金属球。
下层积体电路系藉由复数条导线电连接至第一接点上。
由于本实用新型包括基板、下层积体电路、第一封胶层、上层积体电路及第二封胶层；基板设有上表面及下表面；基板上表面设有形成凹槽的凸缘层，于凹槽内设有复数个第一接点，凸缘层上设有复数个第二接点；下层积体电路设于基板上表面上，并位于凹槽内，且藉由复数条导线电连接至第一接点上；第一封胶层填充于凹槽内，以将下层积体电路及复数条导线包覆住；上层积体电路系设于第一封胶层上，藉由复数条导线电连接至凸缘层的第二接点；第二封胶层系覆盖于上层积体电路上以将上层积体电路及复数条导线包覆住。封装时，首先提供设有形成凹槽凸缘的基板；将下层积体电路设置于凹槽内，再以复数条导线电连接下层积体电路至基板的第一接点上；将第一封胶层填充于凹槽内，以将下层积体电路及复数条导线包覆住；将上层积体电路叠设于第一封胶层上，藉由复数条导线电连接至凸缘层的第二接点上；然后，以第二封胶层覆盖住上层积体电路及复数条导线；无须另行设置间隔层，在制造上较为便利；复数条导线系打线于凸缘层上，其所形成的打线距离较短，可节省线材，且其线弧较短，不会有断损的情形，可提高封装良率。不仅封装方便、降低生产成本，而且降低打线距离、减小弧线、提高封装良率，从而达到本实用新型的目的。
附图说明
图1、为习知的积体电路堆叠封装组件结构示意剖视图。
图2、为本实用新型结构示意剖视图。
图3、为本实用新型封装过程第一示意图。
图4、为本实用新型封装过程第二示意图。
具体实施方式
如图2所示，本实用新型包括基板30、下层积体电路32、第一封胶层34、上层积体电路36及第二封胶层38。
基板30设有上表面40及下表面42。
上表面40设有形成凹槽46的凸缘层44，并于凹槽46内设有复数个第一接点48，凸缘层44上设有复数个第二接点50。凸缘层44系一体成型于基板30上表面40上。
下表面42设有复数个第三接点52，并于第三接点52上形成球栅阵列金属球54。
下层积体电路32系设于基板30的上表面40上，并位于凹槽46内，且藉由复数条导线56电连接至第一接点48上。
第一封胶层34系填充于凹槽46内，用以将下层积体电路32及复数条导线56包覆住。
上层积体电路36系设于第一封胶层34上，藉由复数条导线58电连接至凸缘层44的第二接点50。
第二封胶层38系覆盖于上层积体电路36上，用以将上层积体电路36及复数条导线58包覆住。
封装时，如图3所示，首先提供基板30，使基板30设有形成凹槽46的凸缘层44；将下层积体电路32设置于凹槽46内，再以复数条导线56电连接下层积体电路32至基板30的第一接点48上；将第一封胶层34填充于凹槽46内，以将下层积体电路32及复数条导线56包覆住；如图4所示，将上层积体电路36叠设于第一封胶层34上，藉由复数条导线58电连接至凸缘层44的第二接点50上；然后，如图2所示，以第二封胶层38覆盖住上层积体电路36及复数条导线58，即可完本实用新型的封装。
如上所述，本实用新型具有如下优点：
1、本实用新型制造时无须另行设置间隔层，在制造上较为便利。
2、复数条导线58系打线于凸缘层44上，其所形成的打线距离较短，可节省线材，且其线弧较短，不会有断损的情形，可提高封装良率。

Claims (5)

1、一种积体电路堆叠封装组件，它包括基板、下层积体电路、上层积体电路及第二封胶层；基板设有上表面及下表面；下层积体电路设于基板上表面上；其特征在于所述的基板上表面设有形成填充第一封胶层凹槽的凸缘层，于凹槽内设有复数个第一接点，凸缘层上设有复数个第二接点；设于基板上表面上的下层积体电路位于凹槽内，且藉由复数条导线电连接至第一接点上；填充于凹槽内的第一封胶层将下层积体电路及复数条导线包覆住；上层积体电路系设于第一封胶层上，藉由复数条导线电连接至凸缘层的第二接点；第二封胶层系覆盖于上层积体电路上以将上层积体电路及复数条导线包覆住。
2、根据权利要求1所述的积体电路堆叠封装组件，其特征在于所述的凸缘层系一体成型于基板上表面上。
3、根据权利要求1所述的积体电路堆叠封装组件，其特征在于所述的基板下表面设有复数个第三接点。
4、根据权利要求3所述的积体电路堆叠封装组件，其特征在于所述的基板下表面上复数个第三接点上形成球栅阵列金属球。
5、根据权利要求1所述的积体电路堆叠封装组件，其特征在于所述的下层积体电路系藉由复数条导线电连接至第一接点上。
CNU032403755U 2003-03-11 2003-03-11 积体电路堆叠封装组件 Expired - Fee Related CN2613047Y (zh)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100539131C (zh) * 2007-11-29 2009-09-09 日月光半导体制造股份有限公司 电子元件封装结构
US7816769B2 (en) 2006-08-28 2010-10-19 Atmel Corporation Stackable packages for three-dimensional packaging of semiconductor dice
CN103579207A (zh) * 2013-11-07 2014-02-12 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN103579206A (zh) * 2013-11-07 2014-02-12 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN105826280A (zh) * 2015-01-07 2016-08-03 晟碟半导体（上海）有限公司 台阶形基板和具有其的半导体装置
CN103579207B (zh) * 2013-11-07 2016-11-30 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN109411487A (zh) * 2017-08-15 2019-03-01 胜丽国际股份有限公司 堆叠式感测器封装结构

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7816769B2 (en) 2006-08-28 2010-10-19 Atmel Corporation Stackable packages for three-dimensional packaging of semiconductor dice
CN101512762B (zh) * 2006-08-28 2012-05-23 爱特梅尔公司 用于半导体电路小片的三维封装的可堆叠封装
US8278150B2 (en) 2006-08-28 2012-10-02 Atmel Corporation Stackable packages for three-dimensional packaging of semiconductor dice
CN100539131C (zh) * 2007-11-29 2009-09-09 日月光半导体制造股份有限公司 电子元件封装结构
CN103579207A (zh) * 2013-11-07 2014-02-12 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN103579206A (zh) * 2013-11-07 2014-02-12 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN103579206B (zh) * 2013-11-07 2016-09-21 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN103579207B (zh) * 2013-11-07 2016-11-30 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN105826280A (zh) * 2015-01-07 2016-08-03 晟碟半导体（上海）有限公司 台阶形基板和具有其的半导体装置
CN109411487A (zh) * 2017-08-15 2019-03-01 胜丽国际股份有限公司 堆叠式感测器封装结构
CN109411487B (zh) * 2017-08-15 2020-09-08 胜丽国际股份有限公司 堆叠式感测器封装结构

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