CN2517178Y - Fractional frequency division output phase compensation device - Google Patents
Fractional frequency division output phase compensation device Download PDFInfo
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- CN2517178Y CN2517178Y CN 02218639 CN02218639U CN2517178Y CN 2517178 Y CN2517178 Y CN 2517178Y CN 02218639 CN02218639 CN 02218639 CN 02218639 U CN02218639 U CN 02218639U CN 2517178 Y CN2517178 Y CN 2517178Y
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Abstract
The utility model relates to a phase compensation device of fractional frequency division output which is a Pascal triangle numerical operational circuit of realizing the phase compensation of the N-digital fractional frequency division output and reducing the phase jitter. The device is composed of a plurality of multilevel accumulators which are connected in series, and each of the accumulators is composed of a delayer, a complementer, a full adder, the input terminal of the delayer is connected with the output of the front level accumulator, the output of the delayer is connected with the input terminal of the full adder, the input terminal of the full adder is also separately connected with the complementer, the output of the front level accumulator OUTn +1, the signal input terminal of the current level I N n ; the delayer is composed of a trigger D, the complementer is composed of or-gate and exclusive-or gate, the full adder is composed of a full adder circuit, the input terminal of the delayer, that is, the input terminal of the D trigger is connected with the output of the front level full adder circuit, the output of the D trigger is connected with the input terminal of the current full adder circuit and the input terminal of the or-gate, exclusive-or gate of current level complementer.
Description
One, technical field:
The utility model is the phase compensation of a kind of N-of realization numeral fractional frequency division output and the device that reduces phase jitter.
Two, background technology:
The needs of the increasingly mature and digital communication of semiconductor technology, promoted the ripe gradually of digital phase-locked loop technology, but people are more and more higher to the requirement of frequency of phase locking, promptly require to have capture function fast, higher phase demodulation frequency, the ultra-fine resolution of requirement is arranged simultaneously, good signal-to-noise (S/N) and less phase jitter.For the monocycle frequency synthesizer, if still adopt integer frequency divider can not satisfy the needs of application.People generally adopt N-numeral decimal frequency divider to the monocycle synthesizer in recent years, adopt different N position decimal (technology is to reach 48 at present) according to the requirement of system's loop, guarantee that the little number system of N-numeral has reached very meticulous frequency resolution, keeps the high workload frequency of phase detector simultaneously by the frequency dividing ratio of control frequency divider.The improvement of frequency resolution will be paid certain cost, and the control frequency dividing ratio will inevitably produce phase perturbation in output.
According to Pascal (Pascal) triangle numerical value operation result frequency dividing ratio is adjusted, can finely be realized the phase compensation of N-digital fractional frequency division output and reduce phase jitter.Control frequency dividing ratio N realizes reducing to export remaining phase jitter, (U.s.Patent sep.2,1,986 4609881)
Pascal (Pascal) triangle numerical value, i.e. (a-b)
nLaunching a coefficient, is the mathematical problem of classics, yet it is in communication, frequency compensation, and the good many-sides such as optimization of semiconductor device layout placement-and-routing all are widely used.Realize at present Pascal (Pascal) the triangle existing technology of numerical value computing or with the realization of tabling look-up of programming, or realize with the circuit of serial.The programming look-up method need use CPU, and is impracticable in N one fractional frequency division circuit.Though serial circuit speed increases, can't satisfy the quick response of fractional frequency division circuit, and serial circuit is very complicated, takies very large tracts of land, increase the cost of product.Can not finely realize the phase compensation of N-numeral fractional frequency division output and reduce phase jitter.
Three, summary of the invention:
(1) goal of the invention
Goal of the invention of the present utility model provide a kind of simple, parallel, quick, easy of integration, low-cost, can realize the phase compensation of the digital fractional frequency division output of N one and reduce the fractional frequency division output phase compensation arrangement of phase jitter
(2) technical scheme
Fractional frequency division output phase compensation arrangement of the present utility model is in series by multistage accumulator and forms, and finishes multistage accumulator and overflows quick arithmetical triangle (Pascal) numerical operation for input.Wherein each grade accumulator is made up of delayer, complementer, full adder, the output of the input termination previous stage accumulator of delayer, the output termination full adder of delayer and the input of complementer, the input of full adder also respectively with the output OUT of complementer, previous stage accumulator
N+1, signal input part INn at the corresponding levels joins; Delayer is made of d type flip flop, complementer by or the door and XOR gate, full adder is made of full adder circuit, the input of delayer is the output of the input termination previous stage full adder circuit of d type flip flop, the output of d type flip flop and the input of full adder circuit at the corresponding levels and complementer at the corresponding levels or the door, XOR gate input join, constitute terminal auxiliary circuit with door H and two two input XOR gate, two three input XOR gate, output numerical symbol end is " CH ".
In N-numeral decimal frequency divider circuit, an accumulator is exactly a digital integrator, available (1-Z
-1) expression.When a plurality of accumulator cascade, can be expressed as (1-Z
-1)
n, and with (1-Z
-1)
nLaunch, its coefficient delivery promptly constitutes sequence shown in figure three.In N-numeral decimal frequency divider circuit, by the state that different accumulators are overflowed, by different time sequencings, calculate according to Pascal shown in the figure three (Pascal) triangle numerical value, result of calculation is adjusted frequency dividing ratio, just can finely realize the phase compensation and the minimizing phase jitter of the output of N-numeral fractional frequency division.
(3) technique effect
The circuit that accumulator not at the same level constitutes overflows, and calculates through Pascal (Pascal) triangle numerical value, and result of calculation is adjusted frequency dividing ratio and improved influence to phase jitter.Accumulator constantly overflow mutual stack, more early, more frequent generation makes phase error better be offset at last in this cycle in the phase place correction.
Realize the output of N-numeral decimal frequency divider obtain good phase compensation and preferably the frequency resolution key be how the numerical value shown in Pascal shown in the figure three (Pascal) triangle, by different overflow statuss, according to the different sequential cycles, fast and accurately correction value is calculated, made the frequency dividing ratio of frequency divider in time obtain revising.
Realize that Pascal (Pascal) triangle numerical value calculates, existing technology is finished with programming, serial circuit.Programmed method is impracticable in N-numeral decimal frequency divider.And the serial circuit mode of operation, because of positive and negative numerical value being arranged, the operation result tape symbol in Pascal (Pascal) the triangle numerical value, so circuit structure is complicated, response is slow, digital accumulator is overflowed can not obtain corresponding correction value fast, and the phase compensation that just gets entire circuit lags.
In addition, the utility model also has following characteristics:
1, adopt the parallel processing mode, when input changed, output can quick and precisely reflect.
2, fast counting circuit is simple in structure, aligns, the negative value computing, directly is blended together, and once finishes and must not carry out the sign bit operation, and computing is quick.
3, previous cycle overflow status can be memorized by delay cell, in back one-period participation computing overflow status can not take place and lose phenomenon, safe and reliable.
Four, description of drawings:
Figure one, fractional frequency division output phase compensation arrangement block diagram.Delayer A, complementer B, full adder C are wherein arranged.
Figure two, control frequency dividing ratio N realize reducing remaining phase jitter work block diagram.
Figure three, Pascal (Pascal) triangle numerical value overflow control coefrficient to accumulator.
Figure four, frequency dividing ratio adjustment are to the influence of phase jitter.
Figure five, fractional frequency division output phase compensation arrangement circuit.Wherein have d type flip flop D, full adder circuit G or the door E, XOR gate F, with the door H.
Figure six, level Four Pascal (pascal) triangle numerical value analog computation result
Five, embodiment
Whole circuit of the present utility model can design and be integrated on the integrated circuit as a circuit module.Also can form with discrete component, as:
D type flip flop D: model is CD4076; Or door E: model is CD4071;
XOR gate F: model is CD4070; Full adder circuit G: model is CD4008;
With door H: model is CD4081;
Fractional frequency division output phase compensation arrangement is in series by multistage accumulator and forms, and finishes multistage accumulator and overflows quick Pascal (Pascal) triangle numerical value computing for input.Wherein each grade accumulator is made up of delayer A, complementer B, full adder C, the output of the input termination previous stage accumulator of delayer A, the input of the output termination full adder C of delayer A, the input of full adder C also respectively with the output OUT of complementer B, previous stage accumulator
N+1, signal input part INn at the corresponding levels joins.Delayer A is made of d type flip flop D, complementer B by or door E and XOR gate F, full adder C is made of full adder circuit G, the input of delayer A is the output of the input termination previous stage full adder circuit G of d type flip flop D, the output of d type flip flop D and the input of full adder circuit G at the corresponding levels and complementer at the corresponding levels B's or the door, XOR gate input join.Constitute terminal auxiliary circuit with door H and two two input XOR gate (equivalence is three input XOR gate in the circuit), two three input XOR gate, the symbol end of exporting positive and negative numerical value is " CH ".
The utility model constitutes Pascal (Pascal) the triangle numerical value computing circuit of finishing of a level Four and sees figure five.Circuit diagram five is done following explanation: wherein CP is a clock signal, IN1, IN2, IN3, IN4 correspond respectively to preceding 4 row (corresponding accumulator has when overflowing to be " 1 ") of Pascal (pascal) triangle numerical value, CL is a reset signal, before circuit working,, prevent to occur not stationary state with the trigger zero clearing.D0, D1, D2, D3 are four outputs from low to high, and expression participates in the overflow status of accumulator to revise after according to the computing of different sequential cycle the numerical value of frequency divider frequency dividing ratio N by Pascal (Pascal) triangle numerical value.CH is-symbol position " 0 " expression output D0～D3 be on the occasion of." 1 " expression output D0～D3 is a negative value.Analog result is shown in figure six.
Claims (3)
1, a kind of fractional frequency division output phase compensation arrangement, it is characterized in that this device is in series by multistage accumulator forms, finish multistage accumulator overflow for the input quick arithmetical triangle numerical value numerical operation, wherein each grade accumulator is made up of delayer (A), complementer (B), full adder (C), the output of the input termination previous stage accumulator of delayer (A), the input of the output termination full adder (C) of delayer (A), the input of full adder (C) also respectively with the output OUT of complementer (B), previous stage accumulator
N+1, signal input part INn at the corresponding levels joins.
2, fractional frequency division output phase compensation arrangement according to claim 1, it is characterized in that delayer (A) is made of d type flip flop (D), complementer (B) by or door (E) and XOR gate (F) formation, full adder (C) is made of full adder circuit (G), the input of delayer (A) is the output of the input termination previous stage full adder circuit (G) of d type flip flop (D), the input of the output of d type flip flop (D) and full adder circuit at the corresponding levels (G) and complementer at the corresponding levels (B) or the door, XOR gate input join.
3, fractional frequency division output phase compensation arrangement according to claim 1 and 2 is characterized in that forming terminal auxiliary circuit, output numerical symbol end (CH) with door H and two two input XOR gate (F8, F9), two three input XOR gate (F7, F4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02218639 CN2517178Y (en) | 2002-01-29 | 2002-01-29 | Fractional frequency division output phase compensation device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02218639 CN2517178Y (en) | 2002-01-29 | 2002-01-29 | Fractional frequency division output phase compensation device |
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| CN2517178Y true CN2517178Y (en) | 2002-10-16 |
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| CN 02218639 Expired - Fee Related CN2517178Y (en) | 2002-01-29 | 2002-01-29 | Fractional frequency division output phase compensation device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841325A (en) * | 2010-05-25 | 2010-09-22 | 华东师范大学 | Hardware model for three-order four-bit error feedback incremental summation modulator |
| CN109547386A (en) * | 2018-11-27 | 2019-03-29 | 海安南京大学高新技术研究院 | PD for high-order Sigma-Delta modulatorλThe design method of phase compensator |
| CN112213733A (en) * | 2020-12-03 | 2021-01-12 | 深圳市海创光学有限公司 | Synchronous voltage-controlled adjustable pulse generating circuit and fiber laser |
-
2002
- 2002-01-29 CN CN 02218639 patent/CN2517178Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841325A (en) * | 2010-05-25 | 2010-09-22 | 华东师范大学 | Hardware model for three-order four-bit error feedback incremental summation modulator |
| CN101841325B (en) * | 2010-05-25 | 2011-07-27 | 华东师范大学 | Hardware model for three-order four-bit error feedback incremental summation modulator |
| CN109547386A (en) * | 2018-11-27 | 2019-03-29 | 海安南京大学高新技术研究院 | PD for high-order Sigma-Delta modulatorλThe design method of phase compensator |
| CN112213733A (en) * | 2020-12-03 | 2021-01-12 | 深圳市海创光学有限公司 | Synchronous voltage-controlled adjustable pulse generating circuit and fiber laser |
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| CF01 | Termination of patent right due to non-payment of annual fee |