CN2492976Y - Automatic gain control circuit for analogue signal - Google Patents
Automatic gain control circuit for analogue signal Download PDFInfo
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- CN2492976Y CN2492976Y CN 01261062 CN01261062U CN2492976Y CN 2492976 Y CN2492976 Y CN 2492976Y CN 01261062 CN01261062 CN 01261062 CN 01261062 U CN01261062 U CN 01261062U CN 2492976 Y CN2492976 Y CN 2492976Y
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Abstract
The utility model relates to a front end signal processing arrangement of analog-to-digital converting with automatic adjustment gain, which comprises a buffer circuit, a signal amplification/attenuation circuit, a gain control front end processing circuit, and a signal amplification/attenuation gain control circuit. The front end signal processing arrangement of analog-to-digital converting of automatic adjustment gain generates a set of gain control signals S1 and S2 through hardware, and the amplified/attenuated gain of the signals is then controlled by the signals to automatically adjust the amplification or attenuation of the input signals. Simultaneously, during the operation, a microprocessor can select the correct restoration magnification according to the signals, and ensure the accordance of the computed result and the input signals.
Description
Technical field
The utility model relates to a kind of treatment circuit of analog signal, and the automatic gain that particularly relates to a kind of analog signal is adjusted control circuit.
Background technology
Simulation often is applied in various computer equipments, measuring instrument, the industrial control equipment digital conversion circuit, with the signal that will simulate kenel (for example temperature, pressure ... Deng) convert the signal of digital kenel to, so that the reception of digital processing unit and further handling.
General known single multiplying power simulation to the structure of digital conversion circuit as shown in Figure 1, its circuit mainly includes a signal supervisory instrument 10, a front-end processing circuit 11, a signal amplification circuit 12, a sampling/holding circuit 13, an adc 14 and a microprocessor 15.After signal supervisory instrument 10 detects the input signal Vin that a simulation is arranged, at first by front-end processing circuit 11 with this analog input signal Vin do the decay of appropriate multiplying power (multiplying power that for example decays 1/a) to the analog signal Vin ' of the acceptable margin of safety of system afterwards, by signal amplification circuit 12 this Yin ' appropriateness is amplified again or decay and obtain an analog signal Vin " (for example enlargement ratio b); this analog input signal Vin " do the sampling and the maintenance (Sampling and Holding) of signal again by sampling/holding circuit 13, the last conversion of signals that will simulate through adc 14 again becomes the signal of digital kenel, delivers in the microprocessor 15 and handles.
But, when carrying out numerical operation, will not be the b/a of original signal if consider the operation result that produces summation multiplying power b/a at the enlargement ratio b of the decay multiplying power 1/a of front-end processing circuit 11 and signal amplification circuit 12 at microprocessor 15.Therefore, circuit designers must place reduction multiplying power a/b the calculation procedure of microprocessor 15 in advance, is consistent with input signal Vin to guarantee operation result.
Above-mentioned circuit structure and signal processing mode only can be applicable to the transfer process control of single multiplying power.Signal processing for the conversion program of the multiple multiplying power of needs, then need design a kind of treatment circuit (as shown in Figure 2) with multiple multiplying power handoff functionality, in the conversion control circuit of multiplying power more than this kind, also mainly include a signal supervisory instrument 20, the front-end processing circuit of multiplying power more than one 21, the amplification of ratio signals more than a circuit 22, a sampling/holding circuit 23, an adc 24 and a microprocessor 25.Wherein this many multiplying powers front-end processing circuit 21 has for example three kinds of decay multiplying power 1/a1,1/a2 and 1/a3, and three kinds of enlargement ratio b1, b2 and b3 are also arranged at many ratio signals amplification circuit 22, add up to produce nine kinds of sum total multiplying power bn/am, m=1-3 wherein, n=1-3.Circuit designers must be in advance with nine kinds of reduction multiplying power am/bn, m=1-3, and n=1-3, data place the calculation procedure of microprocessor 25, and wherein maximum multiplying power is a3/b3, and minimum multiplying power a1/b1 is consistent with analog input signal Vin to guarantee operation result.But, microprocessor 25 is being chosen in the suitable reduction multiplying power am/bn, general known method has two kinds, first method is to need to add determining program in microprocessor 25 calculation procedures, select suitable reduction multiplying power am/bn by microprocessor 25 according to judged result, second method is manually to select suitable reduction multiplying power am/bn.
With regard to aforementioned first kind of reduction multiplying power choosing method, as shown in Figure 2, microprocessor 25 is at the beginning during executive program, reduction multiplying power am/bn can be decided to be maximum multiplying power a3/b3 opening the beginning state, and diverter switch is placed the b3 position of the 1/a3 and the signal amplification circuit 22 of front-end processing circuit 21 respectively, when microprocessor 25 calculating are overload (Overflow) state with judged result, the in proper order big again multiplying power a3/b2 of microprocessor 25 continues to calculate and judges, and diverter switch is placed the b2 position of the 1/a3 and the signal amplification circuit 22 of front-end processing circuit 21 respectively, when if the result still is overload, calculating and judgement that the in proper order big again multiplying power a3/b1 of microprocessor 25 continues, calculated value when judged result is no longer transshipped is consistent with analog input signal Vin, and microprocessor 25 just stops to calculate and determining program.
And in second kind the reduction multiplying power choosing method, a manual multiplying power diverter switch 26 (consulting shown in Figure 3) must be set in control circuit.In this kind circuit structure, its circuit structure is identical with circuit structure shown in Figure 2, also design has determining program in microprocessor 25 calculation procedures, but can't automatically diverter switch be placed the bn position of the 1/am and the signal amplification circuit 22 of front-end processing circuit 21 respectively, whether but need to rely on the user to look result of calculation is overload, change hands moving multiplying power selector switch 26 to the suitable position of the switch and dial with manual mode, calculated value when judged result is no longer transshipped is consistent with input signal Vin, just stops to dial changing hands moving multiplying power selector switch 26.
In aforesaid second kind of reduction multiplying power choosing method, must can reach correct simulation function by switch magnification switch manually to digital translation, aspect industry applications, show deficiency is arranged, and in first kind of reduction multiplying power choosing method, though have the translation function of automatic judgement, switch magnification, but in the calculating and deterministic process each time of its microprocessor, microprocessor all must expend considerable time resource could obtain last correct result, for the timely rapid-action of needs system, these two kinds of methods clearly all can't be suitable for.
Summary of the invention
Because the aforementioned shortcoming of having used technology, main purpose of the present utility model promptly provides a kind of automatic gain of analog signal and adjusts control circuit, produce one group of gain control signal S1, S2 by control circuit, organize the gain of signal control signal amplification more thus, automatically adjust the amplification or the decay of input signal, simultaneously, also can organize signal during the microprocessor computing and choose correct reduction multiplying power, guarantee that result of calculation is consistent with input signal according to this.When automatic gain of the present utility model adjust control circuit be combined in a simulation to digital conversion circuit in the time, can cooperate microprocessor to carry out the automatic multiplying power handoff functionality of analog input signal, and when carrying out the conversion processor of signal, energy fast reaction in time the gain automatically adjustment.
In order to reach above-mentioned the utility model purpose, to adjust in the control circuit preferred embodiment at the automatic gain of analog signal of the present utility model, it includes a buffer circuit, in order to cushion an analog input signal; One signal amplification circuit is accepted the output signal of buffer circuit, and in the gain ranging that is selected, this signal is given amplification to the acceptable opereating specification of adc; One gain controlling front-end processing circuit receives this analog input signal simultaneously, earlier this signal is decayed in the safe amplitude range, and next is clamped on positive half cycle, and then this signal is cushioned the appropriate scope that is amplified to, to export positive half cycle voltage division signal; One signal amplification gain control circuit, receive the D. C. value behind the output signal rectifying and wave-filtering of this gain controlling front-end processing circuit, and behind comparator, producing one group of gain control signal, gain control signal is promptly chosen correct yield value as this signal amplification circuit.
Preferably, the automatic gain of analog signal of the present utility model is adjusted control circuit and is more included an adc, convert the signal of digital kenel in order to the analog output signal that this signal amplification circuit is exported, deliver to again in the microprocessor.And this microprocessor also receives the gain control signal that this signal amplification gain control circuit is produced simultaneously, and chooses correct reduction multiplying power according to this gain control signal, is consistent with input signal to guarantee result of calculation.
This buffer circuit is a voltage follower, makes input signal borrow the high input impedance ground connection of voltage follower.This signal amplification circuit includes the first simulation multiplexer, the second simulation multiplexer, many multiplying powers resistance of several precision resistances compositions and the inverting amplifier of an operational amplifier.This front end signal processing unit includes bleeder circuit, clamping diode and buffer amplifier, and this signal amplification gain control circuit includes one group of current rectifying and wave filtering circuit, comparator circuit and clamping diode circuit.
The one group of gain control signal that produces by above-mentioned signal amplification control circuit and the gain of may command signal amplification, automatically adjust the amplification or the decay of input signal apace, simultaneously, this control circuit can be applicable in the digital circuit, cooperates a microprocessor to carry out the automatic gain control and construction one adc at a high speed of analog signal.
Other purpose of the present utility model and structural design thereof will be done one and describe in detail by following embodiment explanation and with reference to shown in the drawings graphic.
Description of drawings
Fig. 1 shows the circuit block diagram of known single multiplying power simulation to digital conversion control circuit;
Fig. 2 shows the circuit block diagram of known many multiplying power simulations to digital conversion control circuit;
Fig. 3 shows the circuit block diagram of the many multiplying power simulations of known manual switchover formula to digital conversion control circuit;
Fig. 4 shows that one includes the circuit block diagram of the simulation of automatic gain adjustment control circuit of the present utility model to digital conversion control circuit;
Fig. 5 is the control circuit functional block diagram that automatic gain is adjusted control circuit in the further displayed map 4;
Fig. 6 is buffer circuit and a signal amplification embodiment of circuit circuit diagram in the displayed map 5;
Fig. 7 is the embodiment circuit diagram of gain controlling front-end processing circuit and signal amplification gain control circuit in the displayed map 5.
Embodiment
Consult shown in Figure 4ly, it is to show that one includes automatic gain of the present utility model and adjusts the circuit block diagram of the simulation of control circuit to digital conversion control circuit.In this circuit structure, mainly include a signal supervisory instrument 1, a front-end processing circuit 2, automatic gain adjustment control circuit 3, a sampling/holding circuit 4, an adc 5 and a microprocessor 6.Adjusting control circuit 3 by automatic gain of the present utility model cooperates microprocessor 6 to carry out analog input signal automatic gain adjustment fast.
Fig. 5 is the control circuit functional block diagram that automatic gain is adjusted control circuit 3 in the further displayed map 4, and it shows that automatic gain adjustment control circuit 3 of the present utility model includes a buffer circuit 31, a signal amplification circuit 32, a gain controlling front-end processing circuit 33, a signal amplification gain control circuit 34.
After signal supervisory instrument 1 detection has an analog input signal Vin, produce an output signal VA, front-end processing circuit 2 can decay to the acceptable margin of safety Vin ' of system with this analog input signal appropriateness, via buffer circuit 31 make signal can the appropriateness impedance matching and the buffering of signal, and then Vin ' appropriateness amplified or decay to Vin by signal amplification circuit 32 ", amplify or decay into Vin as for Vin ' " gain select then by 34 decisions of signal amplification gain control circuit.
When front end treatment circuit 2 when handling input signal Vin, the output signal VA of signal supervisory instrument 1 also can be sent to the gain controlling front-end processing circuit 33 in the automatic gain adjustment control circuit 3, produce gain control signal S1, S2 by signal amplification gain control circuit 34 again, this gain control signal S1, S2 can deliver to signal amplification circuit 32, amplify or the decay multiplying power with the decision signal.This gain control signal S1, S2 also can deliver in the microprocessor 6 simultaneously.
Fig. 6 is the embodiment circuit diagram of buffer circuit 31 and signal amplification circuit 32 in the displayed map 5; Fig. 7 is the embodiment circuit diagram of gain controlling front-end processing circuit 33 and signal amplification gain control circuit 34 in the displayed map 5.Buffer circuit 31 in the utility model is voltage followers, makes input signal borrow the high input impedance ground connection of voltage follower.Include the first simulation multiplexer MUX1, the second simulation multiplexer MUX2, many multiplying powers resistance of several precision resistances compositions and the inverting amplifier OP4 that an operational amplifier is constituted in the signal amplification circuit 32.
The first simulation multiplexer MUX1 is the analog switch of four groups of input channels of a tool (Channel), one group of delivery channel and two groups of control lines, input channel is connected with the output of buffer circuit, two groups of control lines are connected with gain control signal S1, S2 respectively, select one group of input channel to be connected with delivery channel from four groups of input channels according to gain control signal S1, S2.
Three groups of multiplying powers that the second simulation multiplexer MUX2, three groups of precision resistance R2, R3, R4 form constitute with a high-accuracy operational amplifier OP4 adjusts the inverting amplifier that gains automatically.Three groups of input channels of the second simulation multiplexer MUX2 are connected with three groups of multiplying powers respectively, from three groups of input channels, select one group of input channel to be connected by gain control signal S1, S2 with delivery channel, meaning promptly selects one group of multiplying power and high-accuracy operational amplifier OP4 to form inverting amplifier according to gain control signal S1, S2, with the appropriate amplification of signal amplitude to the acceptable opereating specification of adc.
Front end signal treatment circuit 33 of the present utility model includes bleeder circuit Ra ', Rb ', clamping diode D1 and buffer amplifier OP5, wherein this bleeder circuit is connected with low resistance resistance by accurate high resistance measurement, it acts on the decay of input signal VA appropriateness, voltage division signal is clamped on positive half cycle by clamping diode D1 then, buffer amplifier and system earth that last positive half cycle voltage division signal constitutes through a voltage follower.
Signal amplification gain control circuit 34 includes one group of current rectifying and wave filtering circuit, comparator circuit and two groups of clamping diodes.Wherein this current rectifying and wave filtering circuit is the filter circuit that is made of a rectifier diode D2 and resistance R 6, capacitor C 1, and it acts on the positive half cycle voltage division signal rectifying and wave-filtering that this front end signal treatment circuit 33 is sent here and becomes a direct current signal V6.Comparator circuit includes a high level comparator OP6 and low-level comparator OP7, the reference voltage VH of high level comparator OP6, be the rectifying and wave-filtering D. C. value of 10 volts of state switching points in the low gain AL district of the middle gain A M district of 1-10 volt and 10-100 volt, the reference voltage VL of low-level comparator, be the rectifying and wave-filtering D. C. value of 1 volt of state switching points in the middle gain A M district of the high-gain AH district of 0-1 volt and 1-10 volt, when the same time of rectifying and wave-filtering direct current signal V6 respectively with height, low-level comparator relatively after, can produce one group of gain control signal (S1, S2).
Two groups of clamping diode D3, D4 in the signal amplification gain control circuit 34 lay respectively at the output of high and low level comparator OP6, OP7; it acts on the output level of guaranteeing comparator and is clamped between the power supply V+ (" 1 ") and ground (" 0 ") of comparator, with protection microprocessor 6.
Suppose among the embodiment of the present utility model, analog input signal VA opereating specification is the 04--10 volt, and the range of choice of supposing the Gain Automatic adjustment of present embodiment be respectively high-gain AH district, the 1--10 volt of 0--1 volt middle gain A M district, with the low gain AL district of 10--100 volt, suppose to simulate in the present embodiment truth table of multiplexer MUX1 and MUX2 and gain controlling truth table shown in table 1 and table 2:
(table 1)
(table 2)
| | X Y | |
| 1 1 | | |
| 1 0 | X1 Y1 | |
| 0 1 | X2 Y2 | |
| 0 0 | X3 Y3 |
| S1 S2 | X Y | ||
| As VA＜1V | Vb＜VL＜ | 1 1 | X0 Y0 |
| As 1V＜VA＜10V | VL＜Vb＜ | 1 0 | X1 Y1 |
| As 10V＜VA＜100V | VL＜VH＜Vb | 0 0 | X3 Y3 |
Input signal VA directly enters front-end processing circuit 2, and the front-end processing circuit 2 of present embodiment constitutes a bleeder circuit (as shown in Figure 6) by resistance R a, Rb, Rc and Rd, produces voltage division signal Va, Vb and Vc, wherein Va＞Vb＞Vc.
Va=VA* (Rb+Rc+Rd)/R, magnification ratio X0=(Rb+Rc+Rd)/R
Vb=VA* (Rc+Rd)/R, magnification ratio X1=(Rc+Rd)/RVc=VA*Rd/R, magnification ratio X3=Rd/R
R＝Ra+Rb+Rc+Rd
Va, Vb and Vc are respectively via the operational amplifier OP1 in the buffer circuit 31, after OP2 and OP3 and the system matches impedance, voltage division signal is the input X0 of the first simulation multiplexer MUX1 of position in signal amplification circuit 32 respectively, X1 and X3, what component to press signal to be selected as for, then by signal amplification gain control circuit 34 according to gain controlling truth table (table 1), selected one group of gain control signal S1, S2 chooses voltage division signal, simultaneously this group gain control signal S1, S2 also can choose with operational amplifier OP4, the second simulation multiplexer MUX2 is one group of amplifier multiplying power Y0 or the Y1 or the Y3 of core:
Magnification ratio Y0=-R2/R1
Magnification ratio Y1=-R3/R1
Magnification ratio Y3=-R4/R1
This moment amplifier OP4 output signal magnification ratio may for
X0*Y0＝-(Rb+Rc+Rd)*R2/R*R1
Or X1*Y1=-(Rc+Rd) * R3/R*R1
Or X3*Y3=-Rd*R4/R*R1
Directly enter the same time of front-end processing circuit 2 as input signal VA, input signal VA also is introduced into gain controlling front-end processing circuit 33, the component volt circuit that the gain controlling front-end processing circuit 33 of present embodiment mainly is made of resistance R a ' and Rb ', an one clamping diode D1 and a buffer amplifier OP5 constitute (consulting shown in Figure 7), gain controlling front-end processing circuit 33 is mainly obtaining positive half wave gain judgement signal V6 ', then in signal amplification gain control circuit 34 by diode D2, the filter rectifier that resistance R 6 and capacitor C 1 constitute, the positive half wave gain is judged that signal V6 ' filter rectification becomes DC current gain to judge signal V6, DC current gain judge signal V6 more respectively with high level comparator OP6, low-level comparator OP7 relatively produces one group of gain control signal S1, S2 chooses with the gain of control simulation multiplexer MUX1 and MUX2.The high level reference point voltage VH of high level comparator OP6, be the D. C. value of 10 volts of state switching points in the low gain AL district of the middle gain A M district of the Gain Automatic adjustment range of choice of present embodiment 1-10 volt and 10--100 volt, same situation, the low level reference point voltage VL of low-level comparator OP7 is the D. C. value of 1 volt of state switching points in the middle gain A M district of the high-gain AH district of the Gain Automatic adjustment range of choice of present embodiment 0--1 volt and 1--10 volt; The clamping diode D3 of high and low level comparator output, the effect of D4 at the positive output level of nip level comparator, all are positioned at positive level to guarantee gain control signal S1, S2.
When the signal amplitude of input signal VA is positioned at the range of choice of Gain Automatic adjustment of 0--1 volt, the DC current gain of VA is judged signal V6＜VL＜VH, therefore, the output of low-level comparator OP7-gain control signal S2 is high level at this moment, S2=" 1 ", and the output of high level comparator OP7-gain control signal S1 also is a high level, S1=" 1 ", be gain control signal (S1, S2) be (1,1), the truth table 1 of contrast simulation multiplexer MUX1 and MUX2, X contact and the X0 contact of the first simulation multiplexer MUX1 are connected in the signal amplification circuit 32 at this moment, and Y contact and the Y0 contact of the second simulation multiplexer MUX2 are connected, anticipate promptly, the peak value VY of the output Y of OP4 is at this moment
R＝Ra+Rb+Rc+Rd
This peak value VY is behind sampling/holding circuit 4 digital samplings, by adc 5 sampling value is changed into digital code then, at last again by microprocessor 6 with the digital code calculation process, but, microprocessor will face two difficult problems 6 this moments, one for the result of calculation process is not the result of input signal VA, but input signal VA decays
The result, therefore, desire or result correctly must multiply by VY reduction multiplying power VA/VY0=again
So we must place program in advance with reduction multiplying power VA/VY0; Same situation, when the signal amplitude of input signal VA is positioned at the range of choice of Gain Automatic adjustment of 1--10 volt, the DC current gain of VA is judged signal VL＜V6＜VH, gain control signal (S1, S2) be (1,0), the truth table 1 of contrast simulation multiplexer MUX1 and MUX2, X contact and the X1 contact of the first simulation multiplexer MUX1 are connected in the signal amplification circuit 32 at this moment, Y contact and the Y1 contact of the second simulation multiplexer MUX2 are connected, anticipate promptly, the peak value VY of the output Y of OP4 is at this moment
R＝Ra+Rb+Rc+Rd
The reduction multiplying power
Must place program in advance; When the signal amplitude of input signal VA is positioned at the range of choice of Gain Automatic adjustment of 10--100 volt, the DC current gain of VA is judged signal VL＜VH＜V6, gain control signal (S1, S2) be (0,0), the truth table 1 of contrast simulation multiplexer MUX1 and MUX2, X contact and the X3 contact of the first simulation multiplexer MUX1 are connected in the signal amplification circuit 31 at this moment, Y contact and the Y3 contact of the second simulation multiplexer MUX2 are connected, and anticipate promptly, and the peak value VY of the output Y of OP4 is at this moment
R＝Ra+Rb+Rc+Rd
The reduction multiplying power
Reduction multiplying power VA/VY3 also must place program in advance; To face second difficult problem this moment, how from program, to choose correct reduction multiplying power when being microprocessor 6 calculation process? because gain control signal (S1, S2) the decay multiplying power of energy control input signals VA, if microprocessor 6 also can gain acceptance in control signal (S1, S2) time, can choose correct reduction multiplying power, therefore, we only must be with gain control signal (S1, S2) in control decay multiplying power, also pass to microprocessor 6, (S1 S2) chooses correct reduction multiplying power, can obtain correct operation result according to gain control signal by program again.
By above explanation as can be known, by control circuit of the present utility model, the amplification yield value of may command analog signal, simultaneously, this control circuit can be applicable in the digital circuit, cooperates a microprocessor to carry out the automatic gain control and construction one adc at a high speed of analog signal.So value on the dark tool industry of the utility model.
Below preferred embodiment of the present utility model has been done an explanation, all personnel that are skillful in this technology, when can doing other all improvement according to above-mentioned explanation, but these change in the scope that still belongs to claim of the present utility model and defined.
Claims (12)
1. the automatic gain of an analog signal is adjusted control circuit, and the yield value in order to automatic adjustment one analog input signal is characterized in that, this control circuit includes:
One buffer circuit is in order to cushion an analog input signal;
One signal amplification circuit is accepted the output signal of buffer circuit, and in the gain ranging that is selected, this signal is given amplification to the acceptable opereating specification of adc;
One gain controlling front-end processing circuit receives this analog input signal simultaneously, earlier this signal is decayed in the safe amplitude range, and next is clamped on positive half cycle, and then this signal is cushioned the appropriate scope that is amplified to, to export positive half cycle voltage division signal;
One signal amplification gain control circuit, receive the D. C. value behind the output signal rectifying and wave-filtering of this gain controlling front-end processing circuit, and behind comparator, producing one group of gain control signal, gain control signal is promptly chosen correct yield value as this signal amplification circuit.
2. the automatic gain of analog signal as claimed in claim 1 is adjusted control circuit, it is characterized in that: more include an adc, convert the signal of digital kenel in order to the analog output signal that this signal amplification circuit is exported, deliver to again in the microprocessor.
3. the automatic gain of analog signal as claimed in claim 2 is adjusted control circuit, it is characterized in that: this microprocessor also receives the gain control signal that this signal amplification gain control circuit is produced simultaneously, and choose correct reduction multiplying power according to this gain control signal, be consistent with input signal to guarantee result of calculation.
4. the automatic gain of analog signal as claimed in claim 1 is adjusted control circuit, and it is characterized in that: this buffer circuit is a voltage follower, makes input signal borrow the high input impedance ground connection of voltage follower.
5. the automatic gain of analog signal as claimed in claim 1 is adjusted control circuit, it is characterized in that: this signal amplification circuit includes the first simulation multiplexer, the second simulation multiplexer, many multiplying powers resistance of several precision resistances compositions and the inverting amplifier of an operational amplifier.
6. the automatic gain of analog signal as claimed in claim 5 is adjusted control circuit, it is characterized in that: this first simulation multiplexer is one to have the analog switch of four groups of input channels, one group of delivery channel and two groups of control lines, input channel is connected with the output of buffer circuit, two groups of control lines are connected with gain control signal respectively, select one group of input channel to be connected with delivery channel from four groups of input channels according to gain control signal.
7. the automatic gain of analog signal as claimed in claim 5 is adjusted control circuit, it is characterized in that: a many multiplying powers resistance and a high-accuracy operational amplifier that this second simulation multiplexer and array precision resistance are formed constitute the inverting amplifier of adjusting gain automatically, the array input channel of this second simulation multiplexer is connected with array multiplying power resistance respectively, from the array input channel, select one group of input channel to be connected by gain control signal with delivery channel, meaning promptly selects one group of multiplying power and high-accuracy operational amplifier to form inverting amplifier according to gain control signal, with the appropriate amplification of signal amplitude to the acceptable opereating specification of adc.
8. the automatic gain of analog signal as claimed in claim 1 is adjusted control circuit, it is characterized in that: this front end signal processing unit includes bleeder circuit, clamping diode and buffer amplifier, wherein this bleeder circuit is connected with low resistance resistance by accurate high resistance measurement, it acts on the decay of input signal appropriateness, voltage division signal is clamped on positive half cycle by clamping diode then, buffer amplifier and system earth that last positive half cycle voltage division signal constitutes through a voltage follower.
9. the automatic gain of analog signal as claimed in claim 1 is adjusted control circuit, and it is characterized in that: this signal amplification gain control circuit includes one group of current rectifying and wave filtering circuit, comparator circuit and clamping diode circuit.
10. the automatic gain of analog signal as claimed in claim 9 is adjusted control circuit, it is characterized in that: this current rectifying and wave filtering circuit includes the filter circuit that a rectifier diode and resistance, electric capacity constitute, and becomes a direct current signal in order to the positive half cycle voltage division signal rectifying and wave-filtering that the gain controlling front-end processing circuit is produced.
11. the automatic gain of analog signal as claimed in claim 9 is adjusted control circuit, it is characterized in that: this comparator circuit includes a high level comparator and a low-level comparator, according to a high level reference voltage level and a low level reference voltage level, rectifying and wave-filtering direct current signal to input compares, and produces one group of gain control signal according to this.
12. the automatic gain of analog signal as claimed in claim 9 is adjusted control circuit, it is characterized in that: this clamping diode circuit includes two clamping diodes, lay respectively at the output of high and low level comparator, it acts on the output level of guaranteeing comparator and is clamped between the power supply V+ and ground of comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01261062 CN2492976Y (en) | 2001-09-07 | 2001-09-07 | Automatic gain control circuit for analogue signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01261062 CN2492976Y (en) | 2001-09-07 | 2001-09-07 | Automatic gain control circuit for analogue signal |
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|---|---|
| CN2492976Y true CN2492976Y (en) | 2002-05-22 |
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|---|---|---|---|
| CN 01261062 Expired - Lifetime CN2492976Y (en) | 2001-09-07 | 2001-09-07 | Automatic gain control circuit for analogue signal |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7391962B2 (en) | 2004-03-09 | 2008-06-24 | Samsung Electronics Co., Ltd. | Optical recording/reproducing apparatus having a function of separating luminance and color components |
| CN100581052C (en) * | 2004-08-13 | 2010-01-13 | 深圳赛意法微电子有限公司 | Automatic gain control system with self-adaptive climb and decay time |
| CN101222229B (en) * | 2007-01-12 | 2010-09-15 | 义隆电子股份有限公司 | Signal conversion device embedded with self test |
| CN102466756A (en) * | 2010-11-03 | 2012-05-23 | 北京普源精电科技有限公司 | Zero error elimination method of differential measurement circuit and differential measurement circuit |
| CN103575434A (en) * | 2012-07-30 | 2014-02-12 | 环球水泥股份有限公司 | Pressure detection circuit |
| CN106656086A (en) * | 2016-12-20 | 2017-05-10 | 北京中电华大电子设计有限责任公司 | Automatic gain amplifier circuit |
| CN107038013A (en) * | 2017-04-28 | 2017-08-11 | 广东欧珀移动通信有限公司 | Signal processing apparatus, mobile terminal and audio-frequence player device |
| CN112486065A (en) * | 2020-11-27 | 2021-03-12 | 上海商米科技集团股份有限公司 | Alternating current signal sampling method and device and handheld code scanning printer |
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2001
- 2001-09-07 CN CN 01261062 patent/CN2492976Y/en not_active Expired - Lifetime
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7391962B2 (en) | 2004-03-09 | 2008-06-24 | Samsung Electronics Co., Ltd. | Optical recording/reproducing apparatus having a function of separating luminance and color components |
| CN100581052C (en) * | 2004-08-13 | 2010-01-13 | 深圳赛意法微电子有限公司 | Automatic gain control system with self-adaptive climb and decay time |
| CN101222229B (en) * | 2007-01-12 | 2010-09-15 | 义隆电子股份有限公司 | Signal conversion device embedded with self test |
| CN102466756A (en) * | 2010-11-03 | 2012-05-23 | 北京普源精电科技有限公司 | Zero error elimination method of differential measurement circuit and differential measurement circuit |
| CN102466756B (en) * | 2010-11-03 | 2016-01-20 | 北京普源精电科技有限公司 | A kind of zero-error removing method of difference measurement circuit and difference measurement circuit |
| CN103575434A (en) * | 2012-07-30 | 2014-02-12 | 环球水泥股份有限公司 | Pressure detection circuit |
| CN103575434B (en) * | 2012-07-30 | 2016-06-08 | 环球水泥股份有限公司 | Pressure detection circuit |
| CN106656086A (en) * | 2016-12-20 | 2017-05-10 | 北京中电华大电子设计有限责任公司 | Automatic gain amplifier circuit |
| CN106656086B (en) * | 2016-12-20 | 2019-05-03 | 北京中电华大电子设计有限责任公司 | A kind of automatic gain amplifier circuit |
| CN107038013A (en) * | 2017-04-28 | 2017-08-11 | 广东欧珀移动通信有限公司 | Signal processing apparatus, mobile terminal and audio-frequence player device |
| CN107038013B (en) * | 2017-04-28 | 2020-08-14 | Oppo广东移动通信有限公司 | Signal processing device, mobile terminal and audio playing equipment |
| CN112486065A (en) * | 2020-11-27 | 2021-03-12 | 上海商米科技集团股份有限公司 | Alternating current signal sampling method and device and handheld code scanning printer |
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