CN2366858Y - Multi-functional radio testing and reparing instrument - Google Patents

Abstract

The utility model relates to an additional converter of a memory type TV oscillograph, which forms a memory type oscillograph together with a TV. The instrument is composed of an A/D converting circuit, a digital storage circuit, a video signal forming circuit, a TV signal forming circuit, etc. The signals to be tested are converted into digital signals via the A/D converting circuit to control the video signal forming circuit to form video signals containing the waveform patterns of the signals to be tested; the video signals are sent to the TV signal forming circuit to form TV signals; consequently, the waveforms of the signals to be tested can be observed through the TV. The instrument has the advantages of low cost and convenient carrying.

Description

The multifunctional radio examining-repairing instrument

Affiliated field: the present invention is that a kind of general television set that utilizes is made display, observes various time-domain signals and device frequency characteristic, can produce the instrument of various television measuring signals.

Background technology: oscillograph, sweep generator, the television signal generator that electric appliances service is commonly used all is individual independently instrument, and relatively heavier, instruments such as some oscillography tables though stature is little, cost an arm and a leg.

Goal of the invention: be mainly the electric appliances service personnel and design, constitute the memory-type TV oscilloscope additional inverter of memory-scope together with televisor, utilize the televisor of workplace to make display, just can finish signal observation, the device frequency characteristic test.Simultaneously, can produce the signal that various test TVs are used.

Technical scheme: this equipment circuit part mainly is made of three parts: television signal generator circuit (hereinafter claiming A), memory-type TV oscilloscope additional inverter (hereinafter claiming B) and television sweeper additional inverter circuit (hereinafter claiming C) three parts constitute, and also have other circuit such as power circuit in addition.More than three part main circuits also can make up in twos, or constitute independently instrument separately, mix corresponding shell, just constituted instrument with difference in functionality.Above-mentioned each instrument, the each several part circuit of formation instrument, the circuit with identical function can merge.

Television signal generator can produce the signal such as radio frequency, intermediate frequency, audio frequency of various test used as television, the part signal in signal such as colour bar, gridiron pattern, point, gray scale ladder, electronics circle, horizontal bar, vertical bar or the above signal.Can adopt the circuit of common television signal generator, as required, chrominance subcarrier signal can be provided by special circuit.(for example the signal that produces with one several times chrominance subcarrier signal oscillators obtains behind frequency division, or by the quadruple chrominance subcarrier signal through the pulse divider, phase place be 90 ° of signals that frequency is Fsc.

Memory-type TV oscilloscope additional inverter, this instrument is by the A/D change-over circuit, the digital storage circuit, video-signal processing circuit and TV signal form formations such as circuit, principle of work is that signal-under-test is converted into digital signal through the A/D change-over circuit, the digital signal that is converted to is stored in the digital storage circuit, the Digital Signals video-signal processing circuit that contains signal-under-test information forms the vision signal that contains the signal-under-test waveform patterns, this vision signal send TV signal to form the electric forming TV signal, thereby utilizes televisor to observe the waveform of signal-under-test.Its segmentation is made up of following several partial circuits: row field synchronization, blanking signal generation circuit, A/D change-over circuit, kind circuit, digital storage circuit, input circuit, trigger circuit when taking a sample, read partial circuits such as clock circuit, signaling conversion circuit and control circuit and form.

The course of work of TV oscilloscope additional inverter is as follows: measured signal is through pre-process, and the amplitude appropriate signal of becoming is sent to the A/D change-over circuit, by sampling and quantification, gets a string data stream, and this data stream is write among the data storage RAM successively.These digital coding that are stored can be converted into the video or the radiofrequency signal that contain these traffic flow informations after treatment earlier again.Handle and exactly data stream is carried out " compression ", reduce data volume." compression " is that digital coding is divided into groups, and selects a maximal value from each group, selects the information that a minimum value is represented these group data.Because during with ten ripple devices observation waveform, the just amplitude that topographical view measures, what be concerned about is the peak-to-peak value of this local amplitude.This has just obtained the digital coding of one group of group, two data of each group are the maximal value and the minimum value of original that group, during demonstration, after blanking signal on the scene finishes, read one group of data and latch at each line blanking period, each data produces one and by line synchronizing signal control the proportional pulse signal of duration and size of data during line traversal takes place.Each organizes each data, produce a pulse-width signal, can merge into a pulse signal with gate circuit (TTL or other type), will be synchronously, blanking signal and this signal in proportion synchronizing signal amplitude be 1, blanking is 0.8, figure is that signal amplitude is that 0.1 to 0.8 (for bright desirable 0.1) is converted to vision signal (this paper vision signal refers to the picture signal in composite video signal or the composite video signal), perhaps is modulated into radiofrequency signal again.Above-mentioned pulse signal can convert digital signal to and be stored in the digital storage circuit, promptly under sampling clock control, the high or low digital storage circuit that deposits in of current potential during successively with each clock, each pulse signal produces group's digital signal, set of pulses signal produces one group of digital signal as shown in figure 16, successively each row shown in Figure 16 is read at each line period during demonstration.The resulting pattern of above scheme be erect and do not meet our custom, therefore data shown in Figure 16 will be called over to classify as, so this digital storage circuit to or utilize data to adjust circuit and adjust with two address generator circuits.Above-mentioned each group data are selected by original each group data, and the data after " compression " can deposit among the RAM, and signaling conversion circuit is sent in taking-up from RAM again, also the direct number of writing to change-over circuit.Televisor is staggered scanning, in order to make full use of televisor, shows information as much as possible, can be with " data after the compression are divided into odd even two by data set arrangement sequence number to be organized greatly, at odd field, neat array data is shown, and shows the even number set data at even field.To on display screen, observe stable image, be repeatedly with data presentation, as show 1 second (showing that number of times and time are proportional).In order to observe continuous waveform on TV, make the waveform will be near drawing, data after the above-mentioned compression further can be handled: two groups of continuous data are divided into main the group and attached group, (raw data is except that two groups of two, all to do once main the group and attached group successively, it is fixed that main group and attached group of order are appointed, but after determining, will fix in proper order for each main attached group).Two groups data are compared.The maximin of main group is respectively N1 and attached group of maximin of N2 is respectively N3 and N4, when N1≤N4, gets N2 and N4, when N3≤N2, gets N3 and N1, and other situation is got N1 and N2.Per like this two groups of data produce one group of new data, and these data are sent to the RAM storage or directly arrive signaling conversion circuit.Hereinafter, with only from one group of data, selecting maximum minimum value to be called compression method, 1. from two groups of data, select two data according to both sides relation, be called compression method, 2. in data handling procedure, compression method 1 can carry out several, and compression method 2 adopts during data compression the last time.These data operations, can obtain by gate circuit, also can be with H1.H2.H3.H4. as the address, (the pulse-width signal that H1.H2.H3.H4 control produces, it at a time is high level, or low level, therefore, can be used as the address of RAM) with " 0 " or " 1 " representative method 1 and method 2 also as of address by (PRO more than 32 * 1 or 16 * 2 or EPROM etc. obtain.

The data compression of B can be adopted several different methods.Method one: every group of data are sent into individual latch cicuit certainly, they and synchronizing signal or (other pulse signal), producing one is produced by synchronizing signal control, the pulse signal that pulse width is associated with the data, these signals are by the logical operation circuit computing, when a signal level and other signal electricity is inconsistent, export a kind of logic level, when all signal levels are consistent, export another kind of level.The front and back of this signal are along two extreme values having represented these group data respectively.Produce pulse-width signal associated with the data here, can use digital circuit, also available mimic channel.Use digital circuit, with easy to adjust, error is little, uses the analog pulse width modulation circuit, and is that simulating signal is sent to pulse-width modulation circuit again with data conversion earlier.A kind of special circumstances, whole when identical when these group data, the computing circuit computing is reaction not, this situation, produce a narrow pulse signal and the above-mentioned logical signal addition that time of origin is relevant with these data with at least one Data Control, two signals can pass through or the door addition.Method two: the data of each group are latched respectively, the corresponding positions of they each and a counter connects an XOR gate, its output connects many input ends and door, counter adds clock signal, when all XOR gate output high level, with door output high level, (trigger circuit reset at line blanking period in the control triggering electric circuit counter-rotating,) as method one, produce pulse-width signal, carry out computing, calculate logical signal on this logical signal forward position and edge, back, the control lock storage will be worked as the data latching of hour counter, maximal value and minimum value that these two data are exactly this group number.Method three is: adopt micro computer to compare.Micro computer is got a number earlier from these group data, another data and it are compared again, and selects big (or little) and compares with another data, and is maximum or minimum to selecting this group to the end.Only compare with micro computer, speed is slow greatly, can adopt micro computer and hardware to cooperate, and accelerates relatively speed.Micro computer cooperates peripheral hardware to compare, and microcomputerized control is with one group of data input digit circuit, and this circuit is by handling, automatically with maximal value and minimum value output.In method two and the method three, also can adopt and select a utmost point road from one group of data, again from another group, (these two groups of data have half to overlap) selects another opposite extreme value, and these two extreme values constitute one group of new data.

During signals such as observation waveform, signal flow is as follows, data after the A/D conversion can directly become TV signal (vision signal), also can be treated as TV signal again through overcompression, compression can be compressed secondary or more times, data after the A/D conversion also can be transformed into and are pattern signal, adjust circuit outputting video signal (also can pass through the one or many compression before the conversion) through the data order again.It in fact also is that a kind of digital signal is converted into picture signal that data are converted to TV signal.For the pick up speed data processing is finished by the Single-chip Controlling peripheral hardware, wherein transmit with the DMAC control data, by operations such as data compression change-over circuit control data compressing and converting, main circuit is as shown in Figure 9.Fig. 9 cooperates circuit such as Fig. 3 Fig. 2-4 grade, and the processing that can carry out has: one. and with per four data " compression " is two data.Two: with per four data " compression " converting digital pattern signal more earlier.Three: data are converted to TV signal after " compression " again.Information " compression " can be controlled DMAC to circuit input data shown in Figure 9 by CPU, simultaneously, utilizes another DMAC to lead to and deposits output data in RAM.Compressing later data can compress once more.Compression or do not have compressed data can send into circuit shown in Figure 9 is converted into the digital pattern signal or computing circuit output and composite synchronizing signal addition is produced picture signal.

Data processing will be carried out later on finishing data acquisition.Above-mentioned processing is when " one+two ", utilize a DMAC passage that data are input to Fig. 9 circuit from RAM, set data transmission start point then through removing DMAC, quantity, pattern control shielding word command word etc., to another DMAC also initialization, CPU sends startup command, (before sending startup command after DMAC programming is finished, all are participated in the DMAC passage initialization of this process, down together).Carry out data processing.More than each DMAC be operated in the byte transfer mode, do not allow auto-initiation.If will compress once more, CPU will close Fig. 9 circuit earlier, to above DMAC programming, restarts compressor circuit again, for increasing quantity of information, can show different contents continuous two when being operated in " one+three " state.The employing scheme is that (every row shows the point of four data, branch major-minor group) calculates each field energy data presented number, (sending the decision of K pulse number by clock signal generation circuit) is at odd field, data are input to Fig. 9 circuit by DMAC, at even field, the 3rd of last one data begun to be input to Fig. 9 circuit.The total data that odd field will show can be placed on RAM H to the M unit, data presented to be placed on each unit that M+1 begins even field, during transmission, DMAC is operated in the byte transfer mode, allow auto-initiation, eop signal is provided after one or two field scans finish by synchronizing circuit.At this moment the odd field data presented will be calculated accurately, and these data can be raw data, also can be the data after the compression.

Another method is to utilize two DMAC passages to control respectively to transmit two parts data.The data of second DMAC channel transfer begin for the 3rd data of first channel transfer.(Fig. 9 is handled four data simultaneously).At this moment, circuit shown in Figure 9 meets DREQO.The place will be modified as follows: introduce the parity field signal, and have a not gate anti-phase to it.The control signal that former phase and anti-phase parity field signal send with CO start signal output circuit respectively, by with the DREQ control end that send two DMAC passages behind the door again, provide eop signal by synchronizing circuit, allow auto-initiation.

Row field synchronization, blanking signal generation circuit produce consistent with standard television signal or similarly capable field synchronization, blanking signal, as signaling conversion circuit, when televisor is worked synchronizing signal and read the time gate of data among the RAM.

Read clock signal, it is the clock signal when data are read among the RAM.

Input circuit, it is decayed measured signal and preposition amplification, makes the amplitude of the signal that is added to A/D converter suitable.Trigger circuit generation trigger pip, its produces and obtains digital coding or control the address of remembering when triggering after triggering makes RAM begin to store the A/D conversion.

The sampling clock circuit produces sampling clock signal.It can produce the very wide clock signal of frequency model, and its frequency decision is observed the frequency of signal.Sampling clock signal has three kinds: the one, and the self-sustained oscillation signal; The 2nd, the signal of using when surveying TV signal relevant with Fsc; The 3rd, the signal of extraneous input.Self-excited oscillator can produce tens KHz to tens megahertzes even the clock signal of wide frequency ranges more.Make clock signal with the signal relevant with Fsc.(as Fsc, 2Fsc, 4Fsc, 8Fsc ...) this signal can be obtained Fs or be adopted the Fs recovery system circuit of using in the colour TV by television signal generator, multiple Fsc is treated again (as the phase shift frequency multiplication etc. from the TV signal of importing this instrument, phase shift can adopt capacitance-resistance to move or the resistance inductance constitutes moves network, adopts the method for control capacittance or inductance to change the angle of phase shift.) outer signals can be various signals, they will be handled through clamper.More than three kinds of clock signals, wherein a kind of through selector switch, become the clock signal compatible through amplifying again with A/D converter, address ram counter etc.It one the tunnel is added to the A/D change-over circuit, and one the tunnel is added to the address ram circuit.

Television sweeper additional inverter: constitute by row field synchronization blanking signal generation circuit, saw-tooth wave generating circuit, voltage controlled oscillator, demodulation probe, low-frequency amplifier, marker oscillator signaling conversion circuit etc.Field blanking (or synchronizing signal) control produces the field frequency triangular wave, and this triangular wave is by control circuit, and midpoint potential and peak-to-peak value can be regulated respectively and control voltage controlled oscillator generation swept-frequency signal.This swept-frequency signal is removed equipment under test, and after tested being equipped with, its amplitude will change with the amplitude versus frequency characte of circuit-under-test, obtains unidirectional low frequency signal through detection, through amplifying, removes to control pulse-width modulation circuit and produces pulse-width signal.Pulse-width signal is produced by line synchronizing signal control, pulse width is by above-mentioned signal controlling, with pulse-width signal and the addition of row field sync signal that obtains, row field sync signal amplitude is 1, the pulse-width signal amplitude for bright, can be located at 0.1 below 0.8, obtain vision signal or be modulated into radiofrequency signal again, just can utilize televisor to observe the frequency characteristic of equipment.

When B and C combine, can be with by being sent to the input end of B behind the signal demodulator behind the equipment under test and after the frequency standard signal addition, as the test signal of B, and the frequency characteristic by B and television display equipment.During B and C combination, the sawtooth of C also can change the sawtooth wave of frequency adjustable into, and the scan period can be from centisecond to tens second even wideer.

The synchronous blanking signal of television sweeper additional inverter requires lower, can need only synchronizing signal or make synchronizing signal with blanking signal, pulse width can change in a big way, but in order to improve resolving power as far as possible, requires to contain the odd number line period in two field duration.This signal can produce with row field sync signal generation circuit in the common various television signal generators.Make synchronizing signal with blanking signal, saw-tooth wave generating circuit can be used Miller integrator, and the bootstrap type sawtooth wave forms circuit.Generations such as crossing current source sawtooth-wave circuit.Frequency is that field frequency requires the length of trying one's best sweep time, the D.K system, and each 312.5 row, flyback is 25 row, it is approaching with field trace to try one's best sweep time.This field frequency triangular wave will pass through potentiometer, and the amplitude of accommodation by capacitance output, is regulated its midpoint potential by potentiometer.Its maximum peak peak value is wanted enough (as about 30V).Voltage controlled oscillator utilizes the adjustable field frequency triangular wave of amplitude, produces swept-frequency signal.Voltage controlled oscillator can adopt the voltage-controlled device that shakes of varactor.In order to obtain the very wide swept-frequency signal of frequency range.The mutually oscillator of overlap joint of a plurality of frequency ranges can be set, and the lowest segment swept-frequency signal is by obtaining than higher swept-frequency signal and the signal difference frequency of deciding frequency, and the signal of high band can be obtained by the intermediate bands signal frequency multiplication.The output of voltage controlled oscillator signal is wanted steadily can utilize fixed amplitude circuit to handle.Swept-frequency signal is exported by attenuator at last, swept-frequency signal is equipped with after the demodulation probe detection by tested, obtain unidirectional low frequency signal, this signal and frequency standard signal linear, additive can carry out that the number of writing to change-over circuit and row field sync signal form vision signal after the addition with an in-phase amplifier.Earlier produce pulse-width signal together, with pulse-width signal and the addition of row field sync signal, produce vision signal again by this signal and line synchronizing signal.In order to obtain beautiful waveform, edge behind the pulse-width signal can be carried out differential (or utilizing the back) with this differentiated pulse and the normal synchronizing signal addition of row along control steady-state circuit generation pulse signal.Pulse place current potential is opposite with the synchronizing signal current potential, and other parts amplitude and blanking signal amplitude are approaching, thus the pattern that obtains becoming clear.

Control circuit control each several part circuit working.It can be made of various gate circuits etc. also can be controlled by microcomputer, micro computer, and as 8031,8051,80 series etc.More than each circuit can adopt the related circuit of digital storage oscillograph oscillography table.

More than three kinds of instruments can use separately, also can combination in any.The televisor of making display is not the part of this instrument.When they made up mutually, row field synchronization, blanking signal generation circuit can overlap with one, and when A and B combined, the sampling clock of B can be obtained by the colour burst signal of A.This signal can pass through phase-shift circuit, frequency multiplier circuit (adopt quadruple or higher frequency, can better observe TV signal), kind signal when being re-used as sampling after the processing, also can be by several times (as 2 times, 4 times, 8 times of these signals are produced by several times of subcarrier crystal oscillating circuits).Chrominance subcarrier signal one tunnel behind frequency division as the chrominance subcarrier signal of A, one tunnel signal of kind during as the sampling of B, (also can earlier through phase-shift circuit phase shift or frequency multiplier circuit frequency multiplication).As producing the crystal oscillator signal by 4 times of Fsc crystal, the one tunnel makes sampling clock, and four frequency divisions are carried out on another road, make the reference subcarrier of signal generator.The circuit that crystal oscillating circuit can adopt this paper to introduce.When B and C combine, the circuit that can the signal that will react tested device frequency characteristic that the C detecting head is later be converted into video or radiofrequency signal need not, and the signal of the consersion unit frequency characteristic that obtains after the detecting head detection is added to the input end of B, the triangular wave of C can change other frequency into by field frequency in this case, sweep frequency can be regulated, and can better observe the frequency characteristic of equipment.B also can be directly and display screen combine.When both made up, display screen can adopt small-sized kinescope or oscillatron, or liquid crystal display, adopt oscillatron and general memory-scope similar, when adopting kinescope, B and a video monitor can be combined, the vision signal that B is exported directly is added to video monitor.When adopting liquid crystal display, can adopt the combination of liquid crystal display video monitor or signal demonstration reservoir and the liquid crystal mould of B are presented the rafter cat as modules such as 64 * 128 dot matrix or 128 * 180 dot matrix), will data presented import Liquid Crystal Module, in this case, just show or export video or the radiofrequency signal that contains measured signal, utilize televisor to show the measured signal waveform with the signal of digital oscilloscope or its collection of oscillography table or by oscillatron or liquid crystal display.After the combination of B and display screen, still can be again and A and C combination in any, above-mentioned various instruments all will be mixed corresponding shell.The principle of shell is that to make every effort to the instrument volume little, and the limit is in carrying.

The beneficial effect of innovation and creation: the present invention utilizes the televisor in a kind of instrument cooperating place, can finish the instrument function of multiple instrument.

Description of drawings: Fig. 1 multifunctional radio examining-repairing instrument block scheme.Fig. 2 multifunctional radio examining-repairing instrument panel figure.Fig. 3: various clock signal generation circuit diagrams, Fig. 4 modulation circuit, Fig. 5 field frequency triangle wave generating circuit, Fig. 6 pulse signal and composite synchronizing signal with become video circuit.Fig. 7 analog pulse width modulation circuit.Fig. 8 swept-frequency signal generation circuit, Figure 22,23 24 outputs contain the circuit block diagram of a plurality of channel signals.Figure 25 diode limiting circuit, Figure 26 multiple signals mixting circuit, Figure 27 input contains the circuit of a plurality of channel signals.Fig. 9 data compression change-over circuit, Figure 10 digital pulse width modulation circuit, Figure 11 computing circuit, a kind of circuit diagram of Figure 12 and Figure 21 memory-type TV oscilloscope TV additional inverter.Figure 13 start-up circuit, Figure 14 two circuit-switched data are selected circuit, the start-up circuit of Figure 15 Fig. 9.The relation of Figure 16 data and pattern.Figure 17 pulse is by the number control circuit, and Figure 18 data bit is adjusted circuit, and Figure 19 data are adjusted circuit 1 in proper order, and Figure 20 data are adjusted circuit 2 in proper order.Figure 29 main program flow chart.Figure 28 subroutine flow chart.

The embodiment explanation: Fig. 1 is the circuit block diagram of multifunctional radio examining-repairing instrument.This instrument is made of three parts.Fig. 3 and circuit shown in Figure 6 constitute TV signal generation circuit, the synchronous blanking signal that vision signal and Fig. 3 circuit produce is added to Fig. 6 circuit, two signals and become TV signal, the data compression change-over circuit of Fig. 9 and Figure 20 data are adjusted formation video (image) waveshaping circuits such as circuit, signal-under-test is after the A/D conversion, deposit the digital storage circuit in, these data are imported Fig. 9 circuit again and are carried out the compressing and converting processing, the pulse-width signal that obtains directly send the TV signal formation data that contain the measured signal waveform patterns that circuit maybe will obtain to send the circuit shown in Fig. 9 or 20 to adjust as vision signal, thereby changes erect display pattern on the screen as the level demonstration into.Pulse-width modulation circuit in Fig. 9 circuit and computing circuit are respectively as figure 0 and shown in Figure 11, Figure 17 is Fig. 9 clock number control circuit, whether some functional circuits need start-up circuit control to work, and Fig. 9 will use more special start-up circuit, and this circuit is taken on by Figure 15 circuit.The field sync signal control chart 5 that Fig. 3 produces produces the field frequency triangular wave, this signal is added to Fig. 8 swept-frequency signal generation circuit and produces swept-frequency signal, swept-frequency signal by testing apparatus obtains unidirectional low frequency signal through detection, this signal is added to the circuit of pulsewidth accent shown in Figure 7, generation is by the width of line synchronizing signal control generation and the signal of the proportional pulsewidth accent of this signal amplitude, this signal is added to Fig. 6 circuit as picture signal, form TV signal, also the signal that detection can be obtained is added to the input end of memory-type TV oscilloscope, tests as its test signal.

Figure 10 is the digital pulse width modulation circuit.Data are latched, and everybody is added to the input end of an XOR gate respectively, counter, and its output and latch correspondence one by one connect another input end of XOR gate.Count after the counter O reset, when counting and the number that is latched two radix-minus-one complement each other, promptly everybody is opposite with former number, and it is 1 that former number is 0, and it is 0 that former number is 1, and each XOR gate is all exported high level.Through eight Sheffer stroke gates through anti-phase again by or door be added to counter, the counter lowest order uprises level, simultaneously or door be lockable.Under the horizontal blanking impulse effect, next process is carried out in each counter O reset again.Replenish: will arrive most significant digit at each period counter counting otherwise, then can not get relevant pulse width modulation signals, can improve clock frequency or minimizing figure place, also everybody of two radix-minus-one complement of data can be added to corresponding XOR gate if data are little.One or gate action are each data of control among the figure, only produce a width-modulation pulse.

Fig. 3 is synchronizing signal and various pulse signal generation circuit, so the data of low 7 generations of 8 digit counters of 4MHZ crystal oscillator signal are added on 2716.Second 2716 in the 1250th (for PAL D/K system) address, contain reset signal.By changing crystal oscillator frequency, change number of counter bits, also produce various other clock signals.Circuit can produce various signals shown in Fig. 2-1, as composite sync.Blanking signal, field blanking signal, above required three pulses of even field scan period first line blanking period, two pulse signals of other horizontal blanking etc.The a certain bit data of first 2716 every continuous 8 address locations changes once, and signaling conversion circuit is linked in this output, is converted into TV signal, and TV can be received the identical perpendicular thick stick of about 14 black and white.Equally, second every a certain bit data variation in certain unit once, can obtain the whippletree signal at last from the 1st and 626, and the one or two output merges by XOR gate, can obtain the grid signal.Every 2716 in this circuit has eight tunnel outputs, when the more output signal of needs, and can be with several ROM (read-only memory) parallel connections.Should or connect power supply for manual ground connection to a few positions of address, the address that the ROM in back provides for last ROM is many more, first ROM also can export more information, need provide a K pulse signal that takes place at place, horizontal blanking forward position at Fig. 9, this pulse signal can be by the unit storage of this circuit, by a certain I/O mouth output.The various fixing clock signals that produce in time all can be produced by this circuit among the application, and other crystal oscillating circuit, schematic circuit can adopt crystal oscillating circuit in this figure frame of broken lines among the application, and each component specification changes with crystal frequency and suitably adjusts.Among the figure, the clock of 74LS393 is respectively crystal oscillator signal behind crystal oscillator signal and 16 frequency divisions, and counter produces data and is added to ROM, and ROM output is added to latch, by latch data is exported.ROM has the part address pin to select to connect power supply or ground connection by switch in addition, and bundle all draws among the figure.

This circuit can send those synchronizing signals (identical or similar substantially) of the television synchronizing signal generator generator of " electronics newspaper " bound volume last 119 pages of introductions in 96 years, and the scrambler that connects 127 pages of introductions more just can produce colour bar signal.When connecing this coding circuit, before W1, W2, W3, connect a proper resistor, be input to the signal amplitude of encoding block with adjusting, composite synchronizing signal, not enough as fruit bat, can add the one-level interface circuit, reaching needs amplitude.

Programming to ROM: with first be example, this piece mainly produces and row signal relevant various signals.Producing the capable step signal that disappears is example.The address is provided by 7 binary counters, horizontal blanking signal is set at 12 microseconds here, line period is 64 microseconds, the address is 7, like this address is made as high level from 0-23 (transforming the position decimal system) with certain byte (A), work as counter like this and connect the 2MHz clock, this byte can output pulse width be 12 microseconds just, frequency is the horizontal blanking signal of 15625Hz, be decided to be low level as if 0～2 and 12～127 unit bytes equally with another byte, 3～11 are decided to be high level, and can obtain second is the line synchronizing signal of 4.5 microseconds towards width.The address counter clock of second ROM is 2 times of line frequencies, count down to 1250, and the clear order of counter resets.Allow this ROM in the address from 0～49,625～674 certain byte (B) output high level, other address output low level is with this byte output as the address of first ROM, when above-mentioned A byte is low when this position, by above-mentioned programming, when B byte when being high, input be height entirely, like this, the A byte just can be exported composite blanking signal, in like manner, can obtain composite synchronizing signal.Want the field blanking signal separately, B byte signal can be made the field blanking signal, that is to say, sum up first ROM, need the different line period of how many kinds of, second ROM just provides corresponding difference address, the waveform that will export during with this is again according to the level height, as the coding of this unit.In order to increase more output, can take measures: change into ROM more high-order or several parallel connections, set up the non-clock control in several roads in the address of ROM, as by toggle switch or CPU control, this method can be used to select output class.

Fig. 9 circuit, after receiving the control letter number of entering readiness, CD4022 (1) is through zero clearing, here, claim that with quenching pulse (quenching pulse and horizontal blanking signal take place simultaneously in the K pulse, the time ratio synchronizing signal is short a lot, is produced by Fig. 3 circuit, and scan period only on the scene produces when needing display waveform), CO carry end output high level, with control signal through and door remove to trigger the DREQC of DMAC, action is sent in the DMAC response, with a certain cell data output of RAM, CD4022 (1) utilizes the WRITE (also available other signal) of DMAC to make clock signal after anti-phase, CD4022 counting 1, and Q1 exports high level.Anti-phase back of WRITE and Q1 through and door, finish at WRITE, should and the door output signal descend, with data latching, equally, respective latch latchs the two the 3 4th data at a certain road of negative edge latch cicuit.Receive CD4022 carry terminal potential step-down level after four pulses, DMAC stops response.During the horizontal blanking signal, data transmission will be finished.Each Data Control of data via pulse width modulation produces a pulse signal during the line scanning, again through computing circuit output operation result.This result can convert video or radiofrequency signal to by the number of writing to change-over circuit.This signal is added to the shift register input end, and under the clock signal effect, this signal transmits to the right.After CD4022 (2) count down to 8 clocks of shift register input, QO became high level, this signal and time clock through and door, produces one with the 8th the consistent pulse of clock signal, shift register exported lock.Shift register seals in and goes out to get final product.The 8th pulse makes counter (2) counting, lowest order output high level, and the DMAC response deposits these data among the RAM in, and the WRITE that utilizes DMAC simultaneously, then goes on this counter O reset through anti-phase or other signal.The data that four data controls are produced deposit among the RAM, carry out frequency division if will be added to the clock of CD4022 (2) here, then obtain the pattern signal data volume, also reduce thereupon, and (here be that " " with digital signal transition is pattern signal in compression " " expansion.In order to control, can count the pulse number that is added on the CD4022 (2), here, the Q0 output terminal of CD4022 (2) is passed through the number control circuit to connecing a pulse between the counter 2, like this, just finish after the data of the number of in depositing RAM in, setting and suspend dma operation after this takes turns when changing, in this case, clock frequency can bear results by more random computing circuit, also can carry out following operation: counter zero clearing under the horizontal blanking signal effect, count then, counter data is added to latch cicuit, and inciting somebody to action at that time respectively at the signal rising and falling edges, counter data latchs.In next round, from RAM after four data of output, CD4022 (3) zero clearing, Q0 exports high level, and the DMAC response utilizes anti-phase back WRITE signal to make CD4022 (3) counting, with first, second latch triple gate opened, and its latch data is deposited among the RAM respectively.After DMAC responded for the second time, CD4022 (3) Q2 exported high level, and CD4022 stops counting, and these actions will be finished at line blanking period, can widen the horizontal blanking width in case of necessity, widen whole capable field time.Horizontal blanking finishes, and the latch triple gate is closed.Then continue the conversion of data.Function of frequency divider is, is 8 if do not carry out the frequency division latched data, carries out two divided-frequency.Most significant digit is zero in 8, four frequency divisions, and the highest two is zero in 8, frequency divider is made of clock upper edge flip-flop number.Delay circuit effect among the figure: pulse-width modulation circuit and computing circuit have time-delay through multistage gate circuit, make up a deficiency by this place's delay circuit.The available gate circuit series connection of herein delaying time is delayed time or symmetrical spiral delay line.Computing circuit is exported if any spike, available low pass filter filters out.TTL circuit and COMS circuit are arranged among the figure, and suitable interface circuit between them, TTL drive CO MS circuit, connect and draw resistance, or the COMS circuit is changed to the TTL circuit.Be changed to 74L S393 and 74LS138 or 74LS42 i.e. binary counter and one three-eight or multidigit code translator etc. more as CD4022, draw signal by anti-phase as CO with the 3rd of counter (as 74L5393).The control circuit of Fig. 9 will be with control circuit shown in 15.This control circuit work is as follows: start-up circuit send enabling signal effectively after, it is invalid that the counter reset end becomes, counter enters the strong attitude of counting, when horizontal blanking signal arrival hour counter lowest order output high level, this is output as the control signal of Fig. 9, simultaneously, this counter clock input end keeps high level always.When start-up circuit imitate number invalid after, through anti-phase, this signal becomes the reset signal of counter, counter output is low flat, circuit shown in Figure 9 quits work.Fig. 9 circuit, when not being operated in when becoming pulse signal output to synthesize TV signal again the data-switching, its " horizontal blanking " signal can not be " mixed blanking " signal.

Circuit shown in Figure 9 only is converted into TV signal with the computing signal, can to use less than the DMAC programming.In this case, the clock used of digital pulse width modulation circuit can adopt 5MHz.This signal can return frequency division by 20MHz and obtain, simultaneously, 20MHz carry out five or very frequently after, or other frequency division of the frequency can replace clock signal among Fig. 3.Under other situation, to consider that with regard to not needing to consider the signal after the computing is converted into TV signal DMAC transmits, get caught up in DMAC and transmit.Guarantee reliable transmission.At this moment except that the DMAC clock, each signal clock frequency will reduce, and each signal pulse width will increase.As at this moment a synchronous blanking signal partial width being increased by four times, just Fig. 3 clock is reduced to original 1/4th, the pulse-width modulation circuit isochronon, become 5/3rds MH2 (20MH2 is carried out 12 frequency divisions), carry out this change, have only two clock frequencies to change, can establish a control circuit, control two two circuit-switched data and select circuit to select a certain clock respectively sometime.At this moment " " " blanking synchronously " signal with original making a world of difference,, still be called two groups of continuous numbers under " synchronously " or " various situations of blanking signal here, can be respectively h, h+1, h+2; h+3 and h+2, h+3, h+4, h+5, or h, h+1; h+2, h+3 and h+4, h+5, h+6, h+7.Shift register can be incorporated into/seal in two four---and go out/go here and there out to move to deposit series connection (as 74LS194,74LS195 etc.).

The order of the data just that Figure 19 adjusted, the data that just will form a width of cloth pattern, input is by original row order, be that delegation's one line output changes into the row order, promptly, export the data of secondary series more earlier with the data output of each row first row .... when each number has multidigit, each can be listed as first output of each data, export its second again ... and then export the every of second each number .... (in the drawings, the endways row of data of each row, the data of each row are arranged sidewards.) will adjust, also just data are imported RAM successively, and then use the address that another address circuit provides instead, the difference of this two-way address is: the address is the row again of going ahead of the rest in proper order with each during input, before column address comes row address during output, be row then, front and back orders is just before the sequence of addresses low level after the high position.To shake be example to show at 32 * 32, if be made of 8 figure places, 128 data will be arranged then.As Figure 16,4 of this each row of 128 data, totally 32 be listed as, these 128 data exist among the RAM with in 0 128 unit that begin, the 1.2.3.4.5.6.7 pin of address corresponding address ram from the low level to a high position, (being each pin of address to be sorted rather than the pin of RAM here) when output, everybody of the address of RAM connects look 6.7.1.2.3.4.5 position, new address successively, and so just can be adjusted into original row order former antecedent is ordering in proper order in proper order.When everybody output that requires successively data, can be with increasing several and remove many data selection circuits behind the row address before the column address of address, successively everybody of data selected, as totally 10 of the addresses that provided by counter, each pin correspondence of address ram connects this 9.10.1.2.3.4.5 position of 10.Three of 6.7.8 go eight circuit-switched data to select circuit in 10, like this when counter when 0 count down to 0, each dot matrix of the pattern of Figure 16 is calling over a time according to each capable delegation among the figure successively.If TV is in certain row beginning, every row provides 32 pulses, and 32 row are provided altogether, and pattern then shown in Figure 16 just shows on TV.If want two occasions to become a width of cloth pattern, will provide the pulse line number to reduce by half, during output the most significant digit of column address is connect 1 pin of the address of RAM, other everybody order of column address moves one, just the highest as the parity field signal with the address.Shown in Figure 19 or 16, core is RAM, has three tunnel addresses to be added to RAM by tri-state buffer circuit, and other has three road tri-state buffer circuits that three-state control, sheet choosing, read-write control signal are added to RAM, with No. three control circuits, respectively three tunnel addresses and relevant controlling signal are added to RAM.Here, by the address that counter provides, this road control signal can connect high or low level, makes RAM be in read states, and triple gate is opened.In addition two-way address and control signal are provided by DMAC that (available a slice multi-channel DMA C, to RAM input data, input finishes earlier, again the DMAC programming is added to RAM with address and control signal by the ternary buffering in another road.Arbitrary time of three tunnel control signals has only one the tunnel effective at most.Here, DMAC can be operated in the block transfer state, does not allow auto-initiation.Earlier deposit data in RAM, then, can again the data after the adjustment order be deposited among the main RAM or everybody of each number read successively and be converted into TV signal.Control of the three-state of RAM or sheet choosing connect and draw resistance among Figure 20, make this RAM each data-interface when not working be in high-impedance state.The address explanation: use normal address during input, address counter has been counted row earlier to column count during output, row address adds one, and when data were eight digit number, the data of counting each row repeated eight times, each with wherein output, count eight times after, row address adds one.

In the time need showing more waveform with TV, as 256 * 256, with 256 * 32 8 bit data input RAM, address ram expands 13 to, go 256 (or 128 row, parity field shows different content respectively) provide every row 256 time clock.A window can be stayed in the place of display image, use circuit shown in Figure 3, after a certain road (D) output and composite synchronizing signal merge, it on the display screen window, (window has 256 row, it is enough that width is wanted, otherwise reaching at 256, the pattern level that shows not show or etc. at 128 at 64), with the 5MHz clock signal by pulse number control circuit (exporting zero clearing) map interlinking 20 circuit with D, be set in 256 pulses of each output, zero clearing between non-window phase has shown that at two the back to the counter O reset of address is provided, so just can obtain the pattern of one 256 * 256 dot matrix.

Figure 20 is that another kind of data are adjusted circuit, and this circuit is a core with RAM, and other has six road tri-state buffer circuits, and the operational order that address and this address will be carried out is added to RAM respectively.To show that 32 * 32 dot matrix are example, when the input data, each pin of RAM connects the 1.2.3.4.5.6.7 position of the address that DMAC provides successively, when output, connect the 6.7.1.2.3.4.5 position of the address that DMAC provides or connect the 9.10.1.2.3.4.5 position of counter address, counter 6.7.8 goes eight circuit-switched data to select circuit, the corresponding start-up circuit of this three route sends control signal and selects, simultaneously, the various instructions of this control signal during with this address are added to RAM. (when counter provides the address by the three-state buffering, the high or low level of RAM relevant controlling termination is in it and reads, the triple gate open mode).

More than each program can be to finish a program one to stop, CPU receives order and carries out next program again, also can get up continuously.General flow chart is shown in 29.After the startup, finished data acquisition, just changed data compression over to or be converted to pattern signal (numeral and simulation).Compression can be carried out repeatedly as required, the simulating signal after the conversion can be directly and composite synchronizing signal synthesize vision signal.At this moment, data distributing program is operated in loop program, has only this program (this program is last compression or converse routine) circulation to get final product.The digital pattern signal that obtains after the conversion can send Figure 18 processing of circuit to send Figure 19 or 20 processing of circuit again, and last and composite synchronizing signal addition becomes vision signal, also can directly send main RAM to preserve again after Figure 19 or 20 handles without Figure 18 circuit.Each step operation, the main effect of CPU are that the DMAC that each operating process is used is compiled the city, and each subroutine is as follows: CPU sends earlier and makes the out-of-work order of all functions circuit, follows relevant DMAC and programmes, and sends the order that starts relevant functional circuit again.Be transmitted in the measure of taking here and have in order to allow DMAC under the byte transfer mode, accelerate data, the HRQ that will be possible to use control signal that EOP resets and DMAC by or door remove CPU after merging, one monostable circuit is set delays time, CPU is removed in the HRQ signal of monostable output and DMAC or door merging, can repeatedly trigger monostable as required.Monostable triggering is used as an I/O port to monostable circuit by CPU and is treated, and makes trigger pip with its strobe pulse, and triggering times is by the programming decision.Utilize monostable circuit time-delay, can be used in data conversion is on the program of TV signal, utilizes time-delay length, inferiorly decides the pattern displaying time, like this, has only the DMAC end of transmission, and CPU could send Next Command again.Be to reduce maloperation, add several non-operation instructions after can CPU sending startup command.Or carry out of short duration time-delay with other instruction.

In main program flow chart, also can stop in middle therein somewhere, perhaps need not to middle certain subroutine.Data after the data compression that collects, the brilliant display module of the also direct liquor charging of intermediate data such as data that converts pattern to demonstrates waveform.

Figure 11 is a start-up circuit, and the start-up circuit effect is to receive startup or the shutdown command that CPU sends, and makes its control signal of sending enabling signal or closing, and the relevant circuit that is subjected to its control is begun or quits work.In Figure 11, address decoder has three tunnel outputs (three addresses) wherein to cooperate other order to make rolling counters forward in the address, and lowest order output high level just sends enabling signal, this signal control signal is effective, and this road only cooperates information concerning order that it is resetted with another address.This road difference of another road as the eop signal that DMAC sends, resets it for receiving extraneous signal.The two-way start-up circuit can merge into one the tunnel, also can separately use.

Each functional circuit all will have start-up circuit.Programming finishes to DMAC as CPU, and corresponding start-up circuit sends startup command.The control signal of start-up circuit effectively after, just carry out operations such as data transmission, can by the EOP of DMAC or CPU gives an order or other signal resets control signal.Each control circuit respectively has an address, cooperates information concerning order (as reading or writing or other order) to start.Close all to link together with the reset terminal that an address just starts each electric circuit with CPU and cooperate information concerning order orders such as () reading or writing that all start-up circuits are resetted.This start-up circuit also can utilize its output level height as the address (replacement toggle switch) of a control signal as going to control selection compression method 1 or compression method 2 or being used for changing ROM among Fig. 3.In these cases, closing can be with independent address.

Figure 20 is a clock number control circuit, this circuit, clock by or Men Yilu output, the one tunnel as counter clock, counter circuit simultaneously with certain output as or another road of door import.During this bit motion of counter, clock will stop output.During zero clearing, reset signal also is added to or door, and therefore, no-output when reset signal is effective begins output after reset signal is invalid.With counter everybody by be added to after merging with door should or, can control the time clock number of output easily.

Figure 18 circuit conversion, among the figure, the two-way latch totally 16 be arranged in order, per two connect a two paths of data and select circuit, that is to say that the odd bits of two numbers that are latched and the number that even bit is constituted are the new numbers that obtains respectively just.Here DMAC is with a slice multi-channel DMA C, the clock of making counter with AEN or other signal of DMAC, during work, earlier to counter O reset, reset signal is taken on through decoding by the address of start-up circuit, produce control signal simultaneously, second in counter is 0 through anti-phase and control signal and trigger a DMAC passage, twice of response back counter continuous counter, cooperate IOW that two data are write latch, second current potential of unison counter uprises another DMAC channel response, also respond twice, two data that will reconfigure respectively are defeated by buffer circuit, under the IOR effect, with its output, first DMAC channel response next .... these two DMAC passages are operated in the byte transfer mode and do not allow auto-initiation.Returning Figure 19.If will change the data order into horizontally-arranged (precedence) by original vertical setting of types, and import main RAM, can after data are imported among this RAM, start another road DMAC.Each pin that this DMAC is added to address ram is followed successively by the 6.7.1.2.3.4.5 position, and (1.2.3.0 4.5 is five of 32 dot matrix, 6.7. be to produce 32 points to need 2 four eight bit data, other place is similar), being transmitted as between memory to memory of they transmits, and controls relevant triple gate switch through decoding scheme start-up control circuit in this address simultaneously with the software command startup.

Circuit, each counting circuit, what rate request was high can select 74L393 or other model for use, when rate request hangs down.Available CD4040 etc., latch cicuit can be with 74LS373 etc.Tri-state buffer circuit can be used 74LS245,74LS244 etc., and in a word, these circuit can be used different circuit with each serial circuit such as various these functional circuits such as TTL series or HCOMS, and interface will suitably be changed.In above each circuit, some counter only has been the effect of a trigger, and these counters can replace with various trigger circuit.Sometimes, control signal is the high level ternary control end of tri-state buffer circuit that is subjected to its control when low, just can open triple gate, sometimes to use the EOP zero clearing, sometimes or other various situations, signal to be carried out being added to controlled circuit or next stage circuit after anti-phase, under these various situations, will carry out anti-phase.In circuit diagram and circuit block diagram, the outer DIS of tri-state buffer circuit frame is the ternary control of its circuit, the outer DIS of latch cicuit frame is the ternary output control terminal of latch cicuit, LE is for latching control end, and counter or other circuit place mark R are zero clearing or reset that CP is an input end of clock, counter CO is the carry end, each output terminal of QX (X counts arbitrarily) expression counter, latch cicuit xd is an input end, xa is output (X counts arbitrarily).

Figure 12 and Figure 21 are a kind of concrete circuit schemes of B.The course of work is as follows, and the output of A/D change-over circuit has ternary control.At first switch S 43 zero clearings, after trigger circuit produce trigger pip, the output high level, IC44 is output low level 3., and A/D change-over circuit triple gate is opened, the digital coding that obtains after the output analog signal conversionization, RAM is in the state of writing, IC48a and door output low level, IC42, IC43 begins counting, and digital coding is deposited among the RAM.After RAM is filled with, IC42 is pin output high level 6., IC45 is the pin output low level 3., IC44 is pin output high level 3., A/D change-over circuit triple gate is in high-impedance state, IC45 3. two electronic switches of foot control system is added to the counting circuit clear terminal with the field blanking signal respectively, and read clock signal is added to counting circuit input end of clock and another road counting circuit (this road counting circuit is carrying out the scan period zero clearing).The data of reading among the RAM are added to four road latch cicuits.After read clock signal is added to address progression circuit, data on the RAM appropriate address are read out simultaneously, another road counting circuit is output data also, pass through decoding scheme, the decoding scheme respective foot is exported high level successively, when this pin level descends, control corresponding latch cicuit with the RAM output data latch, in order reliably to latch, can be with code translator output and read pulse together by being added to latch cicuit again with door, data after being latched and line synchronizing signal (or blanking signal) go pulse-width modulation circuit to produce pulse-width signal, four road pulse-width signals pass through logical operation circuit, calculate careful after " compression ", the number of writing to change-over circuit produces the video and the radiofrequency signal that contain this information.Some replenishes: the RAM capacity can according to circumstances increase will reach height, the A/D change-over circuit will adopt parallel or high-speed a/d change-over circuit, obtaining data after the A/D conversion is added to time that RAM finishes and will lags behind the time that address ram changes, to guarantee after address modification, the raw address data can reliably be recorded, can solve by the method that seals in delay line, time-delay can be delayed time or delay time at other position the clock that will be added to A/D converter, delay line can be delayed time with digital gate circuit, or utilize symmetrical spiral cable etc. to delay time, circuit needs read clock signal, read clock signal is had an effect at line blanking period, and how many read clock signal pulse signals has relation in the number of line blanking period with the data that will exert oneself.Shown among the circuit RAM data processing as follows: each line blanking period provides four pulses, (first horizontal blanking signal after the field blanking signal ended of even field provides six pulses), the complete blanking signal on the scene of horizontal blanking signal is interior or outer, can read four data during each horizontal blanking signal, this four number according to this wherein two (preceding two or latter two) be main, exert oneself for attached carrying out " pressure " for two in addition, compression result is with pulse " the form appearance.Shown in circuit, two continuous content displayed are that different two continuous occasions become a complete picture.In order to strengthen decrement, ways such as latch cicuit, pulse-width modulation circuit can be enlarged (be preferably the 2H road otherwise, circuit is with complexity), to read the time clock number simultaneously and also enlarge accordingly, the input end of relevant gate circuit enlarges corresponding multiple.Shown in circuit, tight root gate circuit behind the pulse-width modulation circuit, if with two or and Sheffer stroke gate and two Sheffer stroke gates of heel and door remove, this input termination thereafter and door or remove, then the waveform part of Xian Shiing is thicker, but be generally influence not very big.On above basis decoding scheme is connect minimum several of address ram, then the image that shows on the display screen be every all identical.

Fig. 5 is used for producing the field frequency triangular wave.Constant current source gives the C1 average rate fair electricity, and field sync signal is controlled another triode switch, the last generation of C1 field frequency triangular wave.The amplitude of W1 control output triangular wave, the midpoint potential of W2 control output triangular wave.This field frequency triangular wave removes to control voltage controlled oscillator, and Voltage-Controlled oscillation circuit is that core constitutes (63 pages of Beijing electronics newspaper bound volumes 96 years, available this schematic diagram, but only produce the signal of a wave band with this page figure) by MC1648.Also can change schematic diagram into multiband,, connect different inductance, produce the oscillator signal of different frequency by waver control.As 20-40MHZ, 40-80MHZ, a plurality of wave bands such as 80-160MHZ.Here also available CD4017 etc. carries out wave band control, this circuit maximum frequency of oscillation is 225MHz, and a plurality of wave bands are set, and a mixting circuit is set in addition, certain wave band (frequency ratio is higher) mixing of this circuit and MC1648 obtains swept-frequency signal as 0～20MHz by the low pass filtered wave energy.Voltage controlled oscillator also can adopt other various circuit, as local oscillation circuit in the colour TV tuner, can increase LC loop, a few road again and increase several wave bands again, utilizes the tuner local oscillator.Mixting circuit is established a fixed frequency oscillatory circuit again.During the output high-frequency signal, with its failure of oscillation, at low frequency is to make its vibration, the circuit for generating triangular wave of voltage controlled oscillator is between the varactor, impedance is little, reduce resistance between the two in case of necessity, increase an inductance, can take out after the mixer stage various signals (at this moment because of do not add the amplitude control circuit signal amplitude with frequency to change, unevenness) signal exports through attenuator.With the frequency standard signal addition, be amplified to certain amplitude after the demodulation probe detection, remove pulse-width modulation circuit.This pulse-width modulation circuit core is NE555.After the synchronizing signal effect, 7 pin end, and 6 pin current potentials at the uniform velocity rise.When 6 pin current potentials are higher than 5 pin, the counter-rotating of 3 pin current potentials, 7 stir conducting, and 6 pin clampers are about four.Adjust each resistance, make NE555 5. 6. pin change at 4-8V.In the circuit in addition two voltage stabilizing diodes be make circuit output can with the TTL circuit compatibility, be better and the TTL circuit compatibility, can connect at this circuit CMOS-TTL interface circuit such as CD4049 connect again the TTL circuit at this moment two voltage stabilizing diodes just can.With this signal and synchronizing signal addition, just obtain vision signal, utilize televisor to observe the equipment under test frequency characteristic.Circuit shown in pulse-width modulation circuit also available " electronic production " bound volume 94 years the 121st, in the accompanying drawings, 6V is improved in the each point position, and antenna 2 changes the input composite synchronizing signal into, and the signal after the detection is added to the INPUT end through amplifying.Detecting circuit also can adopt " Beijing electronics newspaper " 55 pages of Fig. 4 of the 97 bound volume first volumes or Fig. 5, and Fig. 4 IC2 output connects pulse-width modulation circuit.In this circuit of this Fig. 4, C3 need not, C1 and C2 reduce capacity.Utilize the probe of this figure, the circuit of IC1 and IC2 formation is contained in the instrument casing, probe signal is carried out linear compensation and amplification, by adjusting relevant resistance, make IC2 6. pin output change at 0～4V, connect one 4 volts of voltage stabilizing diodes at 6. pin, connect power supply by resistance again, just can on voltage stabilizing diode, obtain the output of 4～8V, connect pulse-width modulation circuit.IC1 6. pin and IC2 3. connect a resistance between the pin, the rhombus frequency standard signal that marker circuit is produced also is added to 3. pin of IC2 by a resistance again, IC2 just constitutes an adding circuit, and frequency standard signal is introduced wherein.Frequency marking letter circuit can adopt the marker circuit in the sweep generator.

The each several part circuit of television sweeper additional inverter is identical with the partial circuit of circuit sweep generator or have the circuit of identical function, also can be replaced by the same circuits of various sweep generators, as swept-frequency signal generation circuit, marker circuit etc.

Fig. 1 is the basic circuit block scheme of this instrument.In the drawings, used the circuit of a complete stored digital formula oscillograph/table, oscillograph/watch circuit comprises: input circuit, the RAM of A/D change-over circuit, trigger circuit, time base circuit, various storage datas and ROM, and formations such as CPU, display screen and accessory circuit thereof, it and each logical a slice multi-channel DMA C swap data of each data processing circuit, here, DMAC is operated in the cascade state, and swap data is subjected to the relevant controlling signal controlling of clock signal generation circuit simultaneously.Oscillographic about circuit (remove display screen and accessory circuit) and formation memory-type TV oscilloscope additional inverter such as each data processing circuit, clock signal generation circuit, signaling conversion circuit.Shown in Figure 1ly connect the color television encoding circuit by clock signal generation circuit and connect modulator, simultaneously audio frequency oscillator also connects the television signal generator that modulator etc. constitutes, connect voltage controlled oscillator by triangle wave generating circuit and connect output circuit, again the pulse-width modulation circuit of accepting the synchronizing signal control that clock signal generation circuit sends by demodulation probe accept the synchronizing signal control that clock signal generation circuit sends signaling conversion circuit or by demodulation probe connect following signal acquisition circuit and after each connecting circuit constitute utilize televisor to show the instrument of tested equipment amplitude versus frequency characte and accept the data compression that digital signal is converted into vision signal or pattern signal or the change-over circuit of the synchronizing signal control that clock signal generation circuit sends or behind data compression or change-over circuit, accept the data that synchronizing signal that clock signal generation circuit sends controls and adjust circuit in proper order by the signals collecting of instruments such as ordinary numbers oscillograph and storage circuit, the output of data compression or change-over circuit or data are adjusted the vision signal feed signals change-over circuit of the output of circuit in proper order, memory-type TV oscilloscope additional inverter three parts of final signal input televisor constitute, digital oscilloscope/the table of each circuit of oscillograph/off-balancesheet shown in Figure 1 can being packed into is inner, this is only oscilloscope panel need be increased several signals discrepancy jacks and several Control turn-knob and get final product.The control turn-knob that increases has: adjustings of frequency sweep centre frequency, swept-frequency signal bandwidth control, swept-frequency signal decay, the waver turn-knob is (as with controls such as CD4017, can increase a microswitch gets final product, at this moment, increase several wave band pilot lamp, available LED).Connect the color television encoding device behind the clock signal generation circuit, scrambler is encoded to the TV synchronousing signal that the clock signal circuit produces, and produces colour bar signal, audio frequency oscillator produces sound signal, two signals respectively have one tunnel output, and other has one the tunnel to remove modulator, produce radiofrequency signal.Signal generator partly has three output plugholes at least.Among the figure, H represents line synchronizing signal, and V represents field sync signal.Memory-type TV oscilloscope additional inverter connects described various digital processing circuits of literary composition and clock signal generation circuit, formations such as signaling conversion circuit by stored digital formula wave table.Circuit shown in Figure 1 can show waveform by TV.At this moment, the oscillograph appearance only need increase several Control turn-knob and knob, increases several signal input and output jacks and gets final product.Utilize certain circuit-switched data treatment circuit work of CPU control selection in the oscillograph, the control timing signal generating circuit produces various clock signals, and control other each circuit, 4 times of colour subcarrier signal generation circuit produce four times of subcarrier signals and lead up to four frequency divisions and remove the sampling clock circuit of colorflexer.For introducing this subcarrier signal, to above the change of color television encoding device is as follows: change the subcarrier crystal into transformer, the subcarrier signal that obtains behind the elementary introducing frequency division, the secondary mother crystal position that is associated in, (or series connection) in parallel electric capacity, resonance is in subcarrier frequency.When the observation TV signal, make sampling clock in order to adopt the signal relevant with reference subcarrier, scheme is as follows: sampling clock signal is produced by several times of subcarrier signal crystal during the A/D conversion, (frequency is high more, observation is accurate more comparatively speaking), as 16 times of four times, octuple, this crystal oscillator signal is by frequency division, the reference subcarrier signal.Here, signal generator also can adopt other various signal generators, and it is identical to introduce the subcarrier method.

Circuit shown in Figure 1 also can utilize other various standard PC cases or non-standard cabinet.Fig. 2 is the panel figure of cabinet of the most basic function of this instrument.Among the figure, next row is various signal input and output jacks, and the little square frame of rightmost is a power switch.Upwards the turn-knob of four band scales is respectively swept-frequency signal centre frequency, bandwidth, swept-frequency signal decay, measured signal decay adjusting turn-knob again, the upper left corner one row's LED light, power supply indication, the indication of swept-frequency signal frequency range, each duty indication etc. are arranged, it under the pilot lamp fine motion push switch, can change its quantity as required, microswitch is input of CPU control signal and the control of swept-frequency signal wave band, and the panel upper right corner is a display screen, can be oscillatron or LCDs.The whole instrument shell sizes can compare arbitrarily.As panel size is 25cm * 15cm, and thick is 15cm (if use oscillatron, the then minimum oscillatron length that is not less than).This oscillograph is removed display screen, and one is utilized televisor to make display demonstration measured signal waveform, testing apparatus frequency characteristic and the instrument with signal generator exactly.This three part also can be removed wherein a part or two parts (public part wherein will keep), is exactly another kind of multiple function apparatus.(above-mentioned oscillograph also can carry out this way, promptly remove signal generator or frequency sweep part, or these two parts is removed entirely), at this moment, the knob turn-knob on the panel, signal input and output receptacle portion use less than, this part can remove or do ornamental also passable.

In order much to be contained the radiofrequency signal of channel signals, the measure that can take is: go to be modulated by vision signal as carrier wave with the signal that contains a variety of frequency signals.The signal of multiple frequency, each frequency is the integral multiple of the low-limit frequency signal after their mixing, to reduce assorted signal, as F1.F2.F3 etc., can adopt 16MHz.80MHz.320MHz etc., if after the mixing at least 2 times of the signal low-limit frequency vision signal and second accompanying sound intermediate frequency signal, can adopt at interval 2 times of frequency of radio station.In each signal, frequency ratio is lower, carry out amplitude limit and obtain square-wave signal (include and enrich harmonic wave).They will carry out mixing, and then the modulation of tested frequency signal.

Each signal source can be as follows: the F1 that frequency ratio is lower is made of (as 74LS series crystal and gate circuit, the most handy 74S series) zoom into square-wave signal by gate circuit, mixting circuit is removed in the decay of leading up to, the bandwidth-limited circuit of leading up to is selected the higher harmonic wave of frequency ratio (as 80MHz) F2, because of the F1 amplitude very high, so the F2 amplitude is still than higher, at this moment, can utilize diode to carry out amplitude limit and obtain square-wave signal, square-wave signal one tunnel removes mixting circuit, can also obtain another higher frequency signal F3......F1.F2.F3 etc. again and get 16MHz, 80MHz, the 240MHz equifrequent, bandpass filter can be made of inductance capacitance.Here, not high to the signal spectrum purity requirement, also can directly select desired signal by the series LC loop.Amplitude limit can be finished by simple diode limiting circuit, also can finish by differential amplifier circuit, each signal such as F1.F2.F3 also can followingly obtain, by frequency is the crystal oscillating circuit generation F2 square wave of F2, obtain the high F3 signal of frequency by last method, obtain the low F1 signal of frequency etc. by frequency division, various signals carry out mixing again.Perhaps take out carrier signal,, obtain and to be obtained low frequency signal by the signal of acceptance such as relevant gate circuit (as 74S series, ECL series) by frequency division, from its harmonic wave, take out high-frequency signal through amplifying from modulator.These signals (comprising the former signal of penetrating) carry out mixing again.During mixing, will advance decay when individual signal amplitude is too big, modulator can adopt various modulators, can adopt two difference channels to be operated in not plateau by it.Report the circuit of the 47th page of MC1496P formation of 97 bound volumes as Beijing electronics.This circuit modification is as follows: the AFIN input capacitance changes tens microfarads into by 104, and R3, R5 directly connect the MC1496P1 pin, make R3 into, the R5 junction is by 1 pin of resistance connection MC1496P, R3 simultaneously, the R5 junction connects a diode, diode cathode connects the MC1496P4 pin, removes R4, during work, when strong synchronous head arrives, 1 pin is than 4 pin potential difference (PD) maximums, and when image was the brightest, 1 pin was higher slightly than 4 pin current potentials.Whole process 1 pin is than 4 pin current potential height.

Figure 27 is the multichannel signal generating circuit, and by crystal oscillating circuit output F1 signal, the one tunnel removes the triode mixting circuit, another road by after the frequency-selecting of LC loop by diode limiting, also remove mixting circuit, signal removes modulator after the mixing, is modulated by the AV signal.It is modulated also can only with frequency to be that F1 is that square wave goes as carrier wave here.

Want two to show that respectively different data send into pattern data before Figure 19 circuit, can be earlier through Figure 18 circuit conversion.

Claims (1)

1. A kind of multifunctional radio examining-repairing instrument connects the color television encoding circuit by clock signal generation circuit and connects modulator, simultaneously audio frequency oscillator also connects the television signal generator that modulator etc. constitutes, connect voltage controlled oscillator by triangle wave generating circuit and connect output circuit, again the pulse-width modulation circuit of accepting the synchronizing signal control that clock signal generation circuit sends by demodulation probe accept the synchronizing signal control that clock signal generation circuit sends signaling conversion circuit or by demodulation probe connect following signal acquisition circuit and after each connecting circuit constitute utilize televisor to show the instrument of tested equipment amplitude versus frequency characte and accept the data compression that digital signal is converted into vision signal or pattern signal or the change-over circuit of the synchronizing signal control that clock signal generation circuit sends or behind data compression or change-over circuit, accept the data that synchronizing signal that clock signal generation circuit sends controls and adjust circuit in proper order by the signals collecting of instruments such as ordinary numbers oscillograph and storage circuit, data compression or change-over circuit output or data are adjusted the vision signal feed signals change-over circuit of the output of circuit in proper order, the formations such as memory-type TV oscilloscope additional inverter of final signal input televisor is characterized in that connecing data compression or change-over circuit behind the signals collecting storage circuit, or connect data behind data compression or the change-over circuit again and adjust circuit in proper order, data compression or change-over circuit output or data are adjusted the vision signal of circuit output in proper order and are finally imported televisor.

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