CN221262364U - Power semiconductor element packaging structure - Google Patents
Power semiconductor element packaging structure Download PDFInfo
- Publication number
- CN221262364U CN221262364U CN202322424216.8U CN202322424216U CN221262364U CN 221262364 U CN221262364 U CN 221262364U CN 202322424216 U CN202322424216 U CN 202322424216U CN 221262364 U CN221262364 U CN 221262364U
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- power semiconductor
- semiconductor element
- circuit board
- metal foil
- conductive layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000011888 foil Substances 0.000 claims description 37
- 239000000919 ceramic Substances 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 239000011224 oxide ceramic Substances 0.000 claims description 3
- 229910052574 oxide ceramic Inorganic materials 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a power semiconductor element packaging structure, which comprises a circuit board, a power semiconductor element, a packaging body and a heat conduction component, wherein the circuit board is arranged on the power semiconductor element; the insulating substrate of the circuit board is internally and penetratingly provided with a metal block, the first surface of the circuit board is provided with a first conductive layer, the second surface of the circuit board is provided with a second conductive layer, and the second conductive layer comprises a first conductive pattern connected with the metal block and a second conductive pattern separated from the metal block; the power semiconductor element is arranged on the second surface of the circuit board, a plurality of electrodes are arranged on the first connecting surface of the power semiconductor element facing the circuit board, and the plurality of electrodes are respectively connected with the first conductive pattern and the second conductive pattern; the packaging body is arranged on the second surface of the circuit board and packages the power semiconductor element inside; the heat conduction component is arranged in the packaging body and is connected with the second connecting surface of the power semiconductor element. The utility model not only can realize double-sided heat dissipation, but also has the advantages of high integration level and low parasitic inductance.
Description
Technical Field
The utility model relates to the field of semiconductor packaging; and more particularly, to a power semiconductor device package structure.
Background
Power semiconductor devices such as IGBT chips and MOSFET chips are widely used in various power electronics devices, and as power electronics devices are miniaturized, such power semiconductor devices often adopt a modular embedded package structure integrally packaged with peripheral electronic devices. When the power semiconductor element works, a large amount of heat is generated, and if the packaging structure cannot timely emit the generated heat, the work of the power semiconductor element and peripheral electronic elements thereof is seriously affected.
In the prior art, the package structure of the power semiconductor element has various types, such as BGA (Ball GRID ARRAY ), LGA (LAND GRID ARRAY, grid array package) and embedded in a circuit board, but these package structures still have some problems of insufficient heat dissipation performance, complex structure and the like, and needs to be improved.
Disclosure of utility model
The utility model mainly aims to provide a power semiconductor element packaging structure which has a simple structure and better heat dissipation performance.
In order to achieve the above main object, the present utility model discloses a power semiconductor element package structure, comprising:
The circuit board comprises an insulating substrate, a first conductive layer and a second conductive layer, wherein a metal block is arranged in the insulating substrate in a penetrating manner; the first conductive layer is arranged on the first surface of the circuit board, the second conductive layer is arranged on the second surface of the electric board, and the second conductive layer comprises a first conductive pattern connected with the metal block and a second conductive pattern arranged separately from the metal block;
A power semiconductor element disposed on the second surface of the circuit board; the power semiconductor element is provided with a first connecting surface facing the circuit board and a second connecting surface facing away from the circuit board, a plurality of electrodes are arranged on the first connecting surface of the power semiconductor element, one part of the electrodes is connected with the first conductive pattern, and the other part of the electrodes is connected with the second conductive pattern;
A package body disposed on the second surface of the circuit board and having the power semiconductor element packaged therein; and a heat conduction component is arranged in the packaging body and is connected with the second connecting surface of the power semiconductor element.
According to one embodiment of the utility model, the heat conducting component comprises a ceramic plate, and a first metal foil and a second metal foil which are respectively arranged on two opposite sides of the ceramic plate, wherein the first metal foil is connected with the second connecting surface of the power semiconductor element, and the second metal foil is arranged to be exposed from the packaging body.
Further, the thickness of the first metal foil and the second metal foil is 0.2mm to 1.5mm.
Further, the package comprises a plurality of layers of insulating core boards, wherein the insulating core boards are connected through bonding sheets in a bonding mode, and the side edges of the ceramic sheets are clamped between the insulating core boards. Preferably, the entire side edge of the ceramic sheet is clamped by the insulating core plate.
Further, the ceramic sheet is an aluminum nitride, silicon carbide or aluminum oxide ceramic sheet; the thickness of the ceramic sheet may be 0.2mm to 1.0mm.
Further, an electrode electrically connected with the first metal foil is arranged on the second connection surface of the power semiconductor element; the first metal foil is electrically connected with the corresponding first conductive patterns through conductive blocks; or the first metal foil is electrically connected to a conductive member exposed from the package body.
According to another embodiment of the present utility model, the package is a resin or plastic package having an integrally molded structure.
Further, a protruding part is arranged on the side face of the metal block; the metal block may be a copper block.
The technical scheme of the utility model has at least the following beneficial effects:
The first connecting surface of the power semiconductor element is connected with the metal block in the circuit board, and the second connecting surface is connected with the heat conduction component in the packaging body, so that double-sided heat dissipation can be realized, and the power semiconductor element has the advantage of high heat dissipation efficiency; the metal block in the circuit board can also play a role in transmitting large current, and a lead frame is not required to be additionally arranged in the packaging body, so that the packaging structure is simplified, and the manufacturing cost is reduced.
Furthermore, the two surfaces of the circuit board are provided with the first conductive layer and the second conductive layer, and the power semiconductor element and other electronic elements can be integrally arranged on the two surfaces of the circuit board, so that the circuit board not only has high integration level, but also is beneficial to reducing the area of a current loop so as to reduce parasitic inductance.
The objects, technical solutions and advantages of the present utility model will be more clearly described below, and the present utility model will be further described in detail with reference to the accompanying drawings and the detailed description.
Drawings
FIG. 1 is a schematic cross-sectional view of embodiment 1 of the present utility model;
FIG. 2 is a schematic cross-sectional view of embodiment 2 of the present utility model;
FIG. 3 is a schematic cross-sectional view of embodiment 3 of the present utility model;
FIG. 4 is a schematic cross-sectional view of embodiment 4 of the present utility model;
Fig. 5 is a schematic cross-sectional structure of embodiment 5 of the present utility model.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model, it should be understood that the following examples and detailed description are presented for purposes of illustration only and are not intended to limit the scope of the utility model.
Example 1
As shown in fig. 1, the package structure of embodiment 1 includes a circuit board 10, a power semiconductor element 20, and a package body 30. In the present utility model, the circuit board 10 may be a fiberglass cloth-based circuit board, such as an FR-4 circuit board; the power semiconductor element 20 may be a power chip such as an IGBT chip or a MOSFET chip. The number of power semiconductor elements 20 in each package may be one or more, and is specifically determined by circuit design requirements, which is not limited by the present utility model.
The circuit board 10 includes an insulating substrate 11, a metal block 12 (e.g., copper block) is penetratingly disposed in the insulating substrate 11, a first conductive layer 131 is disposed on a first surface of the circuit board 10, and a second conductive layer 132 is disposed on a second surface of the circuit board 10. The first conductive layer 131 and the second conductive layer 132 may be formed by etching, and may each include one or more conductive patterns, and corresponding conductive patterns of the first conductive layer 131 and the second conductive layer 132 are electrically connected through the via hole 133 or the metal block 12 in the insulating substrate 11; the power semiconductor element 20 is electrically connected to the second conductive layer 132, and the power pins and the signal pins of the power semiconductor element 20 may be disposed on the first conductive layer 131. In some embodiments of the present utility model, the circuit board 10 may have an inner conductive trace disposed within the insulating substrate 11 in addition to the first conductive layer 131 and the second conductive layer 132.
In an embodiment, the second conductive layer 132 includes one or more first conductive patterns 1321 connected to the metal block 12 and one or more second conductive patterns 1322 spaced apart from the metal block 12; the power pin of the first conductive layer 131 may be electrically connected to the first conductive pattern 1321 through the metal block 12, and the signal pin may be electrically connected to the second conductive pattern 1322 through the via hole 133. The number of metal blocks 12 may be one or more; one end of each metal block 12 may be correspondingly connected to one of the first conductive patterns 1321, and the other end may be correspondingly connected to a power pin of the first conductive layer 131. The metal block 12 can perform electric conduction and heat conduction simultaneously, so that not only can large current be transmitted when the power semiconductor element 20 works, but also the rapid heat dissipation of the power semiconductor element 20 is facilitated.
The power semiconductor element 20 is arranged on the second surface of the circuit board 10, for example soldered to the second surface of the circuit board 10 in an SMT process. The power semiconductor element 20 has a first connection surface 21 facing the circuit board 10 and a second connection surface 22 facing away from the circuit board 10, and a plurality of electrodes are provided on the first connection surface 21, a part of the plurality of electrodes is connected to the first conductive pattern 1321, and another part of the plurality of electrodes is connected to the second conductive pattern 1322. For example, an IGBT chip as an example of the power semiconductor element 20 has a G pole, a D pole, and an S pole provided on the first connection face 21 thereof, the D pole and the S pole being connected to two corresponding first conductive patterns 1321, respectively, and the G pole being connected to a corresponding second conductive pattern 1322.
The package body 30 is disposed on the second surface of the circuit board 10, and encapsulates the power semiconductor element 20 therein. In embodiment 1, the package 30 includes a plurality of insulating core boards 31, the insulating core boards 31 are bonded to each other by an adhesive sheet 32, and the package 30 can be fixed on the second surface of the circuit board 10 by the adhesive sheet 32.
The package 30 is provided with a heat conducting component, and the heat conducting component is connected with the second connection surface 22 of the power semiconductor element 20. Specifically, the heat conducting assembly includes a ceramic sheet 41, a first metal foil 42 and a second metal foil 43 respectively disposed on opposite sides of the ceramic sheet 41, the first metal foil 42 being connected to the second connection surface 22 of the power semiconductor element 20, the second metal foil 43 being disposed to be exposed from the package body 30. In an embodiment, both the first metal foil 42 and the second metal foil 43 may include a copper foil layer. Further, the thickness of the first metal foil 42 and the second metal foil 43 may be 0.2mm to 1.5mm, and the thickness of the first metal foil 42 and the second metal foil 43 may be the same or different, for example, each about 0.30mm.
The shape of the ceramic sheet 41 may be any shape such as a rectangle or a circle, and may be set as needed, which is not limited by the present utility model. The ceramic sheet 41 may be an aluminum nitride, silicon carbide or aluminum oxide ceramic sheet, and may have a thickness of 0.2mm to 1.0mm, for example, about 0.40mm. As shown in fig. 1, the side edges of the ceramic sheet 41 protrude from the first and second metal foils 42 and 43 and are partially or entirely sandwiched between the insulating core sheets 31, which not only enables the thermally conductive assembly to be reliably embedded in the package body 30, but also can increase the creepage distance of the first and second metal foils 42 and 43 to enhance the withstand voltage performance of the package structure.
In the present utility model, the first connection face 21 and the second connection face 22 of the power semiconductor element 20 may be connected to the second conductive layer 132 and the first metal foil 42, respectively, by the solder material 23. The solder material 23 may be solder paste, nano silver paste or nano copper paste, but is not limited thereto.
Example 2
As shown in fig. 2, embodiment 2 differs from embodiment 1 in that: the package 30 in embodiment 2 is a resin or plastic package with an integrally formed structure, which can be manufactured by a method such as mold injection, so as to simplify the manufacturing cost of the package structure.
Example 3
As shown in fig. 3, embodiment 3 differs from embodiment 1 in that: in embodiment 3, the side surface of the metal block 12 is provided with the protruding portion 121, so that the metal block 12 and the insulating substrate 11 have better bonding strength.
Example 4
As shown in fig. 4, embodiment 4 differs from embodiment 1 in that: in example 4, electrodes are also provided on the second connection surface 22 of the power semiconductor element 20, for example, the G-pole and S-pole of the power semiconductor element 20 are provided on the first connection surface 21, and the D-pole is provided on the second connection surface 22.
In embodiment 4, the electrode on the second connection face 22 may be welded to the first metal foil 42 by the conductive welding material 23, and a part of the first metal foil 42 protrudes from the side edge of the ceramic sheet 41. One end of the conductive member 51 is connected to the first metal foil 42, and the other end is exposed to the package body 30 and forms a power pin of the power semiconductor element 20 to achieve external electrical connection of the electrode on the second connection face 22.
Example 5
As shown in fig. 5, embodiment 5 differs from embodiment 1 in that: in example 5, electrodes are also provided on the second connection surface 22 of the power semiconductor element 20, for example, the G-pole and S-pole of the power semiconductor element 20 are provided on the first connection surface 21, and the D-pole is provided on the second connection surface 22.
In embodiment 5, the electrode (e.g., D-electrode) on the second connection surface 22 can be welded on the first metal foil 42 by the conductive welding material 23, and the first metal foil 42 is electrically connected to the corresponding first conductive pattern 1321 by the conductive bump 52 (e.g., copper bump), and further electrically connected to the corresponding power pin of the first conductive layer by the corresponding metal bump 12. Wherein the first metal foil 42 may be welded with the conductive block 52 or have an integrally formed structure.
In the present utility model, the first surface of the circuit board 10 may be completely exposed outside the package structure, or may be partially or completely covered by another package body. Further, the semiconductor package may further have other electronic components, not shown, such as a capacitor, a resistor, an inductor, a diode, a triode, a driving chip, etc., which may be selectively connected to the first conductive layer 131 or the second conductive layer 132, so that not only high integration/integration of the package is achieved, but also a current loop area is advantageously reduced to reduce parasitic inductance.
Although the present utility model has been described by way of examples, the foregoing examples are provided for illustrative purposes only and are not intended to limit the scope of the utility model, and equivalent substitutions or modifications by those skilled in the art according to the present utility model shall be construed to be encompassed by the scope of the present utility model as defined by the appended claims.
Claims (9)
1. A power semiconductor element package structure, characterized by comprising:
The circuit board comprises an insulating substrate, a first conductive layer and a second conductive layer, wherein a metal block is arranged in the insulating substrate in a penetrating manner; the first conductive layer is arranged on the first surface of the circuit board, the second conductive layer is arranged on the second surface of the circuit board, and the second conductive layer comprises a first conductive pattern connected with the metal block and a second conductive pattern arranged separately from the metal block;
A power semiconductor element disposed on the second surface of the circuit board; the power semiconductor element is provided with a first connecting surface facing the circuit board and a second connecting surface facing away from the circuit board, a plurality of electrodes are arranged on the first connecting surface of the power semiconductor element, one part of the electrodes is connected with the first conductive pattern, and the other part of the electrodes is connected with the second conductive pattern;
A package body disposed on the second surface of the circuit board and having the power semiconductor element packaged therein; and a heat conduction component is arranged in the packaging body and is connected with the second connecting surface of the power semiconductor element.
2. The power semiconductor device package according to claim 1, wherein: the heat conduction assembly comprises a ceramic plate, and a first metal foil and a second metal foil which are respectively arranged on two opposite sides of the ceramic plate, wherein the first metal foil is connected with a second connecting surface of the power semiconductor element, and the second metal foil is arranged to be exposed from the packaging body.
3. The power semiconductor device package according to claim 2, wherein: the thickness of the first metal foil and the second metal foil is 0.2 mm-1.5 mm.
4. The power semiconductor device package according to claim 2, wherein: the package body comprises a plurality of layers of insulating core plates, wherein the insulating core plates are connected through bonding sheets in a bonding mode, and the side edges of the ceramic sheets are clamped between the insulating core plates.
5. The power semiconductor device package according to claim 2, wherein: the ceramic plate is an aluminum nitride, silicon carbide or aluminum oxide ceramic plate; the thickness of the ceramic sheet is 0.2 mm-1.0 mm.
6. The power semiconductor device package according to claim 2, wherein: an electrode connected with the first metal foil is arranged on the second connecting surface of the power semiconductor element;
The first metal foil is electrically connected with the corresponding first conductive patterns through conductive blocks; or the first metal foil is electrically connected to a conductive member exposed from the package body.
7. The power semiconductor element package structure according to claim 1 or 2, wherein: the package body is a resin or plastic package body with an integrated structure.
8. The power semiconductor element package structure according to claim 1 or 2, wherein: the side of the metal block is provided with a protruding part.
9. The power semiconductor element package structure according to claim 1 or 2, wherein: the metal block is a copper block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322424216.8U CN221262364U (en) | 2023-09-07 | 2023-09-07 | Power semiconductor element packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322424216.8U CN221262364U (en) | 2023-09-07 | 2023-09-07 | Power semiconductor element packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221262364U true CN221262364U (en) | 2024-07-02 |
Family
ID=91655507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322424216.8U Active CN221262364U (en) | 2023-09-07 | 2023-09-07 | Power semiconductor element packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN221262364U (en) |
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2023
- 2023-09-07 CN CN202322424216.8U patent/CN221262364U/en active Active
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| Date | Code | Title | Description |
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| GR01 | Patent grant |