CN221239266U

CN221239266U - I.MX6ULL-based small-volume stamp hole core plate

Info

Publication number: CN221239266U
Application number: CN202323202667.3U
Authority: CN
Inventors: 刘火良; 王金亮
Original assignee: Dongguan Wildfire Technology Co ltd
Current assignee: Dongguan Wildfire Technology Co ltd
Priority date: 2023-11-27
Filing date: 2023-11-27
Publication date: 2024-06-28
Anticipated expiration: 2033-11-27

Abstract

The utility model discloses a small-volume stamp hole core board based on i.MX6ULL, wherein a power supply monitoring module is respectively and electrically connected with a main control chip, a memory module, a storage module and stamp hole interfaces; the power monitoring module comprises a power monitoring chip U10 and a power electronic switch U9, wherein a RESET pin of the power monitoring chip U10 is electrically connected with an EN pin of the power electronic switch U9, an MR pin of the power monitoring chip U10 is electrically connected with the main control chip, a VDD pin of the power monitoring chip U10 and an IN pin of the power electronic switch U9 are respectively electrically connected with the power supply module, a GND pin of the power monitoring chip U10 is grounded, an OUT pin of the power electronic switch U9 is respectively electrically connected with the memory module, the storage module and each stamp hole interface, and an ISET pin and the GND pin of the power electronic switch U9 are respectively grounded. The stability of starting the core board is improved, continuous operation under the condition of unstable power supply is prevented, the operation stability and reliability are improved, the customization capability and compatibility of the core board are improved, and the application scene is enlarged.

Description

I.MX6ULL-based small-volume stamp hole core plate

Technical Field

The utility model relates to the technical field of core boards, in particular to an i.MX6ULL-based small-volume stamp hole core board.

Background

A core board, also known as a computer module, is a minimized computer system comprised of a processor, memory, storage, circuit boards, and operating software. With the progress of intelligence, more and more embedded products need to perform a series of functions of interaction, internet access, etc. through a core board. At present, man-machine interaction interfaces of embedded products are increasingly complex, data processing capacity is increasingly large, network communication speed and network communication delay are also increasingly high, the performances of a traditional low-performance core board and a common single chip microcomputer are weaker, requirements of the embedded products are difficult to meet, and the conditions of blocking and dead halt often occur. And for embedded products with high performance requirements, bare computers or development modes of embedded operating systems under a single chip microcomputer are required to be researched, complicated peripheral driving and the problem that certain intermediate components may be lacking are required to be researched, a great amount of time is required to debug, the marketing speed of the products is delayed, and the development period is long.

On the other hand, when the i.mx6ull-based core board in the prior art is powered on, the i.mx6ull main chip and the peripheral device are powered on simultaneously, so that the i.mx6ull main chip cannot completely identify the peripheral device, the starting failure is caused, the starting success rate is low, the existing core board still keeps running under the condition of unstable power supply, and the risk of crashing or even burning the core board is caused when the existing core board runs under the condition of unstable power supply, so the improvement is necessary.

Disclosure of utility model

Aiming at the defects existing in the prior art, the utility model aims to provide the i.MX6ULL-based small-volume stamp hole core board, which improves the starting stability of the core board, prevents continuous operation under the condition of unstable power supply, improves the operation stability and reliability of the core board, improves the customization capability and compatibility of the core board and expands the application scene.

In order to achieve the above purpose, the technical scheme adopted by the utility model is as follows: the small-volume stamp hole core board based on the i.MX6ULL comprises a printed circuit board, wherein the printed circuit board is provided with a main control chip, a memory module, a storage module, a power supply module and a power supply monitoring module;

A plurality of stamp hole interfaces are arranged around the printed circuit board;

the model of the main control chip is i.MX6ULL;

the main control chip is respectively and electrically connected with the memory module, the storage module and the stamp hole interfaces;

the power supply module is respectively and electrically connected with the main control chip and the power supply monitoring module,

The power supply monitoring module is respectively and electrically connected with the main control chip, the memory module, the storage module and the stamp hole interfaces;

The power supply monitoring module comprises a power supply monitoring chip U10 and a power electronic switch U9,

The RESET pin of the power monitoring chip U10 is electrically connected with the EN pin of the power electronic switch U9, the MR pin of the power monitoring chip U10 is electrically connected with the main control chip, the VDD pin of the power monitoring chip U10 and the IN pin of the power electronic switch U9 are respectively electrically connected with the power supply module, the GND pin of the power monitoring chip U10 is grounded,

The OUT pin of the power electronic switch U9 is electrically connected with the memory module, the storage module and the stamp hole interfaces respectively, and the ISET pin and the GND pin of the power electronic switch U9 are grounded respectively.

In a further technical scheme, the power supply monitoring module is further provided with a resistor R79, a resistor R78, a resistor R77, a resistor R74, a capacitor C104 and a capacitor C33, wherein a first end of the resistor R79 is electrically connected between a RESET pin of the power supply monitoring chip U10 and an EN pin of the power electronic switch U9, a second end of the resistor R79 is grounded, the resistor R78 is serially connected between an MR pin of the power supply monitoring chip U10 and the main control chip, a first end of the resistor R77 is electrically connected with an ISET pin of the power electronic switch U9, a second end of the resistor R77 is grounded, a node A is arranged between an OUT pin of the power electronic switch U9 and each stamp hole interface, the memory module and the storage module are respectively electrically connected with the node A, the resistor R74 is serially connected between the node A and each stamp hole interface, the capacitor C104 is serially connected between a VDD pin of the power supply monitoring chip U10 and a GND pin, and a first end of the capacitor C33 is electrically connected with the node A, and a second end of the capacitor C33 is grounded.

In a further technical scheme, the model of the power supply monitoring chip U10 is VP811REUS/T, the model of the power electronic switch U9 is MT9700, and the resistance value of the resistor R77 is 3.4K.

In a further technical scheme, the memory module comprises a memory voltage stabilizing circuit and at least one memory chip, the memory voltage stabilizing circuit is provided with a voltage stabilizing chip U6, the VIN pin of the voltage stabilizing chip U6 is electrically connected with the OUT pin of the power electronic switch U9, the EN pin of the voltage stabilizing chip U6 is electrically connected with the VIN pin of the voltage stabilizing chip U6, the LX pin and the FB pin of the voltage stabilizing chip U6 are respectively electrically connected with the memory chip, and the GND pin of the voltage stabilizing chip U6 is grounded.

In a further technical scheme, the memory voltage stabilizing circuit is also provided with a capacitor C4, a capacitor C20, a capacitor C21, a resistor R3, a resistor R4, a resistor R5 and an inductor L1,

The first end of the capacitor C4 is electrically connected between the VIN pin of the voltage stabilizing chip U6 and the OUT pin of the power electronic switch U9, the second end of the capacitor C4 is grounded,

The first end of the inductor L1 is electrically connected with the LX pin of the voltage stabilizing chip U6, the second end of the inductor L1 is electrically connected with the first end of the resistor R4, the second end of the resistor R4 is electrically connected with the memory chip,

The first end of the capacitor C20 is electrically connected with the FB pin of the voltage stabilizing chip U6, the second end of the capacitor C20 is electrically connected between the inductor L1 and the resistor R4,

The first end of the resistor R3 is electrically connected between the capacitor C20 and the FB pin of the voltage stabilizing chip U6, the second end of the resistor R3 is electrically connected between the inductor L1 and the resistor R4,

The first end of the resistor R5 is electrically connected between the capacitor C20 and the FB pin of the voltage stabilizing chip U6, the second end of the resistor R5 and the second end of the capacitor C21 are respectively grounded, and the first end of the capacitor C21 is electrically connected between the inductor L1 and the resistor R4.

In a further technical scheme, the storage module comprises a storage voltage stabilizing circuit and at least one storage chip, the storage chip is selected from a NAND chip or an eMMC chip,

The memory voltage stabilizing circuit is provided with a voltage stabilizing chip U7, the VIN pin of the voltage stabilizing chip U7 is electrically connected with the OUT pin of the power electronic switch U9, the EN pin of the voltage stabilizing chip U7 is electrically connected with the VIN pin of the voltage stabilizing chip U7, the LX pin and the FB pin of the voltage stabilizing chip U7 are respectively electrically connected with the storage chip, and the GND pin of the voltage stabilizing chip U7 is grounded.

In a further technical scheme, the storage voltage stabilizing circuit is also provided with a capacitor C5, a capacitor C29, a capacitor C28, a resistor R9, a resistor R8, a resistor R11 and an inductor L2,

The first end of the capacitor C5 is electrically connected between the VIN pin of the voltage stabilizing chip U7 and the OUT pin of the power electronic switch U9, the second end of the capacitor C5 is grounded,

The first end of the inductor L2 is electrically connected with the LX pin of the voltage stabilizing chip U7, the second end of the inductor L2 is electrically connected with the first end of the resistor R8, the second end of the resistor R8 is electrically connected with the storage chip,

The first end of the capacitor C29 is electrically connected with the FB pin of the voltage stabilizing chip U7, the second end of the capacitor C29 is electrically connected between the inductor L2 and the resistor R8,

The first end of the resistor R9 is electrically connected between the capacitor C29 and the FB pin of the voltage stabilizing chip U7, the second end of the resistor R9 is electrically connected between the inductor L2 and the resistor R8,

The first end of the resistor R11 is electrically connected between the capacitor C29 and the FB pin of the voltage stabilizing chip U7, the second end of the resistor R11 and the second end of the capacitor C28 are grounded respectively, and the first end of the capacitor C28 is electrically connected between the inductor L2 and the resistor R8.

In a further technical scheme, a low-voltage stabilizing circuit is arranged between the power supply monitoring module and each stamp hole interface, the low-voltage stabilizing circuit comprises a voltage stabilizing chip U8, a capacitor C10 and a capacitor C6, the VIN pin of the voltage stabilizing chip U8 and the first end of the capacitor C10 are respectively electrically connected with the OUT pin of the power electronic switch U9, the VOUT pin of the voltage stabilizing chip U8 and the first end of the capacitor C6 are respectively electrically connected with each stamp hole interface, and the GND pin of the voltage stabilizing chip U8, the second end of the capacitor C10 and the second end of the capacitor C6 are respectively grounded.

In a further technical scheme, a main control chip, a memory module, a storage module, a power supply module and a power supply monitoring module are respectively arranged on the top surface of the printed circuit board, the main control chip is arranged on the right lower portion of the top surface of the printed circuit board, the memory module is arranged on the left lower portion of the top surface of the printed circuit board, the storage module is arranged on the left upper portion of the top surface of the printed circuit board, and the power supply module and the power supply monitoring module are respectively arranged on the right upper portion of the top surface of the printed circuit board.

In a further technical scheme, the printed circuit board is provided with one hundred forty stamp hole interfaces, thirty-five stamp hole interfaces are arranged on each side of the printed circuit board at intervals, the stamp hole interfaces are provided with a POR_B reset interface for restarting, the POR_B reset interface is electrically connected with the main control chip, and the length and the width of the printed circuit board are 39mm.

By adopting the structure, compared with the prior art, the utility model has the following advantages: the power supply module is used for firstly powering up the main control chip and the power supply monitoring module, outputting a PMIC (pulse mode control) -NO-REQ signal to the power supply monitoring module after the main control chip is started normally, and supplying power to the memory module, the storage module and the peripheral connected through the stamp hole interface by the power supply monitoring module, so that the starting stability of the core board is improved; the voltage of the power supply module is monitored through the power supply monitoring chip U10, when the VDD pin of the power supply monitoring chip U10 is lower than the monitored voltage, the power electronic switch U9 is disabled to be disconnected, the core board is prevented from continuously running under the condition of unstable power supply, the running stability and reliability of the core board are improved, and the service life is prolonged; the back of the printed circuit board is not provided with any electronic component, so that the bottom plate does not need to be perforated to avoid, and the compatibility is improved; the structure is compact, the length and width of the printed circuit board are reduced to 39mm, the volume is small, and the application range is wide; through changing storage chip and memory chip in order to satisfy different demands, customization ability is strong, and the compatibility is high.

Drawings

The utility model will be further described with reference to the drawings and examples.

FIG. 1 is a schematic diagram of the structure of the present utility model;

FIG. 2 is a circuit block diagram of the present utility model;

FIG. 3 is a circuit diagram of a power monitoring module of the present utility model;

FIG. 4 is a circuit diagram of a memory module according to the present utility model;

FIG. 5 is a circuit diagram of a storage module of the present utility model;

FIG. 6 is a circuit diagram of a low voltage regulator circuit of the present utility model;

FIG. 7 is a pin signal circuit diagram of a printed wiring board of the present utility model;

fig. 8 is a flowchart of the operation of the present utility model.

In the figure:

001 printed circuit board, 011 stamp hole interface, 002 main control chip, 003 memory module, 004 storage module.

Detailed Description

The following are only preferred embodiments of the present utility model, and are not intended to limit the scope of the present utility model.

An i.mx6ull-based small volume postage stamp hole core board, as shown in fig. 1-8, comprising a printed wiring board, characterized by: the printed circuit board is provided with a main control chip, a memory module, a storage module, a power supply module and a power supply monitoring module; a plurality of stamp hole interfaces are arranged around the printed circuit board; the model of the main control chip is i.MX6ULL; the main control chip is respectively and electrically connected with the memory module, the storage module and the stamp hole interfaces; the power supply module is respectively and electrically connected with the main control chip and the power supply monitoring module, and the power supply monitoring module is respectively and electrically connected with the main control chip, the memory module, the storage module and the stamp hole interfaces; the power monitoring module comprises a power monitoring chip U10 and a power electronic switch U9, wherein a RESET pin of the power monitoring chip U10 is electrically connected with an EN pin of the power electronic switch U9, an MR pin of the power monitoring chip U10 is electrically connected with the main control chip, a VDD pin of the power monitoring chip U10 and an IN pin of the power electronic switch U9 are respectively electrically connected with the power supply module, a GND pin of the power monitoring chip U10 is grounded, an OUT pin of the power electronic switch U9 is respectively electrically connected with the memory module, the storage module and each stamp hole interface, and an ISET pin and the GND pin of the power electronic switch U9 are respectively grounded.

The traditional core board has low performance, poor compatibility and functionality, the core board with high performance can be damaged when running in an unstable power supply environment, the running is unstable, the starting stability is poor, the peripheral device is electrified before the main control chip is not normally started, the driving loading success rate is low, and the starting stability is poor; the voltage of the power supply module is monitored through the power supply monitoring chip U10, when the VDD pin of the power supply monitoring chip U10 is lower than the monitored voltage, the power electronic switch U9 is disabled to be disconnected, the core board is prevented from continuously running under the condition of unstable power supply, the running stability and reliability of the core board are improved, and the service life is prolonged; the back of the printed circuit board 001 is not provided with any electronic component, so that the bottom plate does not need to be perforated to avoid, and the compatibility is improved; the structure is compact, the length and width of the printed circuit board 001 are reduced to 39mm, the volume is small, and the application range is wide; through changing the memory chip 003 and storing chip 004 in order to satisfy different demands, customization ability is strong, and the compatibility is high.

Specifically, the power monitoring module is further provided with a resistor R79, a resistor R78, a resistor R77, a resistor R74, a capacitor C104 and a capacitor C33, wherein a first end of the resistor R79 is electrically connected between a RESET pin of the power monitoring chip U10 and an EN pin of the power electronic switch U9, a second end of the resistor R79 is grounded, the resistor R78 is serially connected between an MR pin of the power monitoring chip U10 and the main control chip, a first end of the resistor R77 is electrically connected with an ISET pin of the power electronic switch U9, a second end of the resistor R77 is grounded, a node A is arranged between an OUT pin of the power electronic switch U9 and each stamp hole interface, the memory module and the storage module are respectively electrically connected with the node A, the resistor R74 is serially connected between the node A and each stamp hole interface, the capacitor C104 is serially connected between a VDD pin and a GND pin of the power monitoring chip U10, and a second end of the capacitor C33 is electrically connected with the node A, and a second end of the capacitor C33 is grounded. After the main control chip 002 is powered on and normally started, the main control chip 002 gives a high level to the MR pin of the power monitoring chip U10 through a PMIC_NO_REQ signal, the VDD pin of the power monitoring chip U10 is higher than the monitoring voltage, the RESET pin of the power monitoring chip U10 is high level, the RESET signal is not triggered, the EN pin of the power electronic switch U9 is high level at this moment, the power electronic switch U9 is enabled, and the output DCDC_3V3 gives the internal power supply of the memory module 003 and the storage module 004 to the core board, and the peripheral power supply is connected through the stamp hole interface 011.

Specifically, the model of the power supply monitoring chip U10 is VP811REUS/T, the model of the power electronic switch U9 is MT9700, and the resistance value of the resistor R77 is 3.4K. The power electronic switch U9 also has a function of limiting current, i=6.8k (constant value)/R77, in this embodiment, i=6.8k/3.7k, and I is 2A, so as to prevent the excessive current, so that the core board is burnt, improving reliability and stability, and the structure is simple and the cost is low. When the VDD pin of the power supply monitoring chip U10 is lower than the monitoring voltage, the RESET pin of the power supply monitoring chip U10 is low level, a RESET signal is triggered, the EN pin of the power electronic switch U9 receives the RESET signal of the low level, at the moment, the power electronic switch U9 is disabled, the output of DCDC_3V3 is stopped, the power supply is disconnected, the core board is prevented from running under unstable power supply, the service life of the core board is prolonged, and the core board is prevented from being damaged.

Specifically, the memory module includes a memory voltage stabilizing circuit and at least one memory chip, the memory voltage stabilizing circuit is provided with a voltage stabilizing chip U6, the VIN pin of the voltage stabilizing chip U6 is electrically connected with the OUT pin of the power electronic switch U9, the EN pin of the voltage stabilizing chip U6 is electrically connected with the VIN pin of the voltage stabilizing chip U6, the LX pin and the FB pin of the voltage stabilizing chip U6 are respectively electrically connected with the memory chip, and the GND pin of the voltage stabilizing chip U6 is grounded. The memory chip is subjected to power supply protection through the memory voltage stabilizing circuit, so that the running stability of the memory chip is improved, the service life of the memory chip is prolonged, and the failure rate is reduced.

Specifically, as shown in fig. 4, the memory voltage stabilizing circuit is further provided with a capacitor C4, a capacitor C20, a capacitor C21, a resistor R3, a resistor R4, a resistor R5 and an inductor L1, wherein a first end of the capacitor C4 is electrically connected between the VIN pin of the voltage stabilizing chip U6 and the OUT pin of the power electronic switch U9, a second end of the capacitor C4 is grounded, a first end of the inductor L1 is electrically connected with the LX pin of the voltage stabilizing chip U6, a second end of the inductor L1 is electrically connected with the first end of the resistor R4, a second end of the resistor R4 is electrically connected with the memory chip, a first end of the capacitor C20 is electrically connected between the inductor L1 and the resistor R4, a first end of the resistor R3 is electrically connected between the capacitor C20 and the FB pin of the voltage stabilizing chip U6, a first end of the resistor R5 is electrically connected between the inductor L1 and the resistor R4, and a second end of the resistor R5 is electrically connected between the capacitor C21 and the resistor L1 and the resistor L4. DDR3L is selected as the memory chip, 3.3V voltage is converted into 1.35V voltage through the memory voltage stabilizing circuit, and the maximum output current is limited to 1000mA, so that the memory chip is stably powered, the reliability and the stability are improved, and the memory chip is ensured to operate under the high-efficiency power supply condition.

Specifically, the storage module comprises a storage voltage stabilizing circuit and at least one storage chip, the storage chip is a NAND chip or an eMMC chip, the memory voltage stabilizing circuit is provided with a voltage stabilizing chip U7, the VIN pin of the voltage stabilizing chip U7 is electrically connected with the OUT pin of the power electronic switch U9, the EN pin of the voltage stabilizing chip U7 is electrically connected with the VIN pin of the voltage stabilizing chip U7, the LX pin and the FB pin of the voltage stabilizing chip U7 are respectively electrically connected with the storage chip, and the GND pin of the voltage stabilizing chip U7 is grounded. The storage chip selects the NAND chip or the eMMC chip, improves customization ability, and application scope is extensive, carries out power supply protection to the storage chip through storing voltage stabilizing circuit, improves the operating stability of storage chip, prolongs the life of storage chip, reduces the fault rate.

Specifically, as shown in fig. 5, the storage voltage stabilizing circuit is further provided with a capacitor C5, a capacitor C29, a capacitor C28, a resistor R9, a resistor R8, a resistor R11 and an inductor L2, wherein a first end of the capacitor C5 is electrically connected between the VIN pin of the voltage stabilizing chip U7 and the OUT pin of the power electronic switch U9, a second end of the capacitor C5 is grounded, a first end of the inductor L2 is electrically connected with the LX pin of the voltage stabilizing chip U7, a second end of the inductor L2 is electrically connected with the first end of the resistor R8, a second end of the resistor R8 is electrically connected with the storage chip, a first end of the capacitor C29 is electrically connected with the FB pin of the voltage stabilizing chip U7, a second end of the resistor R9 is electrically connected between the capacitor C29 and the FB pin of the voltage stabilizing chip U7, a second end of the resistor R9 is electrically connected between the inductor L2 and the resistor R8, a first end of the resistor R11 is electrically connected between the capacitor C29 and the FB pin of the voltage stabilizing chip U7, and a second end of the resistor R11 is electrically connected between the capacitor C28 and the resistor L2 and the resistor R8. The storage voltage stabilizing circuit converts 3.3V voltage into 1.2V voltage, and limits the maximum output current to 1000mA, so that the storage chip is stably powered, the reliability and stability are improved, and the storage chip is ensured to operate under the high-efficiency power supply condition.

Specifically, a low-voltage stabilizing circuit is arranged between the power supply monitoring module and each stamp hole interface, the low-voltage stabilizing circuit comprises a voltage stabilizing chip U8, a capacitor C10 and a capacitor C6, the VIN pin of the voltage stabilizing chip U8 and the first end of the capacitor C10 are respectively electrically connected with the OUT pin of the power electronic switch U9, the VOUT pin of the voltage stabilizing chip U8 and the first end of the capacitor C6 are respectively electrically connected with each stamp hole interface, and the GND pin of the voltage stabilizing chip U8, the second end of the capacitor C10 and the second end of the capacitor C6 are respectively grounded. Other components and parts and peripheral hardware power supply in the core board through the low-voltage stabilizing circuit, the low-voltage stabilizing circuit converts 3.3V voltage into 1.8V voltage to satisfy different voltage demands, improve application scope, increase compatibility.

Specifically, main control chip, memory module, storage module, power module and power monitoring module set up in the top surface of printed wiring board respectively, and main control chip sets up in the lower right part of printed wiring board top surface, and memory module sets up in the lower left part of printed wiring board top surface, and storage module sets up in the upper left part of printed wiring board top surface, and power module and power monitoring module set up in the upper right part of printed wiring board top surface respectively. The main control chip, the memory module, the storage module, the power supply module and the power supply monitoring module are respectively arranged on the top surface of the printed circuit board, no electronic component exists on the back surface of the printed circuit board, holes are not needed to be formed on the bottom plate to avoid the electronic component, the suitability of the core board is improved, the bottom plate is not needed to be customized, the product marketing speed is accelerated, and the structure is compact and the size is small.

Specifically, as shown in fig. 7, the printed circuit board is provided with one hundred forty stamp hole interfaces, thirty-five stamp hole interfaces are arranged on each side of the printed circuit board at intervals, the stamp hole interfaces are provided with a por_b reset interface for restarting, the por_b reset interface is electrically connected with the main control chip, and the length and the width of the printed circuit board are 39mm or 39mm. One hundred forty stamp hole interfaces are convenient to connect with the bottom plate, wherein 107 GPIO are led out, one differential clock is set, 2 USB special ports are provided, 2 power control ports are provided, abundant stamp hole interfaces are provided, expansibility is improved, reset ICs on the bottom plate are connected through POR_B reset interfaces, the reset ICs on the bottom plate are used for forcedly restarting the core plate, so that the phenomenon of dead halt and the like is solved, fault discharge speed is improved, meanwhile, the problem of restarting a system under a vibration occasion is solved, and running stability and reliability are further improved.

As shown in fig. 8, the workflow of the present utility model is: the external power supply is used for powering ON the power supply through the stamp hole interface, the power supply outputs a VCC_SYS signal to the main control chip 001 and the power supply monitoring module, the main control chip 001 is electrified and started, the PMIC_ON_REQ signal is output to the power supply monitoring chip U10 after the main control chip 001 is normally started, the power supply monitoring chip U10 receives the VCC_SYS signal and the PMIC_ON_REQ signal and judges whether the voltage of the VCC_SYS signal is lower than the monitoring voltage, and when the voltage of the VCC_SYS signal is lower than the monitoring voltage, the power electronic switch U9 is disabled, the output of the DCDC_3V3 signal is stopped, and the power supply is disconnected; when the voltage of the VCC_SYS signal is higher than the monitoring voltage, the power electronic switch U9 is enabled, and outputs a DCDC_3V3 signal to the memory module 003 and the storage module 004 for supplying power to the inside of the core board, and peripheral power is supplied through the stamp hole interface 011; the main control chip 001 enters different modes according to the level of a starting pin, when the external SD card is selected to be started, the core board loads an image file in the SD card, the Linux system is started, a bottom plate peripheral driver is loaded, and then a user service program is operated; when the storage chip is selected to be started, the core board loads the mirror image file in the storage chip, the Linux system is started, the peripheral driver of the bottom plate is loaded, and then the user service program is operated; when the image is selected to be burned, the image file is burned into the storage chip through the USB connected with the outside.

The foregoing is merely exemplary of the present utility model, and those skilled in the art should not be considered as limiting the utility model, since modifications may be made in the specific embodiments and application scope of the utility model in light of the teachings of the present utility model.

Claims

1. A small volume postage stamp hole core board based on i.mx6ull comprising a printed wiring board (001), characterized in that: the printed circuit board (001) is provided with a main control chip (002), a memory module (003), a storage module (004), a power supply module and a power supply monitoring module;

a plurality of stamp hole interfaces (011) are arranged on the periphery of the printed circuit board (001);

the model of the main control chip (002) is i.MX6ULL;

The main control chip (002) is respectively and electrically connected with the memory module (003), the storage module (004) and each stamp hole interface (011);

the power supply module is respectively and electrically connected with the main control chip (002) and the power supply monitoring module,

The power supply monitoring module is respectively and electrically connected with the main control chip (002), the memory module (003), the storage module (004) and each stamp hole interface (011);

The RESET pin of the power monitoring chip U10 is electrically connected with the EN pin of the power electronic switch U9, the MR pin of the power monitoring chip U10 is electrically connected with the main control chip (002), the VDD pin of the power monitoring chip U10 and the IN pin of the power electronic switch U9 are respectively electrically connected with the power supply module, the GND pin of the power monitoring chip U10 is grounded,

The OUT pin of the power electronic switch U9 is respectively and electrically connected with the memory module (003), the storage module (004) and each stamp hole interface (011), and the ISET pin and the GND pin of the power electronic switch U9 are respectively grounded.

2. A small volume postage stamp aperture core board based on i.mx6ull as claimed in claim 1 wherein: the power supply monitoring module is further provided with a resistor R79, a resistor R78, a resistor R77, a resistor R74, a capacitor C104 and a capacitor C33, wherein a first end of the resistor R79 is electrically connected between a RESET pin of the power supply monitoring chip U10 and an EN pin of the power electronic switch U9, a second end of the resistor R79 is grounded, the resistor R78 is serially connected between an MR pin of the power supply monitoring chip U10 and the main control chip (002), a first end of the resistor R77 is electrically connected with an ISET pin of the power electronic switch U9, a second end of the resistor R77 is grounded, a node A is arranged between an OUT pin of the power electronic switch U9 and each stamp hole interface (011), the memory module (003) and the storage module (004) are respectively electrically connected with the node A, the resistor R74 is serially connected between the node A and each stamp hole interface (011), the capacitor C104 is serially connected between a pin of the power supply monitoring chip U10 and the GND pin, and a first end of the capacitor C33 is electrically connected with the node A, and a second end of the capacitor C33 is grounded.

3. A small volume postage stamp aperture core board based on i.mx6ull as claimed in claim 2 wherein: the model of the power supply monitoring chip U10 is VP811REUS/T, the model of the power electronic switch U9 is MT9700, and the resistance value of the resistor R77 is 3.4K.

4. A small volume postage stamp aperture core board based on i.mx6ull as claimed in claim 1 wherein: the memory module (003) comprises a memory voltage stabilizing circuit and at least one memory chip, wherein the memory voltage stabilizing circuit is provided with a voltage stabilizing chip U6, the VIN pin of the voltage stabilizing chip U6 is electrically connected with the OUT pin of the power electronic switch U9, the EN pin of the voltage stabilizing chip U6 is electrically connected with the VIN pin of the voltage stabilizing chip U6, the LX pin and the FB pin of the voltage stabilizing chip U6 are respectively electrically connected with the memory chip, and the GND pin of the voltage stabilizing chip U6 is grounded.

5. A small volume postage stamp aperture core board based on i.mx6ull as claimed in claim 4, wherein: the memory voltage stabilizing circuit is also provided with a capacitor C4, a capacitor C20, a capacitor C21, a resistor R3, a resistor R4, a resistor R5 and an inductor L1,

6. A small volume postage stamp aperture core board based on i.mx6ull as claimed in claim 1 wherein: the storage module (004) comprises a storage voltage stabilizing circuit and at least one storage chip, the storage chip is selected from a NAND chip or an eMMC chip,

7. A small volume postage stamp aperture core board based on i.mx6ull as claimed in claim 6, wherein: the storage voltage stabilizing circuit is also provided with a capacitor C5, a capacitor C29, a capacitor C28, a resistor R9, a resistor R8, a resistor R11 and an inductor L2,

8. A small volume postage stamp aperture core board based on i.mx6ull as claimed in claim 1 wherein: the power supply monitoring module is provided with a low-voltage stabilizing circuit between each stamp hole interface (011), the low-voltage stabilizing circuit comprises a voltage stabilizing chip U8, a capacitor C10 and a capacitor C6, the VIN pin of the voltage stabilizing chip U8 and the first end of the capacitor C10 are respectively electrically connected with the OUT pin of the power electronic switch U9, the VOUT pin of the voltage stabilizing chip U8 and the first end of the capacitor C6 are respectively electrically connected with each stamp hole interface (011), and the GND pin of the voltage stabilizing chip U8, the second end of the capacitor C10 and the second end of the capacitor C6 are respectively grounded.

9. A small volume postage stamp aperture core board based on i.mx6ull as claimed in any one of claims 1 to 8 wherein: the main control chip (002) the memory module (003) the storage module (004) the power module with power monitoring module set up respectively in the top surface of printed wiring board (001), main control chip (002) set up in the lower right part of printed wiring board (001) top surface, and memory module (003) set up in the lower left part of printed wiring board (001) top surface, and storage module (004) set up in the upper left part of printed wiring board (001) top surface, and power module and power monitoring module set up respectively in the upper right part of printed wiring board (001) top surface.

10. A small volume postage stamp aperture core board based on i.mx6ull as claimed in claim 9 wherein: the printed circuit board (001) is provided with one hundred forty stamp hole interfaces (011), thirty-five stamp hole interfaces (011) are arranged on each side of the printed circuit board (001) at intervals, the stamp hole interfaces (011) are provided with a reset interface of POR_B for restarting, the reset interface of POR_B is electrically connected with the main control chip (002), and the length and width of the printed circuit board (001) are 39 x 39mm.