CN221177996U - Circuit board and electronic equipment - Google Patents

Abstract

The application provides a circuit board and electronic equipment, the circuit board includes: a substrate having a first surface and a second surface disposed opposite each other; at least one connecting area is arranged on the first surface and used for connecting a chip; the substrate is provided with a plurality of functional layers which are sequentially laminated, and the functional layers at least comprise: the first functional layer, the second functional layer and the first power supply layer; the first functional layer is provided with the first surface, the second functional layer is provided with the second surface, the first functional layer is used for being connected with the chip, and the first power supply layer is arranged close to the first functional layer and supplies power for at least the chip.

Description

Circuit board and electronic equipment

Technical Field

The present application relates to the field of electronic devices, and in particular, to a circuit board and an electronic device.

Background

The circuit board is a core component in an electronic device (such as a notebook computer) and is not only a support for electronic components, but also a carrier for electrical interconnection of the electronic components.

Currently, to accommodate miniaturization of electronic devices, circuit boards and chips connected to circuit boards are simultaneously reduced in size. However, as the size of the circuit board and the chips attached to the circuit board becomes smaller, the transmission rate of the circuit board decreases, which is contrary to the high transmission rate requirements of electronic devices.

Disclosure of utility model

In view of the above, the present application provides a circuit board and an electronic device, which have the following technical schemes:

In a first aspect, an embodiment of the present application provides a circuit board, including: a substrate having a first surface and a second surface disposed opposite each other; at least one connecting area is arranged on the first surface and used for connecting a chip; the substrate is provided with a plurality of functional layers which are sequentially laminated, and the functional layers at least comprise: the first functional layer, the second functional layer and the first power supply layer; the first functional layer is provided with the first surface, the second functional layer is provided with the second surface, the first functional layer is used for being connected with the chip, and the first power supply layer is arranged close to the first functional layer and supplies power for at least the chip.

In some embodiments, a signal layer is disposed between the first functional layer and the second functional layer; the signal layer includes: a first signal layer and a second signal layer; the first signal layer is provided with a first circuit, and the first circuit is provided with a plurality of first line segments; the second signal layer is provided with a second circuit, and the second circuit is provided with a plurality of second line segments; the plurality of line segments of the first line are at least partially connected with the plurality of second line segments of the second line.

In some embodiments, the first signal layer is disposed adjacent to the first functional layer; the second signal layer is disposed adjacent to the second functional layer.

In some embodiments, the first signal layer and the second signal layer are disposed immediately adjacent; or a first grounding layer is arranged between the first signal layer and the second signal layer, a first via hole is formed in the first grounding layer, and a conductive material is arranged in the first via hole.

In some embodiments, the first power supply layer is disposed between the first functional layer and the first signal layer; the first power supply layer is connected with the first functional layer; the first power supply layer is connected with the first signal layer through the second grounding layer.

In some embodiments, the second ground layer is provided with a second via, and a conductive material is disposed in the second via.

In some embodiments, the plurality of functional layers further comprises: a second power supply layer; the second power supply layer is the second functional layer, a third grounding layer is arranged between the second power supply layer and the second signal layer, a third via hole is formed in the third grounding layer, and a conductive material is arranged in the third via hole.

In some embodiments, the thickness of the plurality of functional layers is not exactly uniform.

In some embodiments, the number of functional layers is less than 10.

In a second aspect, an embodiment of the present application provides an electronic device, including: a circuit board as claimed in any one of the preceding claims.

The foregoing description is only an overview of the present application, and is intended to provide a better understanding of the present application, as it is embodied in the following description, with reference to the preferred embodiments of the present application and the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a circuit board according to an embodiment of the application;

Fig. 2 is a schematic diagram of a first functional layer of a circuit board according to an embodiment of the application.

Reference numerals illustrate:

10. A substrate; 101. a first surface; 102. a second surface; 103. a chip; 11. a first functional layer; 12. a second functional layer; 13. a first power supply layer; 14. a first signal layer; 15. a second signal layer; 16. a first ground layer; 17. a second ground layer; 18. and a third ground layer.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, based on the embodiments of the application, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the application. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application.

Embodiments of the application and features of the embodiments may be combined with each other without conflict. The application will be described in detail below with reference to the drawings in connection with embodiments.

First aspect

An embodiment of the present application provides a circuit board, as shown in fig. 1 and 2, including: a substrate 10, the substrate 10 having a first surface 101 and a second surface 102 disposed opposite to each other; at least one connection region is disposed on the first surface 101, and the connection region is used for connecting the chip 103; the substrate 10 has a plurality of functional layers stacked in order, and the plurality of functional layers includes at least: a first functional layer 11, a second functional layer 12, and a first power supply layer 13; the first functional layer 11 has a first surface 101 and the second functional layer 12 has a second surface 102, the first functional layer 11 being for connection to a chip 103, the first power supply layer 13 being arranged adjacent to the first functional layer 11 and supplying at least the chip 103 with power.

Specifically, the substrate 10 has a first surface 101 and a second surface 102 disposed opposite to each other, for example: referring to fig. 1, the substrate 10 has an upper surface 101 and a lower surface 102 disposed opposite to each other. At least one connection region is disposed on the first surface 101, where the connection region is used to connect the chips 103, that is, one connection region may be disposed on the first surface 101, or a plurality of connection regions may be disposed on the first surface, and one connection region may be connected to one chip 103, or a plurality of chips 103 may be connected to one connection region. The chip 103 can communicate with the wires provided on the substrate 10, that is, the chip 103 connected to the first surface 101 can be connected with the wires provided in the substrate 10, so as to realize communication between the chip 103 and the wires, for example: the chip 103 connected to the first surface 101 is connected to a first line provided on the first signal layer 14 hereinafter so that the chip 103 connected to the first surface 101 can communicate with the first line provided on the first signal layer 14.

The first surface 101 is provided with three connection regions, namely a first connection region, a second connection region and a third connection region, wherein the first connection region and the second connection region have the same shape and size, the third connection region has a similar shape to the first connection region, and the third connection region has a size larger than that of the first connection region. Wherein the first connection region, the second connection region and the third connection region are respectively used for connecting the chip 103. Here, the chips connected to the first and second connection regions may be Double Data Rate synchronous dynamic random access memory (DDR) chips, and the chip connected to the third connection region may be a central processing unit (CPU, central Processing Unit) chip.

The substrate 10 has a plurality of functional layers stacked in order, and the plurality of functional layers includes at least: the first functional layer 11, the second functional layer 12, and the first power supply layer 13, that is, the substrate 10 includes: the plurality of functional layers are stacked in this order in a predetermined order, and among the plurality of functional layers of the substrate 10, other functional layers may be provided in addition to the first functional layer 11, the second functional layer 12, and the first power supply layer 13. Of the plurality of functional layers in the substrate 10, any two functional layers may have the same or different roles, for example: referring to fig. 1 and 2, the first functional layer 11 is connected to a plurality of chips 103, a ground structure is provided in the plurality of chips 103, and the second functional layer 12 is used to supply power to the substrate 10.

The first functional layer 11 has a first surface 101, the second functional layer 12 has a second surface 102, and the first functional layer 11 is used for connecting with the chip 103, so that the first functional layer 11 and the second functional layer 12 are two functional layers at two ends on the substrate 10. The first power supply layer 13 is disposed adjacent to the first functional layer 11 and supplies power to at least the chip 103, that is, the distance from the first power supply layer 13 to the first functional layer 11 is smaller than the distance from the first power supply layer 13 to the second functional layer 12 in the plurality of functional layers, and the first power supply layer 13 can supply power to the chip 103 connected to the first functional layer 11, however, the first power supply layer 13 can also supply power to other functional layers requiring electric energy.

In some embodiments, referring to fig. 1 and 2, a circuit board includes: a substrate 10, the substrate 10 having a first surface 101 and a second surface 102 disposed opposite to each other; the first surface 101 is provided with a plurality of connection areas, and the connection areas are respectively connected with the chip 103. The substrate 10 includes a first functional layer 11, a first power supply layer 13, a second ground layer 17, a first signal layer 14, a first ground layer 16, a second signal layer 15, a third ground layer 18, and a second functional layer 12 stacked from top to bottom; the first functional layer 11 is provided with a plurality of connection areas, and each connection area is connected with a chip 103; the first power supply layer 13 is capable of supplying power to the chip 103; the second ground layer 17 isolates the first power supply layer 13 from the first signal layer 14 to prevent mutual interference of signals between the first power supply layer 13 and the first signal layer 14; the first signal layer 14 is connected to the chip 103 on the first functional layer 11 to enable communication between the first signal layer 14 and the chip 103 on the first functional layer 11; the first ground layer 16 isolates the first signal layer 14 and the second signal layer 15 to prevent mutual interference of signals between the first signal layer 14 and the second signal layer 15; the second signal layer 15 may be connected to the first signal layer 14 to enable the second signal layer 15 and the first signal layer 14 to communicate with each other, or may be connected to the chip 103 on the first functional layer 11 to enable the second signal layer 15 and the chip 103 on the first functional layer 11 to communicate with each other; the third ground layer 18 isolates the second signal layer 15 from the second functional layer 12 to prevent mutual interference of signals between the second signal layer 15 and the second functional layer 12, and the second functional layer 12 is a second power supply layer to be able to supply power to any one of the functional layers on the substrate 10. And each grounding layer is provided with a via hole, and conductive materials are arranged in the via holes so as to electrically connect the two functional layers on two sides of the grounding layer through the conductive materials in the via holes.

When a plurality of functional layers are disposed between the first functional layer 11 and the first power supply layer 13 so that the first power supply layer 13 is far away from the first functional layer 11, vias need to be formed on the functional layers between the first power supply layer 13 and the first functional layer 11 to enable the first power supply layer 13 and the first functional layer 11 to be electrically connected through connection structures in the vias, and signal transmission from the first power supply layer 13 to the first functional layer 11 is delayed due to the arrangement of the vias on each functional layer, so that the transmission rate of the circuit board is low, and the thickness dimension of the circuit board is large due to the plurality of functional layers between the first power supply layer 13 and the first functional layer 11. In this embodiment, the first power supply layer 13 is disposed between the first functional layer 11 and the second functional layer 12 opposite to each other on the circuit board, and the first power supply layer 13 is disposed adjacent to the first functional layer 11 and can supply power to the chip 103 connected to the first functional layer 11, so that the distance from the first power supply layer 13 to the first functional layer 11 is short, so that the number of vias in the board thickness direction can be reduced, and the transmission speed from the first power supply layer 13 to the chip 103 on the first functional layer 11 is high, and the transmission speed of the circuit board can be ensured; meanwhile, since the first power supply layer 13 is disposed adjacent to the first functional layer 11, the number of functional layers between the first power supply layer 13 and the first functional layer 11 can be reduced, so that the thickness dimension of the circuit board can be reduced.

In some embodiments, as shown with reference to fig. 1, a signal layer is disposed between the first functional layer 11 and the second functional layer 12; the signal layer includes: a first signal layer 14 and a second signal layer 15; the first signal layer 14 is provided with a first line, and the first line is provided with a plurality of first line segments; the second signal layer 15 is provided with a second line, and the second line is provided with a plurality of second line segments; the plurality of line segments of the first line are at least partially connected with the plurality of second line segments of the second line.

Specifically, the signal layers are disposed between the first functional layer 11 and the second functional layer 12, the signal layers are for setting lines, and the number of the signal layers between the first functional layer 11 and the second functional layer 12 may be one or plural, and when the number of the signal layers between the first functional layer 11 and the second functional layer 12 is plural, the plural signal layers may be disposed next to each other, or may be a ground layer disposed between two adjacent signal layers and electrically connected to the two adjacent signal layers through a connection structure in the ground layer, so as to reduce the problem of signal interference between the two adjacent signal layers.

The signal layer includes: the first signal layer 14 and the second signal layer 15, the first signal layer 14 is provided with a first line, the first line has a plurality of first line segments, the second signal layer 15 is provided with a second line, the second line has a plurality of second line segments, and the plurality of line segments of the first line are at least partially connected with the plurality of second line segments of the second line, in other words, the first signal layer 14 and the second signal layer 15 are electrically connected with each other, so as to enable mutual communication between the first signal layer 14 and the second signal layer 15. The density of the first line segments on the first signal layer 14 and the density of the second line segments on the second signal layer 15 may be the same or different; the wire diameter of the first wire segment on the first signal layer 14 and the wire diameter of the second wire segment on the second signal layer 15 may or may not be identical; the thickness of the first signal layer 14 may or may not be identical to the thickness of the second signal layer 15.

In some embodiments, referring to fig. 1, a first signal layer 14 and a second signal layer 15 are disposed between the first functional layer 11 and the second functional layer 12, the first signal layer 14 is disposed adjacent to the first functional layer 11, and the second signal layer 15 is disposed adjacent to the second functional layer 12. The surface of the first signal layer 14 near the first functional layer 11 is provided with a first power supply structure (such as a VDDQ power supply structure, a 1.8V power supply structure or a VDD power supply structure), and the surface of the first signal layer 14 near the second functional layer 12 is provided with a first line for transmitting signals, where the first power supply structure can supply power to the first line. A second power supply structure (such as a VDDQ power supply structure, a 1.8V power supply structure, or a VDD power supply structure) is disposed on a surface of the second signal layer 15 near the first functional layer 11, and a second circuit for transmitting signals is disposed on a surface of the second signal layer 15 near the second functional layer 12, where the second power supply structure supplies power to the second circuit. While the power of the first and second power supply structures may come from the second functional layer 12.

Here, the density of the first wire segments on the first signal layer 14 and the density of the second wire segments on the second signal layer 15 may be set to be larger, so that a larger number of first wire segments can be set on the first signal layer 14 and a larger number of second wire segments can be set on the second signal layer 15. In this way, the trace segments originally disposed on three or even four signal layers can be integrated on the first signal layer 14 and the second signal layer 15, so that the number of signal layers in the circuit board can be further reduced, and the thickness of the circuit board can be further reduced.

In some embodiments, referring to fig. 1, the first signal layer 14 is disposed adjacent to the first functional layer 11; the second signal layer 15 is arranged adjacent to the second functional layer 12. That is, the first functional layer 11, the first signal layer 14, the second signal layer 15, and the second functional layer 12 are disposed in this order, so that the first signal layer 14 can communicate with the external structure from the side close to the first functional layer 11, and the second signal layer 15 can communicate with the external structure from the side close to the second functional layer 12.

In other embodiments, the first signal layer 14 is disposed adjacent to the second functional layer 12 and the second signal layer 15 is disposed adjacent to the first functional layer 11.

Here, the specific arrangement may be selected in either of the above two embodiments according to the specific line arrangement on the first signal layer 14 and the second signal layer 15 and the position of the external structure that needs to communicate with the first signal layer 14 and the second signal layer 15.

In some embodiments, the first signal layer 14 and the second signal layer 15 are disposed immediately adjacent; or referring to fig. 1, a first ground layer 16 is disposed between the first signal layer 14 and the second signal layer 15, and a first via hole is formed in the first ground layer 16, and a conductive material is disposed in the first via hole.

When the first signal layer 14 and the second signal layer 15 are disposed next to each other, the first line segment on the first signal layer 14 and the second line segment on the second signal layer 15 can be directly connected, and since the distance between the first signal layer 14 and the second signal layer 15 is short, the signal delay can be reduced to thereby increase the rate of signal transmission between the first signal layer 14 and the second signal layer 15, and at the same time, the first signal layer 14 and the second signal layer 15 are disposed next to each other to reduce the thickness of the circuit board. When the first ground layer 16 is disposed between the first signal layer 14 and the second signal layer 15, the first ground layer 16 is provided with a first via hole, a conductive material is disposed in the first via hole, and the first signal layer 14 and the second signal layer 15 are connected by the conductive material in the first via hole, so as to realize signal transmission between the first signal layer 14 and the second signal layer 15, and the arrangement of the first ground layer 16 can reduce mutual interference of signals between the first signal layer 14 and the second signal layer 15. In this way, any setting mode of the two embodiments in this embodiment can be selected according to the actual setting requirement to perform setting.

In some embodiments, referring to fig. 1, a first power supply layer 13 is disposed between the first functional layer 11 and the first signal layer 14; the first power supply layer 13 is connected with the first functional layer 11; the first power supply layer 13 is connected to the first signal layer 14 through the second ground layer 17. That is, the first functional layer 11, the first power supply layer 13, the second ground layer 17, and the first signal layer 14 are stacked in this order.

In this embodiment, the first power supply layer 13 and the first functional layer 11 are closely connected, so that no other functional layer exists between the first power supply layer 13 and the first functional layer 11, so that the thickness dimension of the circuit board is small, and no through hole exists between the first power supply layer 13 and the first functional layer 11, so that the transmission speed from the first power supply layer 13 to the chip 103 on the first functional layer 11 is high, and the transmission speed of the circuit board can be ensured. In addition, the first power supply layer 13 is located between the first functional layer 11 and the first signal layer 14, so that the first signal layer 14 does not need to be provided with a via hole for connecting the first power supply layer 13 and the first functional layer 11, so that more space is provided on the first signal layer 14 to provide first wire segments and more space is provided to provide isolation spaces between different first wire segments, thereby reducing the number of signal layers in the circuit board and reducing signal interference between different first wire segments on the first signal layer 14.

In some embodiments, referring to fig. 1, the second ground layer 17 is provided with a second via, and a conductive material is disposed in the second via. Here, the conductive material in the second via hole can prevent mutual interference of signals between the first power supply layer 13 and the first signal layer 14.

In some embodiments, referring to fig. 1, the plurality of functional layers may further include: a second power supply layer; the second power supply layer is the second functional layer 12, is provided with third ground layer 18 between second power supply layer and the second signal layer 15, and third via hole has been seted up to third ground layer 18, is provided with conductive material in the third via hole.

Specifically, the second power supply layer described above can supply power to any of the plurality of functional layers of the substrate 10. The third ground layer 18 can isolate the second power supply layer from the second signal layer 15 to prevent mutual interference of signals of the second power supply layer and the second signal layer 15, and the conductive material in the third via hole can connect the second power supply layer and the second signal layer 15 to realize mutual transmission of signals between the second power supply layer and the second signal layer 15.

In some embodiments, the thickness of the plurality of functional layers is not exactly the same as shown with reference to fig. 1. The thickness of each functional layer may be specifically set according to the specific situation. Such as: when the first power supply layer 13 supplies power to only the chip 103 on the first functional layer 11 and the second power supply layer supplies power to other structures except the first functional layer 11 among the plurality of functional layers on the substrate 10, the thickness of the second power supply layer may be greater than that of the first power supply layer 13; and, for example: when the wire diameter of the first wire section on the first signal layer 14 is larger than the wire diameter of the second wire section on the second signal layer 15, the thickness of the first signal layer 14 is larger than the thickness of the second signal layer 15; for another example: since the first signal layer 14 is provided with the first circuit and the second signal layer 15 is provided with the second circuit, the thickness of the first signal layer 14 and the thickness of the second signal layer 15 are both greater than the thicknesses of other functional layers on the substrate 10.

In some embodiments, the number of functional layers is less than 10. Such as: referring to fig. 1, the first power supply layer 13 is disposed next to the first functional layer 11, so that there is no need to dispose a via hole on the first signal layer 14 to connect the first power supply layer 13 and the first functional layer 11, so that there is more space on the first signal layer 14 to dispose the first wire segments and more space to have isolation spaces between different first wire segments, thereby all circuits required by the circuit board can be disposed on the first signal layer 14 and the second signal layer 15, and thus, at least one signal layer and a ground layer isolating the signal layer are reduced, so that the number of the functional layers is 8.

Second aspect

The embodiment of the application provides electronic equipment, which comprises: a circuit board as in any above.

Specifically, the electronic device may be a notebook computer, an integrated computer, or other electronic devices. The second surface 102 of the circuit board may be provided with connection pins that are capable of connecting with a motherboard within the electronic device such that the circuit board and the motherboard form a collective chip.

It should be noted that, the circuit board in the electronic device provided by the embodiment of the present application is similar to the description of the circuit board embodiment described in the foregoing description, and has similar beneficial effects as the circuit board embodiment described in the foregoing description. For technical details not disclosed in the embodiments of the electronic device of the present application, please refer to the description of the embodiments of the circuit board of the present application, and the details are not repeated here.

In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.

In addition, in the description of the present application, it should be understood that the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", etc. indicate orientations or positional relationships based on the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.

Furthermore, in the present application, unless explicitly specified and limited otherwise, the terms "connected," "coupled," and the like are to be construed broadly and may be, for example, mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, unless otherwise specifically defined, the meaning of the terms in this disclosure is to be understood by those of ordinary skill in the art.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims (10)

1. A circuit board, comprising: a substrate having a first surface and a second surface disposed opposite each other; at least one connecting area is arranged on the first surface and used for connecting a chip;

The substrate is provided with a plurality of functional layers which are sequentially laminated, and the functional layers at least comprise: the first functional layer, the second functional layer and the first power supply layer;

The first functional layer is provided with the first surface, the second functional layer is provided with the second surface, the first functional layer is used for being connected with the chip, and the first power supply layer is arranged close to the first functional layer and supplies power for at least the chip.

2. The circuit board of claim 1, wherein the circuit board is configured to,

A signal layer is arranged between the first functional layer and the second functional layer;

the signal layer includes: a first signal layer and a second signal layer;

The first signal layer is provided with a first circuit, and the first circuit is provided with a plurality of first line segments;

the second signal layer is provided with a second circuit, and the second circuit is provided with a plurality of second line segments;

the plurality of line segments of the first line are at least partially connected with the plurality of second line segments of the second line.

3. The circuit board of claim 2, wherein the circuit board is configured to,

The first signal layer is arranged adjacent to the first functional layer;

The second signal layer is disposed adjacent to the second functional layer.

4. The circuit board of claim 2, wherein the circuit board is configured to,

The first signal layer and the second signal layer are disposed next to each other; or alternatively

A first grounding layer is arranged between the first signal layer and the second signal layer, a first via hole is formed in the first grounding layer, and a conductive material is arranged in the first via hole.

5. The circuit board of claim 3, wherein,

The first power supply layer is arranged between the first functional layer and the first signal layer;

the first power supply layer is connected with the first functional layer;

The first power supply layer is connected with the first signal layer through the second grounding layer.

6. The circuit board of claim 5, wherein the circuit board is further configured to,

The second ground layer is provided with a second via hole, and a conductive material is arranged in the second via hole.

7. The circuit board of claim 3, wherein,

The plurality of functional layers further includes: a second power supply layer;

The second power supply layer is the second functional layer, a third grounding layer is arranged between the second power supply layer and the second signal layer, a third via hole is formed in the third grounding layer, and a conductive material is arranged in the third via hole.

8. The circuit board of claim 1, wherein the circuit board is configured to,

The thickness of the plurality of functional layers is not entirely uniform.

9. The circuit board of claim 1, wherein the circuit board is configured to,

The number of functional layers is less than 10.

10. An electronic device, comprising:

The circuit board of any one of claims 1 to 9.