CN221100928U - Aging experiment device for generating multiple groups of interface signals - Google Patents
Aging experiment device for generating multiple groups of interface signals Download PDFInfo
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- CN221100928U CN221100928U CN202322941772.2U CN202322941772U CN221100928U CN 221100928 U CN221100928 U CN 221100928U CN 202322941772 U CN202322941772 U CN 202322941772U CN 221100928 U CN221100928 U CN 221100928U
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Abstract
The application discloses an aging experiment device for generating a plurality of groups of interface signals, which is used for inputting control signals to a plurality of test assemblies and comprises a box body, a control board, a control module and a signal switching module, wherein: the control module and the signal switching module are arranged on the control board; the control panel is arranged in the box body; the input end of the control module is connected with the PC end; the output end of the control module is connected with the input end of the signal switching module; the number of the input ends of the signal switching module is at least two; the number of the output ends of the signal transfer module is four times of the number of the input ends of the signal transfer module; the output end of the signal switching module is connected with the input ends of the test assemblies. The control signal is output to the plurality of test assemblies through the signal switching module, so that the effect of ageing the plurality of test assemblies at one time with low cost is achieved.
Description
Technical Field
The utility model belongs to the technical field of communication test, and particularly relates to an aging experiment device for generating multiple groups of interface signals.
Background
During the aging process of a communication component, some process requirements require that multiple components be aged simultaneously. The control box used at present only controls a single component by a single interface, if a plurality of components are controlled simultaneously, a plurality of control boxes are needed, so that the cost is increased, the components can not be controlled simultaneously, and the aging requirement can not be met. There are also larger burn-in platforms, which, although more automated, are more bulky and costly, and do not meet the test requirements for miniaturization and low cost.
Disclosure of Invention
In order to solve the problems in the related art, the application provides an aging test device for generating multiple groups of interface signals, which can control multiple test components simultaneously and reduce equipment cost.
The technical proposal is as follows:
An ageing experiment device for generating a plurality of groups of interface signals is used for inputting control signals to a plurality of test assemblies, and comprises a box body, a control board, a control module and a signal switching module, wherein: the control module and the signal switching module are arranged on the control board; the control panel is arranged in the box body; the input end of the control module is connected with the PC end; the output end of the control module is connected with the input end of the signal switching module; the number of the input ends of the signal switching module is at least two groups; the number of the output ends of the signal transfer module is four times of the number of the input ends of the signal transfer module; the output end of the signal switching module is connected with the input ends of the test assemblies.
The control signal is output to the plurality of test assemblies through the signal switching module, so that the effect of ageing the plurality of test assemblies at one time with low cost is achieved.
Further, the control module comprises a power supply module, a clock module, a serial port module, an FPGA main controller and a level conversion module, wherein: the output ends of the power supply module, the clock module and the serial port module are connected with the input end of the FPGA main controller; the input end of the serial port module is connected with the PC end; the output end of the FPGA main controller is connected with the input end of the level conversion module; the number of the output ends of the level conversion module is four groups.
The FPGA master controller is arranged to adapt to test components of different models by changing programs, so that the application range of the device is effectively improved.
Further, the signal switching module includes a first signal switching board, a second signal switching board, a third signal switching board and a fourth signal switching board, wherein: the four groups of output ends of the level conversion module are respectively connected with the input ends of the first signal switching plate, the second signal switching plate, the third signal switching plate and the fourth signal switching plate; the number of the output ends of the first signal switching plate, the second signal switching plate, the third signal switching plate and the fourth signal switching plate is four; the output ends of the first signal switching plate, the second signal switching plate, the third signal switching plate and the fourth signal switching plate are respectively connected with the input ends of the corresponding test assemblies.
Through setting up multiunit signal patch panel, every signal patch panel of group is with signal output to a plurality of test assembly, realizes controlling a plurality of test assembly simultaneously.
Further, the control signals output by the first signal switching board, the second signal switching board, the third signal switching board and the fourth signal switching board are the same.
By outputting the same control signals, each test component can execute the same command, and the consistency of the aging test of a plurality of test components is realized.
Further, the number of test assemblies was 16 groups.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the utility model as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the utility model and together with the description, serve to explain the principles of the utility model.
FIG. 1 is a schematic overall flow chart of the present utility model;
FIG. 2 is a schematic diagram illustrating connection between a first signal patch panel and a corresponding testing assembly according to the present utility model;
FIG. 3 is a schematic view of the external structure of the case of the present utility model;
Fig. 1-3 include:
1. a power module; 2. a clock module; 3. a serial port module; 4. an FPGA master controller; 5. a level conversion module; 61. a first signal patch panel; 62. a second signal patch panel; 63. a third signal patch panel; 64. a fourth signal patch panel; 7. and testing the assembly.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the utility model. Rather, they are merely examples of apparatus and methods consistent with aspects of the utility model as detailed in the accompanying claims.
As shown in fig. 1-3:
an aging experiment device for generating multiple groups of interface signals is used for inputting control signals to multiple test assemblies 7, and comprises a box body 8, a control board, a control module and a signal switching module, wherein: the control module and the signal switching module are arranged on the control board; the control panel is arranged in the box body 8; the input end of the control module is connected with the PC end; the output end of the control module is connected with the input end of the signal switching module; the number of the input ends of the signal switching module is at least two groups;
The number of the output ends of the signal transfer module is four times of the number of the input ends of the signal transfer module; the output end of the signal switching module is connected with the input ends of the test assemblies.
The working process of the application is as follows:
The aging experiment device is respectively connected with a computer and a testing component 7, an input control signal is arranged at the PC end and is output to a signal switching module after the signal is processed by the control module, the signal switching module outputs a plurality of groups of identical signals of the control signal output bit, and each group of signals are input to the corresponding testing component, so that the effect of inputting a plurality of groups of output at one time is realized; and a plurality of test components are controlled without a plurality of control boxes, so that the use cost is reduced, and the method is suitable for small-batch burn-in test work. And after the program is set on the PC end, the PC end is sent to an aging experiment device, the aging experiment device converts the program into corresponding electric signals, then the electric signals are output by a plurality of interfaces, each interface is correspondingly connected with a test assembly 7 to be subjected to aging test, and the test assembly 7 starts loading aging after receiving the signals.
The control signals are output to the plurality of test assemblies 7 through the signal switching module, so that the effect of ageing the plurality of test assemblies 7 at one time with low cost is achieved.
Optionally, the control module includes a power module 1, a clock module 2, a serial port module 3, an FPGA master 4, and a level conversion module 5, where: the output ends of the power supply module 1, the clock module 2 and the serial port module 3 are connected with the input end of the FPGA main controller 4; the input end of the serial port module 3 is connected with the PC end; the output end of the FPGA main controller 4 is connected with the input end of the level conversion module 5; the number of output terminals of the level shift module 5 is four. The power module 1 is used for supplying power to the whole device, the serial port module 3 is communicated with the PC end, signals are transmitted to the FPGA main controller 4, and control signals output by the FPGA main controller 4 are filtered by the level conversion module 5 and then are transmitted to the signal switching module. The FPGA main controller 4 is arranged to adapt to test assemblies 7 of different models by changing programs, so that the application range of the device is effectively improved.
The output signals of the FPGA main controller 4 pass through the level conversion module 5, the level conversion module 5 can output the signals into 3.3v or 5v signals according to different product requirements, and at most 4 x 13 signals are generated, 13 signals are in a group, four groups of signals are respectively output through four groups of output ends of the level conversion module 5, and the output ends of the level conversion module 5 can adopt a signal output connector to output the signals. The four-group signal output can be performed at most, and the number of output ends can be changed according to the requirements of different products.
Optionally, the signal switching module includes a first signal switching board 61, a second signal switching board 62, a third signal switching board 63, and a fourth signal switching board 64, wherein: the four groups of output ends of the level conversion module 5 are respectively connected to the input ends of the first signal switching plate 61, the second signal switching plate 62, the third signal switching plate 63 and the fourth signal switching plate 64; the number of output ends of the first signal patch panel 61, the second signal patch panel 62, the third signal patch panel 63 and the fourth signal patch panel 64 is four; the output ends of the first signal patch panel 61, the second signal patch panel 62, the third signal patch panel 63 and the fourth signal patch panel 64 are respectively connected to the input ends of the corresponding test assemblies 7.
Four groups of adapter plates are arranged, each group of adapter plates receives 13 signals at most, the 13 signals are in one group, after the signals are received, the adapter plates divide the four groups of signals, then the signals are output through an output connector, and finally the signals are connected to a test assembly, so that 16 groups of control signals can be output at the same time, and the aging test of a small batch can be basically met; the output end of the adapter plate can be connected with the testing assembly through the connector, and as one group of control signals are input into four groups of adapter plates and then are converted into 16 groups of signals, a plurality of control boxes are not needed, the control module, the adapter plate and the connector are integrated in one control box, and the use cost is reduced.
Alternatively, the control signals output from the first signal patch panel 61, the second signal patch panel 62, the third signal patch panel 63, and the fourth signal patch panel 64 are all the same. By outputting the same control signal, each test component 7 can be made to execute the same command, and consistency of burn-in testing of the plurality of test components 7 can be achieved.
Alternatively, the number of test assemblies 7 is 16 groups.
Other embodiments of the utility model will be apparent to those skilled in the art from consideration of the specification and practice of the utility model disclosed herein. This utility model is intended to cover any variations, uses, or adaptations of the utility model following, in general, the principles of the utility model and including such departures from the present disclosure as come within known or customary practice within the art to which the utility model pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the utility model being indicated by the following claims.
It is to be understood that the utility model is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the utility model is limited only by the appended claims.
Claims (6)
1. An ageing experiment device for producing multiunit interface signal for to a plurality of test module input control signal, its characterized in that includes box body, control panel, control module and signal switching module, wherein:
The control module and the signal switching module are arranged on the control panel;
the control board is arranged in the box body;
the input end of the control module is connected with the PC end;
The output end of the control module is connected with the input end of the signal switching module;
the number of the input ends of the signal switching module is at least two groups;
the number of the output ends of the signal transfer module is four times that of the input ends of the signal transfer module;
The output end of the signal switching module is connected with the input ends of the test assemblies.
2. The burn-in apparatus of claim 1 wherein the control module comprises a power module, a clock module, a serial port module, an FPGA master and a level shift module, wherein:
The output ends of the power supply module, the clock module and the serial port module are connected with the input end of the FPGA main controller;
the input end of the serial port module is connected with the PC end;
The output end of the FPGA main controller is connected with the input end of the level conversion module;
The number of the output ends of the level conversion module is four groups.
3. The burn-in apparatus of claim 2 wherein the signal transfer module comprises a first signal transfer plate, a second signal transfer plate, a third signal transfer plate, and a fourth signal transfer plate, wherein:
The four groups of output ends of the level conversion module are respectively connected with the input ends of the first signal switching plate, the second signal switching plate, the third signal switching plate and the fourth signal switching plate;
The number of output ends of the first signal adapter plate, the second signal adapter plate, the third signal adapter plate and the fourth signal adapter plate is four;
The output ends of the first signal switching plate, the second signal switching plate, the third signal switching plate and the fourth signal switching plate are respectively connected with the input ends of the corresponding testing components.
4. The burn-in apparatus of claim 3 wherein the control signals output by the first signal patch panel, the second signal patch panel, the third signal patch panel, and the fourth signal patch panel are all the same.
5. A burn-in apparatus as in claim 3 wherein the number of test elements is 16 groups.
6. The burn-in apparatus of claim 3 wherein the cartridge is provided with a power port, a PC port, and a plurality of output ports, wherein:
The power supply module is connected to an external power supply through the power supply port;
the serial port module is connected to the PC end through the PC port;
The output ends of the first signal adapter plate, the second signal adapter plate, the third signal adapter plate and the fourth signal adapter plate are connected to the test assembly through the output port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322941772.2U CN221100928U (en) | 2023-11-01 | 2023-11-01 | Aging experiment device for generating multiple groups of interface signals |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322941772.2U CN221100928U (en) | 2023-11-01 | 2023-11-01 | Aging experiment device for generating multiple groups of interface signals |
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| CN221100928U true CN221100928U (en) | 2024-06-07 |
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| CN202322941772.2U Active CN221100928U (en) | 2023-11-01 | 2023-11-01 | Aging experiment device for generating multiple groups of interface signals |
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