CN221080020U - Electronic device - Google Patents

Abstract

The application provides an electronic device, in particular to a fan-out type chip-on-substrate packaging product, which comprises a packaging structure and a heat dissipation cover, wherein: the packaging structure comprises: a substrate; the first chip and the second chip are positioned on the same side surface of the substrate and are arranged at intervals; the circuit layer is electrically connected with the substrate, the first chip and the second chip; an underfill material covering the circuit layer and filling a gap between the first chip and the second chip; the heat dissipation cover is arranged above the packaging structure, the thermal expansion coefficient of the heat dissipation cover is smaller than that of the packaging structure, and the fracture toughness of the heat dissipation cover is larger than that of the first chip and the second chip. The application avoids the bottom filling material fracture caused by the over high interface stress in the process by limiting the thermal expansion coefficient and fracture toughness of the heat dissipation cover material, and improves the process yield of the electronic device.

Description

Electronic device

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to an electronic device.

Background

With the increasing demands of high-density, high-speed and low-delay chip interconnection, the chip-on-Fan-Out substrate packaging technology (FOCoS, fan Out Chip on Substrate) breaks through the limitations of the traditional flip-chip packaging, and can realize system integration at the packaging level after recombining multiple chips or multiple heterogeneous chiplets (Chiplet) into a Fan-Out Module.

In the conventional fan-out type chip-on-substrate package product, various functional elements are stacked and integrated with different materials, as shown in fig. 1, for example, a first chip 011 and a second chip 012 made of silicon material, a heat dissipation cover 015 made of heat dissipation material, and an underfill material 013 made of epoxy resin. The problem that the interfacial stress exceeds the interfacial strength is easily generated in the high temperature environment of the manufacturing process of the chip packaging product on the fan-out type substrate, and the phenomenon is that the filling positions of the underfills among the chips are easily broken due to the overlarge difference of the thermal expansion coefficients of various different materials.

Disclosure of utility model

The application provides an electronic device.

The application provides a fan-out type chip-on-substrate packaging product, which comprises: package structure and heat dissipation lid. Wherein the packaging structure includes: a substrate; the first chip is positioned on one side surface of the substrate; the second chip is positioned on one side surface of the substrate, the first chip and the second chip are positioned on the same side surface of the substrate, and the first chip and the second chip are arranged at intervals; the circuit layer is arranged on the substrate and is electrically connected with the substrate, the first chip and the second chip; and the bottom filling material is used for coating the circuit layer and filling a gap between the first chip and the second chip. The heat dissipation cover is arranged above the packaging structure, the thermal expansion coefficient of the heat dissipation cover is smaller than that of the packaging structure, and the fracture toughness of the heat dissipation cover is larger than that of the first chip and the second chip.

In order to solve the technical problems of bottom filling material fracture and poor process yield in the existing fan-out type substrate chip packaging product process, the application provides an electronic device, which comprises a packaging structure and a heat dissipation cover, wherein the heat dissipation cover is arranged above the packaging structure; the specific packaging structure comprises a substrate and a first chip and a second chip which are positioned on the same side surface of the substrate, in order to avoid mutual interference of the first chip and the second chip or influence heat dissipation of the chips, the first chip and the second chip are arranged at intervals, a circuit layer is arranged on the substrate, the first chip and the second chip are electrically connected with the substrate through the circuit layer, gaps between the first chip and the second chip are filled with underfill, meanwhile, the underfill coats the circuit layer, the first chip and the second chip are separated through the underfill, the first chip and the second chip are fixed relative to the circuit layer, the underfill can protect the first chip and the second chip from being affected by physical damage and humidity, so that reliability and service life of the first chip and the second chip are improved, and the underfill can bear thermal stress and mechanical stress of a process. The thermal expansion coefficient and the fracture toughness of the heat dissipation cover material are limited by selecting the heat dissipation cover material, the thermal expansion coefficient of the heat dissipation cover is smaller than that of the packaging structure, and the fracture toughness of the heat dissipation cover is larger than that of the first chip and the second chip; avoid the fracture of the underfill caused by the too high interface stress in the process. The heat dissipation cover material is selected so that the thermal expansion coefficient of the heat dissipation cover is matched with that of the bottom filling material, the stress borne by the bottom filling material is reduced in a high-temperature environment in the process, and the technical problem that the bottom filling material is easy to break in the process is solved; meanwhile, the high fracture toughness of the heat dissipation cover improves the technical problems that the heat dissipation cover is fragile and easy to damage, and the manufacturing process is difficult. The technical effect of avoiding influencing the process yield under the premise of ensuring the integrity of the bottom filling material is achieved. In addition, the stability of the whole structure is improved by the packaging structure, and the reliability of the electronic device in a normal working scene is guaranteed.

In some optional embodiments, the fracture toughness of the heat dissipation cover is greater than or equal to 3 MPa-m ^1/2, so that the structural strength of the heat dissipation cover is ensured, and the heat dissipation cover is prevented from fracture in the process.

In some alternative embodiments, the thermal expansion coefficient of the heat dissipating cover is less than or equal to 5 ppm/DEG C, which reduces the stress on the underfill during processing compared to the prior art, which is a better match to the thermal expansion coefficient of the underfill.

In some alternative embodiments, the electronic device further comprises a mold seal surrounding the first chip and the second chip, wherein an upper surface of the mold seal, an upper surface of the first chip, an upper surface of the second chip, and an upper surface of the underfill are coplanar. The plane formed by the upper surface of the mold seal layer, the upper surface of the first chip, the upper surface of the second chip and the upper surface of the bottom filling material is a first surface, so that the application of a thermal interface material and the installation of a heat dissipation cover are easy.

In some optional embodiments, the electronic device further includes a thermal interface material layer disposed between the first surface and the heat dissipating cover, so that thermal expansion caused by high heat can be reduced to weaken interface stress during the process, the probability of breaking the underfill can be reduced, and heat generated by the first chip and the second chip can be rapidly conducted out during the product use, so that the temperatures of the first chip and the second chip can be reduced.

In some alternative embodiments, the surface of the heat dissipating cover facing the first surface is a second surface, and the second surface is an arc surface, so as to reduce internal stress of the product and prevent the underfill from breaking.

In some alternative embodiments, the second surface protrudes toward an upper surface of the heat dissipating cover.

In some alternative embodiments, the electronic device further comprises a plurality of conductive posts connecting the heat dissipating cover and the substrate.

In some alternative embodiments, the heat-dissipating cover has a heat-conducting capacity that is greater than the heat-conducting capacity of the electrically-conductive posts.

In some optional embodiments, the heat conducting capacity of the heat dissipating cover is greater than or equal to 200W/m·k, so that the heat conducting rate in a high-temperature environment can be increased, the thermal expansion caused by high heat can be reduced in the process to weaken the interface stress, the probability of breaking the filler is reduced, the heat generated by the first chip and the second chip can be rapidly conducted out in the use of the product, and the temperature of the first chip and the second chip is reduced.

In some alternative embodiments, the material of the heat dissipating cover is diamond or silicon carbide, where the silicon carbide and the diamond have excellent heat conducting capability, the coefficient of thermal expansion is matched with that of the underfill, and the heat dissipating capability is better when the heat dissipating cover is applied to high-order operation.

In some alternative embodiments, the thermal interface material layer covers the first chip and the second chip and is capable of substantially conducting heat generated by the first chip and the second chip.

In some optional embodiments, the orthographic projection of the thermal interface material layer on the substrate and the orthographic projection of the mold seal layer on the substrate do not overlap, so that waste caused by excessive application of the thermal interface material is avoided.

In some alternative embodiments, the orthographic projection of the heat dissipating cover on the substrate covers the orthographic projection of the conductive post on the substrate, and the heat dissipating cover is supported by the conductive post and is connected to the substrate.

In some alternative embodiments, the thermal resistance of the heat dissipation cover is smaller than that of silicon, so that the heat dissipation is prevented from being influenced by the fact that the heat conduction capacity is too low when the temperature difference between the inside and the outside is large.

In some alternative embodiments, the outer edges of the mold seal layer and the circuit layer are substantially flush, taking full advantage of mold seal material and avoiding waste.

In some optional embodiments, the orthographic projection of the heat dissipation cover on the substrate covers the orthographic projection of the thermal interface material layer on the substrate, so that a sufficient contact area between the thermal interface material layer and the heat dissipation cover is ensured, and the overall heat dissipation efficiency is improved.

In some alternative embodiments, the first chip and the second chip are functionally different chips. The first chip and the second chip having different functions may provide greater flexibility and adaptability to the electronic device.

In some alternative embodiments, the first chip is an application specific integrated chip. The special integrated chip has the advantages of higher performance, higher efficiency, lower cost, smaller package and the like.

In some alternative embodiments, the second chip is a high bandwidth memory chip. High bandwidth memory chips can provide higher bandwidth, lower power consumption, and smaller packages.

In some alternative embodiments, the conductive posts are disposed around the substrate. The conductive posts around the substrate can form a firm support frame that can enhance the mechanical strength and stability of the overall structure, thereby enhancing its vibration and shock resistance.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

FIG. 1 is a partial schematic view of a longitudinal cross-section of a current electronic device;

FIG. 2 is a partial schematic view of a transverse cross-section of a current electronic device;

FIG. 3 is a schematic diagram of a current underfill break;

FIG. 4 is a schematic longitudinal cross-sectional view of one embodiment 4a of the electronic device of the present application;

Fig. 5 is a schematic longitudinal sectional structure of an embodiment 5a of the electronic device of the present application.

Reference numerals/symbol description:

011-a first chip; 012-second chip; 013-underfill; 014-cleavage structure; 015-heat sink cap; 016—a circuit layer;

10-packaging structure; 11-a first chip; 12-a second chip; 13-a substrate; 14-a circuit layer; 15-underfill; 16-an adhesive layer; 17-metal columns; 18-bump; 19-a first surface;

20-a heat dissipation cover; 30-mold sealing; 40—a layer of thermal interface material; 50-conductive pillars.

The specific embodiment is as follows:

The following description of the embodiments of the present disclosure is provided in connection with the accompanying drawings and examples, and those skilled in the art will readily understand the technical problems and effects addressed by the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. In addition, for convenience of description, only a portion related to the related invention is shown in the drawings.

It should be readily understood that the meanings of "on," "over," and "above" in this disclosure should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire chips, or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the descriptions of the structures, proportions, sizes, etc. for the understanding and reading of the disclosure, and are not intended to limit the applicable limitations of the disclosure, so that any structural modifications, proportional changes, or adjustments of sizes are not technically essential, and thus, any structural modifications, proportional changes, or adjustments of sizes may fall within the scope of the disclosure without affecting the efficacy or achievement of the present disclosure. Also, the terms "upper", "first", "second", and "a" and the like recited in the present specification are also for descriptive purposes only and are not intended to limit the scope of the disclosure in which the present disclosure may be practiced, but rather the relative relationship of the terms is modified or adapted to be within the scope of the disclosure without substantial modification to the technical content.

It should be further noted that, the longitudinal section corresponding to the embodiment of the present disclosure may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the upper view direction.

In addition, embodiments of the present disclosure and features of embodiments may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In the existing fan-out type chip-on-substrate packaging product, various functional elements are stacked and integrated with different materials, and the problem that the interface stress exceeds the interface strength is easily generated in the high-temperature environment of the manufacturing process of the fan-out type chip-on-substrate packaging product is caused by the fact that the thermal expansion coefficients of the various different materials are too large, so that the filling positions of the underfills among the chips are easily broken. Although the lower substrate and the upper heat dissipation cover can provide rigidity which is not easy to deform, in practical tests, the heat dissipation cover made of copper is easy to generate the problem that the interface stress exceeds the interface strength, and the underfill material between chips is more easy to break.

The semiconductor packaging industry has also made heat dissipation covers based on silicon materials so as to improve the fracture situation of the bottom filling materials by utilizing the smaller thermal expansion coefficient in practical tests, but the fracture toughness of the silicon materials is low and is easy to fracture during manufacturing, and meanwhile, the heat conduction coefficient is low, so that the yield of the manufacturing process is low, and the heat dissipation capacity of the produced electronic device is poor.

As shown in fig. 1-3, in the fan-out type chip-on-substrate package product, a first chip 011 is electrically connected with a second chip 012 and a circuit layer 016, a gap is reserved in the middle of the same side of the circuit layer 016, an underfill 013 coats the circuit layer 016 and fills the gap between the first chip 011 and the second chip 012, a heat dissipation cover 015 is arranged above the first chip 011, the second chip 012 and the underfill 013, and the heat dissipation cover 015 is made of copper or silicon. Because of the special structure of the chip package product on the fan-out substrate in the process, the underfill 013 is subjected to much higher stress than other components and is easy to break, so that the underfill 013 is broken to form a broken structure 014.

Therefore, the existing heat dissipation cover 015 of the fan-out type substrate chip package product is difficult to fully protect the underfill 013, and meanwhile, the process yield is affected due to improper material selection of the heat dissipation cover 015.

In order to solve the above-mentioned series of problems, the present application adopts the following scheme, and referring to fig. 4, fig. 4 is a schematic view of a longitudinal cross-sectional structure of an embodiment 4a of the electronic device of the present application. In fig. 4, the present application provides an electronic device including: the package structure 10 and the heat dissipation cover 20 disposed above the package structure 10, in order to ensure that the package structure 10 is broken due to the performance of the heat dissipation cover 20, that is, to avoid breaking at the underfill 15 between the first chip 11 and the second chip 12, it is necessary to ensure that the thermal expansion coefficient of the heat dissipation cover 20 is smaller than that of the package structure 10, and the fracture toughness of the heat dissipation cover 20 is greater than that of the first chip 11 and the second chip 12. A specific package structure 10 includes: a substrate 13; a first chip 11 located on one side surface of the substrate 13; the second chip 12 is located on one side surface of the substrate 13, the first chip 11 and the second chip 12 are located on the same side surface of the substrate 13, and in order to avoid mutual interference of the first chip 11 and the second chip 12 or influence on heat dissipation of the chips, the second chip 12 and the first chip 11 are arranged at intervals; a circuit layer 14 disposed on the substrate 13 and electrically connected to the substrate 13, the first chip 11 and the second chip 12; an underfill 15 that coats the circuit layer 14 and fills a gap between the first chip 11 and the second chip 12; the heat dissipation cover 20 is disposed above the package structure 10, the thermal expansion coefficient of the heat dissipation cover 20 is smaller than that of the package structure 10, and the fracture toughness of the heat dissipation cover 20 is greater than that of the first chip 11 and the second chip 12.

In order to solve the technical problems of breakage of the underfill 15 and poor process yield in the existing process of packaging chips on a fan-out substrate 13, the application provides an electronic device, which comprises a packaging structure 10 and a heat dissipation cover 20, wherein the heat dissipation cover 20 is arranged above the packaging structure 10; the specific packaging structure 10 includes a substrate 13 and a first chip 11 and a second chip 12 located on the same side surface of the substrate 13, in order to avoid mutual interference of the first chip 11 and the second chip 12 or influence on heat dissipation of the chips, the first chip 11 and the second chip 12 are arranged at intervals, a circuit layer 14 is arranged on the substrate 13, the first chip 11 and the second chip 12 are electrically connected with the substrate 13 through the circuit layer 14, a gap between the first chip 11 and the second chip 12 is filled with an underfill 15, meanwhile, the underfill 15 coats the circuit layer 14, the first chip 11 and the second chip 12 are isolated through the underfill 15, the first chip 11 and the second chip 12 are fixed relative to the circuit layer 14, the underfill 15 can protect the first chip 11 and the second chip 12 from physical damage and humidity, so that reliability and service life of the first chip 11 and the second chip 12 are improved, and the underfill 15 can bear thermal stress and mechanical stress of a process. By selecting the material of the heat dissipation cover 20, the thermal expansion coefficient and the fracture toughness of the material of the heat dissipation cover 20 are limited, the thermal expansion coefficient of the heat dissipation cover 20 is smaller than that of the package structure 10, and the fracture toughness of the heat dissipation cover 20 is larger than that of the first chip 11 and the second chip 12; the underfill 15 is prevented from breaking due to excessive interfacial stress during the process. The material of the heat dissipation cover 20 is selected so that the thermal expansion coefficient of the heat dissipation cover 20 is matched with that of the bottom filling material 15, the stress on the bottom filling material 15 is reduced in the high-temperature environment in the process, and the technical problem that the bottom filling material 15 is easy to break in the process is solved; meanwhile, the high fracture toughness of the heat dissipation cover 20 improves the technical problem that the heat dissipation cover 20 is fragile and easy to damage, and the manufacturing process is difficult. The technical effect of avoiding influencing the process yield under the premise of ensuring the completeness of the bottom filling material 15 is achieved. In addition, the package structure 10 improves the stability of the overall structure, and ensures the reliability of the electronic device in a normal working scene.

For ease of understanding, the coefficient of thermal expansion (CTE, coefficient of thermal expansion) is the expansion of the object due to temperature changes. Fracture toughness (K _IC) is a material constant, referred to as the plane strain fracture toughness of a material.

Alternatively, the fracture toughness of the heat dissipation cover 20 is 3mpa·m ^1/2 or more, for example, the fracture toughness of the heat dissipation cover 20 may be 3.5MPa·m^1/2、4MPa·m^1/2、4.5MPa·m^1/2、5MPa·m^1/2、5.3MPa·m^1/2、5.5MPa·m^1/2、6MPa·m^1/2、6.5MPa·m^1/2 or 7mpa·m ^1/2; the structural strength of the heat dissipation cover 20 is ensured, and the breakage of the heat dissipation cover during the manufacturing process is avoided.

Alternatively, the coefficient of thermal expansion of the heat sink cap 20 is less than or equal to 5 ppm/. Degree.C.for example, the coefficient of thermal expansion of the heat sink cap 20 is 1 ppm/. Degree.C.1.5 ppm/. Degree.C.2 ppm/. Degree.C.2.5 ppm/. Degree.C.3 ppm/. Degree.C.3.5 ppm/. Degree.C.4 ppm/. Degree.C.4.5 ppm/. Degree.C.or 5 ppm/. Degree.C.. Compared with the prior art, the thermal expansion coefficient of the underfill material 15 is more matched, so that the stress on the underfill material 15 in the process is reduced.

With continued reference to fig. 4, the circuit layer 14 is electrically connected to the substrate 13 through the bump 18 and electrically connected to the first chip 11 and the second chip 12 through the metal pillar 17; the underfill 15 encapsulates the circuit layer 14 and fills the gap between the first chip 11 and the second chip 12, and is used for providing mechanical support for the package body, reducing external environment interference and absorbing the adaptive stress in the temperature cycle process to ensure the functional effect of the electronic device provided by the embodiment of the application; the thermal interface material layer 40 is disposed on the first surface 19 to accelerate heat conduction between the first chip 11, the second chip 12 and the heat dissipation cover 20, and the thermal interface material layer 40 covers the first chip 11 and the second chip 12, so as to maximize the contact area and accelerate the heat dissipation speed.

For example, the substrate 13 includes, but is not limited to, a common substrate, a lead frame (LEAD FRAME), a molded interconnect substrate (Molded Interconnect Substrate, MIS). The mold layer 30 herein may be formed of various mold materials (Molding Compound). For example, the molding material may include Epoxy (Epoxy resin), filler (Filler), catalyst (Pigment), release Agent (RELEASE AGENT), flame retardant (FLAME RETARDANT), coupling Agent (Coupling Agent), hardener (Harden), low stress absorber (Low Stress Absorber), adhesion promoter (Adhesion Promoter), ion scavenger (Ion TRAPPING AGENT), and the like. For example, the underfill may be, for example, a capillary underfill (CUF, CAPILLARY UNDERFILL), a Molded Underfill (MUF), a Non-conductive Paste (NCP), or the like.

In some embodiments, the electronic device further includes a mold seal layer 30, the mold seal layer 30 surrounding the first chip 11 and the second chip 12, an upper surface of the mold seal layer 30, an upper surface of the first chip 11, an upper surface of the second chip 12, and an upper surface of the underfill 15 are coplanar; the plane formed by the upper surface of the mold layer 30, the upper surface of the first chip 11, the upper surface of the second chip 12, and the upper surface of the underfill 15 is the first surface 19. By ensuring that the upper surface of the mold seal layer 30, the upper surface of the first chip 11, the upper surface of the second chip 12, and the upper surface of the underfill 15 are coplanar, it is convenient to form a thermal interface material layer 40 on the first surface 19 thereof in a subsequent process, and form a heat dissipation cap 20, specifically a thermal interface material layer 40, on the upper surface of the thermal interface material layer 40, disposed between the first surface 19 and the heat dissipation cap 20; the thermal interface material layer 40 can reduce thermal expansion caused by high heat to weaken interface stress and reduce the fracture probability of the underfill 15, so that the heat generated by the first chip 11 and the second chip 12 can be rapidly conducted out in the use of the electronic device, and the temperature of the first chip 11 and the second chip 12 can be reduced.

Referring specifically to fig. 4, the electronic device provided in the embodiment of the present application further includes a plurality of conductive pillars 50, where the conductive pillars 50 connect the heat dissipating cover 20 and the substrate 13. The conductive posts 50 are connected with the heat dissipation cover 20 through the adhesive layer 16, and the conductive posts 50 are connected with the substrate 13 through the adhesive layer 16; the specific conductive posts 50 are perpendicular to the substrate 13, and the conductive posts 50 are also perpendicular to the heat sink cap 20. The conductive posts 50 strengthen the connection between the heat dissipating cover 20 and the substrate 13, improving the heat dissipating efficiency of the electronic device provided by the embodiments of the present application. When the electronic device provided by the embodiment of the application works, a large amount of heat is generated, and if the heat cannot be timely dissipated, the temperature of the electronic device is increased, so that the electronic device is caused to fail; it is required to rapidly dissipate heat through the heat dissipating cover 20. In addition, the conductive posts 50 can also improve the mechanical strength and reliability of the electronic device provided by the embodiment of the application, and reduce the risk of damage caused by temperature changes and mechanical stress changes.

In order to improve the heat dissipation capacity of the heat dissipation cover 20, the heat conduction capacity K of the heat dissipation cover 20 is greater than the heat conduction capacity of the conductive pillars 50. The heat conduction capacity K of the heat dissipation cover 20 is 200W/m.k or more, for example, 200W/m·k、250W/m·k、300W/m·k、400W/m·k、500W/m·k、600W/m·k、700W/m·k、800W/m·k、900W/m·k、1000W/m·k、1100W/m·k、1200W/m·k、1300W/m·k、1400W/m·k、1500W/m·k、1600W/m·k、1700W/m·k、1800W/m·k、1900W/m·k or 2000W/m.k of the heat dissipation cover 20. The heat conduction rate in a high-temperature environment can be increased, the thermal expansion caused by high heat can be reduced in the process to weaken the interface stress, the breaking probability of the filling material can be reduced, the heat generated by the first chip 11 and the second chip 12 can be rapidly led out in the use of the electronic device, and the temperatures of the first chip 11 and the second chip 12 can be reduced.

For example, the material of the heat dissipating cover 20 is diamond or silicon carbide, wherein silicon carbide and diamond have excellent heat conducting capability, and the thermal expansion coefficient is relatively matched with that of the underfill 15, so that the heat resistance of the electronic device provided by the embodiment of the application is smaller, and the heat dissipating capability is better when the electronic device is applied to high-order operation.

With continued reference to fig. 4, the thermal interface material layer 40 covers the first chip 11 and the second chip 12 and is capable of sufficiently conducting heat generated by the first chip 11 and the second chip 12. The front projection of the thermal interface material layer 40 on the substrate 13 does not overlap with the front projection of the mold seal layer 30 on the substrate 13, so that waste caused by excessive application of the thermal interface material is avoided.

For example, the front projection of the heat dissipating cover 20 on the substrate 13 covers the front projection of the conductive post 50 on the substrate 13, and the heat dissipating cover 20 is supported by the conductive post 50 and connected to the substrate 13. The conductive posts 50 are disposed around the substrate 13, that is, the conductive posts 50 are located at the edge of the substrate 13, and the conductive posts 50 around the substrate 13 can form a firm supporting frame, so as to enhance the mechanical strength and stability of the overall structure, thereby enhancing the vibration and impact resistance thereof.

When the electronic device provided in the embodiment of the application performs a High-order operation, for example, AI, high-performance computing (HPC, high-Performance Computing), etc., it is required to reduce the thermal resistance (θ _JC) of the heat dissipation cover 20, that is, the smaller the thermal resistance of the heat dissipation cover 20 is, the better, the thermal resistance of the heat dissipation cover 20 is smaller than the thermal resistance of silicon, so as to prevent the heat dissipation from being affected by the too low heat conduction capability when the temperature difference between the inside and outside is large, for example, the thermal resistance (θ _JC) of the heat dissipation cover 20 may be 0.024 (°c/W), 0.030 (°c/W), or 0.034 (°c/W).

Regarding the material of the heat dissipation cover 20, it may be selected according to the materials in table 1 below.

TABLE 1

Heat radiation cover	Cu (copper)	Si (silicon)	Diamond diamond
				CTE(ppm/℃)	16.5	2.5	1.1
K(W/m·k)	401	149	1000-2200
				KIC(MPa·m1/2)	40-100	0.7-1.3	5.3-7.0
θJC(℃/W)	0.024	0.034	≤0.020

In table 1, when the heat dissipating cover is selected to be Cu (copper), it has a high heat conducting capability (K), but at the same time has a high Coefficient of Thermal Expansion (CTE), which may easily cause breakage of the underfill; when the heat sink cap is selected to be Si (silicon), although the heat sink cap has a low Coefficient of Thermal Expansion (CTE), the heat conduction capability (K) and fracture toughness (K _IC) are also low, which results in poor heat dissipation capability and brittle heat sink cap; when diamond is selected as the heat dissipating cover material, the heat dissipating cover has low Coefficient of Thermal Expansion (CTE), high heat conducting capacity (K), high fracture toughness (K _IC), and thermal resistance (θ _JC) can be improved by more than 41%, so that the performance of the heat dissipating cover is improved.

In some alternative embodiments, the outer edges of the mold layer 30 and the circuit layer 14 are substantially flush, such that the mold layer 30 both ensures protection of the first chip 11 and the second chip 12 from external vibrations, humidity, oxidation, etc., and fully utilizes the mold material and avoids waste.

The front projection of the heat dissipating cover 20 on the substrate 13 covers the front projection of the thermal interface material layer 40 on the substrate 13, so as to ensure that the thermal interface material layer 40 and the heat dissipating cover 20 have enough contact area, and improve the overall heat dissipating efficiency.

In the electronic device provided in the embodiment of the present application, the first chip 11 and the second chip 12 are chips with different functions. The first chip 11 and the second chip 12, which are functionally different, may bring about greater flexibility and adaptability to the electronic device.

For example, the first chip 11 is an application specific integrated chip. The special integrated chip has the advantages of higher performance, higher efficiency, lower cost, smaller package and the like. For example, the second chip 12 is a high bandwidth memory chip. High bandwidth memory chips can provide higher bandwidth, lower power consumption, and smaller packages.

As shown in fig. 5, fig. 5 is a schematic longitudinal sectional structure of an embodiment 5a of the electronic device of the present application. Fig. 5 is different from fig. 4 in that, in the electronic device shown in fig. 5, a surface of the heat dissipation cover 20 facing the first surface 19 is a second surface, and the second surface is an arc surface, so as to reduce internal stress of the product and prevent the underfill 15 from breaking. In some alternative embodiments, the second surface protrudes toward the upper surface of the heat dissipating cover 20.

For ease of understanding, the following detailed description is made with respect to the specific structure of fig. 5: one embodiment of a chip package product on a fan-out substrate 13 shown in fig. 5 is similar to the electronic device shown in fig. 4, wherein the first chip 11 and the second chip 12 are an application specific integrated chip and a high bandwidth memory chip respectively, and are located on the same side of the substrate 13 and are arranged at intervals, and the circuit layer 14 is electrically connected with the substrate 13 through the bump 18 and is electrically connected with the first chip 11 and the second chip 12 through the metal pillar 17; the underfill 15 coats the circuit layer 14 and fills the gap between the first chip 11 and the second chip 12, and is used for providing mechanical support, avoiding the interference of external environment and absorbing the adaptive stress in the temperature cycle process to ensure the functional effect of the electronic device; the mold seal layer 30 surrounds the first chip 11 and the second chip 12, the upper surface of the mold seal layer 30, the upper surface of the first chip 11, the upper surface of the second chip 12 and the upper surface of the underfill 15 are coplanar, the plane is called as a first surface 19, meanwhile, the surface of the heat dissipation cover 20 facing the first surface 19 is a second surface, the second surface is an arc-shaped surface, and protrudes towards the upper surface of the heat dissipation cover 20, and the heat dissipation cover 20 adopts an arc-shaped surface structure protruding upwards to help reduce the internal stress of the product and reduce the fracture probability of the underfill 15. The outer edges of the mold seal layer 30 are substantially flush with the outer edges of the circuit layer 14, preventing material waste; the thermal interface material layer 40 is arranged on the first surface 19, so that heat conduction is accelerated, the thermal interface material layer 40 covers the first chip 11 and the second chip 12, the contact area with the first chip 11 is maximized, the heat dissipation speed is accelerated, and meanwhile, the orthographic projection of the thermal interface material layer 40 on the substrate 13 is not overlapped with the orthographic projection of the mold seal layer 30 on the substrate 13, so that the use amount of the thermal interface material is reduced, and the cost is reduced; the heat dissipation cover 20 is connected with the package structure 10 through the thermal interface material layer 40, the conductive posts 50 are connected with the substrate 13 and the heat dissipation cover 20 and are positioned around the substrate 13, and the adhesive layers 16 are adhered between the conductive posts 50 and the substrate 13 and between the conductive posts 50 and the heat dissipation cover 20; preferably, the heat dissipating cover 20 has a heat conducting capacity greater than that of the conductive posts 50; alternative materials for heat spreading cover 20 include, but are not limited to, diamond or silicon carbide.

While the application has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to limit the application. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the application as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproduction and actual implementation in the present application due to variables in the manufacturing process, etc. Other embodiments of the application not specifically illustrated may exist. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods applied herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Thus, the order and grouping of the operations is not a limitation of the present application unless specifically indicated herein.

Claims (10)

1. An electronic device, comprising:

A package structure, comprising:

A substrate;

the first chip is positioned on one side surface of the substrate;

The second chip is positioned on one side surface of the substrate, the first chip and the second chip are positioned on the same side surface of the substrate, and the second chip and the first chip are arranged at intervals;

The circuit layer is arranged on the substrate and is electrically connected with the substrate, the first chip and the second chip;

An underfill material covering the circuit layer and filling a gap between the first chip and the second chip;

The heat dissipation cover is arranged above the packaging structure, the thermal expansion coefficient of the heat dissipation cover is smaller than that of the packaging structure, and the fracture toughness of the heat dissipation cover is larger than that of the first chip and the second chip.

2. The electronic device of claim 1, wherein the heat spreader lid has a fracture toughness of 3 MPa-m ^1/2 or greater.

3. The electronic device of claim 1, wherein the heat spreading cover has a coefficient of thermal expansion of 5ppm/°c or less.

4. The electronic device of claim 1, further comprising a mold seal surrounding the first and second chips, an upper surface of the mold seal, an upper surface of the first chip, an upper surface of the second chip, and an upper surface of the underfill being coplanar;

The plane formed by the upper surface of the mold seal layer, the upper surface of the first chip, the upper surface of the second chip and the upper surface of the bottom filling material is a first surface.

5. The electronic device of claim 4, further comprising a thermal interface material layer disposed between the first surface and the heat sink cap.

6. The electronic device of claim 4, wherein a surface of the heat dissipating cover facing the first surface is a second surface, and the second surface is an arcuate surface.

7. The electronic device of claim 1, further comprising a plurality of conductive posts connecting the heat sink cap and the substrate.

8. The electronic device of claim 7, wherein the heat-dissipating cover has a heat-conducting capability greater than a heat-conducting capability of the electrically-conductive posts.

9. The electronic device according to claim 1, wherein the heat conductive capability of the heat dissipation cover is 200W/m-k or more.

10. The electronic device of claim 1, wherein the heat sink cap material is diamond or silicon carbide.