CN221008957U

CN221008957U - MOSFET layout and MOSFET

Info

Publication number: CN221008957U
Application number: CN202322511370.9U
Authority: CN
Inventors: 薛华瑞; 阮孟波; 董建新
Original assignee: Will Semiconductor Ltd
Current assignee: Will Semiconductor Ltd
Priority date: 2023-09-14
Filing date: 2023-09-14
Publication date: 2024-05-24
Anticipated expiration: 2033-09-14

Abstract

The application provides a MOSFET layout and a MOSFET, comprising: a gate region, a source region and a drain region, the source region being disposed at an intermediate position of the drain region and the gate region; the drain region comprises a first metal layer and a plurality of grooves which are arranged at intervals; the first metal layer is arranged above the groove region and used for leading out a drain electrode; the gate electrode is arranged on the upper portion of the gate electrode region, the third metal region is arranged on the upper portion of the source electrode region, the gate electrode is led out of the gate electrode region through the second metal region, and the source electrode is led out of the source electrode region through the third metal region. According to the application, the groove is introduced into the drain region, and the bottom of the groove penetrates through the whole epitaxial layer to reach the substrate, so that the on-resistance can be reduced.

Description

MOSFET layout and MOSFET

Technical Field

The application relates to the technical field of semiconductors, in particular to a MOSFET layout and a MOSFET.

Background

In the prior art, a gate electrode and a drain electrode of a metal-oxide semiconductor field effect transistor (MOSFET) are both arranged on the front surface of a chip, the drain electrode is led out through a contact hole to form a current conveying channel, and when a forward bias voltage is applied to a gate region, a reverse channel can provide a transmission path from a source region to a drain region for electrons, so that the general on-resistance of the structure is higher.

Disclosure of Invention

In order to solve or alleviate the problems in the prior art.

In a first aspect, an embodiment of the present application provides a MOSFET layout, including: a gate region, a source region and a drain region, the source region being disposed at an intermediate position of the drain region and the gate region;

the drain region comprises a first metal layer and a plurality of grooves which are arranged at intervals;

the first metal layer is arranged above the groove region and used for leading out a drain electrode;

The gate electrode is arranged on the upper portion of the gate electrode region, the third metal region is arranged on the upper portion of the source electrode region, the gate electrode is led out of the gate electrode region through the second metal region, and the source electrode is led out of the source electrode region through the third metal region.

In a second aspect, an embodiment of the present application further provides a MOSFET, including: a gate region, a source region, and a drain region;

The bottommost parts of the grooves extend into the substrate through the epitaxial layer, the epitaxial layer is arranged on the substrate, and a first injection region is arranged between two adjacent grooves;

And the groove is filled with metal, and the top of the groove is contacted with the first metal layer.

As a preferred embodiment of the present application, the metal is tungsten.

As a preferred embodiment of the present application, the bottommost portion of each trench is provided with a second implantation region.

As a preferred embodiment of the present application, the doping type of the first implantation region and the second implantation region are the same.

As a preferred embodiment of the present application, the depth of each of the grooves is the same.

As a preferred embodiment of the present application, the depth of the first implantation region disposed between two adjacent trenches is the same.

Compared with the prior art, the embodiment of the application provides a MOSFET layout and a MOSFET, wherein the source electrode area and the gate electrode area of the layout are unchanged, and the bottom of the trench penetrates through the whole epitaxial layer to reach the substrate by introducing the trench into the drain electrode area, so that the on-resistance can be reduced.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. Some specific embodiments of the application will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers in the drawings denote the same or similar parts or portions, and it will be understood by those skilled in the art that the drawings are not necessarily drawn to scale, in which:

Fig. 1 is a schematic structural diagram of a MOSFET layout according to an embodiment of the present application;

Fig. 2 is a schematic structural diagram of a MOSFET according to an embodiment of the present application;

Fig. 3 is a schematic diagram of a MOSFET made by the layout of the first aspect according to an embodiment of the application.

Detailed Description

In order to enable those skilled in the art to better understand the present application, the following description will make clear and complete descriptions of the technical solutions according to the embodiments of the present application with reference to the accompanying drawings. It will be apparent that the described embodiments are merely some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.

In a first aspect, as shown in fig. 1 and 2, an embodiment of the present application provides a MOSFET layout, including: a gate region 01, a source region 02, and a drain region 03, the source region 02 being disposed at an intermediate position between the drain region 03 and the gate region 01;

The drain region 03 comprises a first metal layer 03-2 and a plurality of trenches 03-1 which are arranged at intervals;

The first metal layer 03-2 is arranged above the plurality of grooves 03-1 and used for leading out a drain electrode;

A second metal region is arranged above the gate region 01, a third metal region is arranged above the source region 02, the gate is led out from the gate region 01 through the second metal region, and the source is led out from the source region 02 through the third metal region.

According to the layout provided by the embodiment of the application, the source electrode region 02 and the gate electrode region 01 in the layout provided by the embodiment of the application are unchanged, the drain electrode region 01 is led into the groove 03-1, metal is filled in the groove 03-1, the drain electrode is led out through the metal, and the bottom of the groove 03-1 passes through the whole epitaxial layer 04 to reach the substrate 05, so that the on-resistance can be reduced.

In a second aspect, as shown in fig. 3, an embodiment of the present application further provides a MOSFET prepared by the layout of the first aspect, including: a gate region 01, a source region 02 and a drain region 03;

the bottommost parts of the plurality of grooves 03-1 extend into the substrate 05 through the epitaxial layer 04, the epitaxial layer 04 is arranged on the substrate 05, a first injection region 06 is arranged between two adjacent grooves 03-1, a dielectric layer 07 is arranged on the upper surface of the epitaxial layer 06, the grooves 03-1 extend to the substrate 05 from top to bottom through the dielectric layer 07, and the epitaxial layer 06 extends to the substrate 05.

The trench 03-1 is filled with metal, and the top of the trench 03-1 is on the basis of the first metal layer 03-2.

Preferably, the metal is tungsten.

Preferably, the bottommost portion of each trench 03-1 is provided with a second implanted region 08.

Preferably, the doping types of the first implantation region 06 and the second implantation region 08 are the same, and arsenic impurities are doped in the embodiment of the present application.

Preferably, the depth of each of the grooves 03-1 is the same.

Preferably, the depth of the first implantation region 06 arranged between two adjacent trenches 03-1 is the same.

In the present application, the side of the substrate 05 away from the epitaxial layer 04 may be thinned, so that the on-resistance of the entire MOSFET may be reduced.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A MOSFET layout, comprising: a gate region, a source region and a drain region, the source region being disposed at an intermediate position of the drain region and the gate region;

2. A MOSFET prepared by a MOSFET layout as claimed in claim 1, comprising: a gate region, a source region, and a drain region;

3. The MOSFET layout prepared MOSFET of claim 2, wherein said metal is tungsten.

4. The MOSFET layout prepared MOSFET of claim 2, wherein a second implant region is provided at a bottommost portion of each trench.

5. The MOSFET layout prepared of claim 4, wherein said first and second implant regions are of the same doping type.

6. The MOSFET layout prepared MOSFET of claim 2 wherein the depth of each of said trenches is the same.

7. A MOSFET layout prepared according to claim 2, wherein the depth of the first implant region disposed between two adjacent trenches is the same.