CN221008254U - LVDS signal conversion device for parallel backboard bus communication mode - Google Patents
LVDS signal conversion device for parallel backboard bus communication mode Download PDFInfo
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- CN221008254U CN221008254U CN202322637363.3U CN202322637363U CN221008254U CN 221008254 U CN221008254 U CN 221008254U CN 202322637363 U CN202322637363 U CN 202322637363U CN 221008254 U CN221008254 U CN 221008254U
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Abstract
The utility model belongs to the technical field of avionics, and particularly relates to an LVDS signal conversion device for a parallel backboard bus communication mode. The LVDS signal conversion device is located on each board, and the LVDS signal conversion device includes: the LVDS data transmitting unit and the LVDS data receiving unit, wherein the LVDS data transmitting unit comprises: the LVDS transmitting device comprises an LVDS transmitting driver, a first code stream converter, a first bit width converter, a coding module and a data transmitting buffer module; the LVDS data receiving unit includes: the LVDS receiving driver, the decoding module, the second bit width converter, the second code stream converter and the data receiving buffer module; compared with direct communication of parallel backboard bus data, the number of pins of a connector and PCB wiring resources are greatly saved.
Description
Technical Field
The utility model belongs to the technical field of avionics, and particularly relates to an LVDS signal conversion device for a parallel backboard bus communication mode.
Background
In the design process of aviation onboard equipment, parallel backboard bus communication is a frequently adopted communication mode among board cards in the equipment. This means that a large number of data lines, address lines and control lines are required to be used for connection in the inter-board communication process, and the pin count requirements of devices such as connectors and dual-port RAM are high. If an LVDS (low voltage differential signaling) signal conversion device is used, parallel backplane bus data are converted into LVDS serial bus signals to perform information transmission between boards, so that the transmission rate can be improved, a large number of connection pins can be reduced, and further, the PCB wiring resources can be greatly saved, and another low-cost solution is provided for subsequent inter-board communication.
Disclosure of utility model
The utility model aims to: the LVDS signal conversion device for the parallel backboard bus communication mode is provided, parallel bus data are converted into serial LVDS signals to complete data communication between boards in equipment, communication cost is reduced, and communication speed is improved.
The technical scheme is as follows:
An LVDS signal conversion device for parallel backplane bus communication, the LVDS signal conversion device being located on each board, the LVDS signal conversion device comprising: the LVDS data transmitting unit and the LVDS data receiving unit, wherein the LVDS data transmitting unit comprises: the LVDS transmitting device comprises an LVDS transmitting driver, a first code stream converter, a first bit width converter, a coding module and a data transmitting buffer module; the LVDS data receiving unit includes: the LVDS receiving driver, the decoding module, the second bit width converter, the second code stream converter and the data receiving buffer module;
The output end of the main functional module of the first board card is connected with the input end of the data transmission buffer module through a 32-bit parallel data bus and a plurality of control buses respectively; the output end of the data transmission buffer module is connected with the input end of the first code stream converter through a 32-bit parallel data bus; the output end of the first code stream converter is connected with the input end of the first bit width converter through a serial data bus; the output end of the first bit width converter is connected with the input end of the coding module through a serial data bus; the output end of the coding module is connected with the input end of the transmitting driver through a serial data bus; the output end of the LVDS transmitting driver is connected with the input end of the LVDS receiving driver of the second board card through an LVDS serial differential bus;
The output end of the LVDS transmitting driver of the second board card is connected with the input end of the LVDS receiving driver of the first board card through an LVDS serial differential bus; the output end of the LVDS receiving driver is connected with the input end of the decoding module through a serial data bus; the output end of the decoding module is connected with the input end of the second bit width converter through a serial data bus; the output end of the second bit width converter is connected with the input end of the second code stream converter through a serial data bus; the output end of the second code stream converter is connected with the data receiving buffer module through a 32-bit parallel data bus, and the output end of the data receiving buffer module is connected with the input end of the main function module of the first board card through a 32-bit parallel data bus and a plurality of control buses respectively.
Further, the LVDS transmitting driver and the LVDS receiving driver are SelectIO IP cores.
Further, the first bit-width converter and the second bit-width converter are both axis_ dwidth _converter IP cores.
Further, the first code stream converter and the second code stream converter are fifo_generator IP cores.
Further, the S end of the fifo_generator IP core of the first code stream converter and the second code stream converter is a 32bit code stream, and the M end is a 32bit parallel data area of the FIFO end.
Further, the data sending buffer memory module and the data receiving buffer memory module both comprise a control IP core and a block_memory storage IP core of the BRAM.
The beneficial effects are that:
The LVDS signal conversion device for parallel backboard bus communication realizes conversion from parallel bus data to LVDS signals on an FPGA, thereby completing data communication between backboard. Adopting a code stream converter, a bit width converter, an encoding module and a decoding module to complete the mutual conversion of parallel bus data and 10bit LVDS code streams; the LVDS receiving driver and the LVDS transmitting driver are adopted to realize the conversion of the 10bit LVDS code stream and the serial LVDS differential level signal, so that the purpose of transmitting data is achieved. After the device is used, the inter-board communication can realize the data transmission function only by 4 signal wires (2 clock wires and 2 LVDS differential signal wires), compared with the direct communication of parallel backboard bus data, the number of pins of a connector and PCB wiring resources are greatly saved; meanwhile, the bandwidth rate of the LVDS is in the range of 100 Mbps-600 Mbps, so that the communication efficiency is greatly improved.
Drawings
FIG. 1 is a functional schematic diagram of an LVDS signal conversion device;
Fig. 2 is a schematic diagram of an LVDS signal conversion device.
Detailed Description
The LVDS signal conversion device for parallel backboard bus communication comprises two functional units, namely LVDS data transmission and LVDS data reception. The transmitting functional unit of the device acquires parallel bus data from the data transmitting buffer module, the parallel bus data is changed into serial LVDS differential level signals after passing through the code stream converter, the bit width converter, the coding module and the LVDS transmitting driver in sequence, and the receiving functional unit of the device receives the serial LVDS differential level signals and then is changed into parallel bus data after passing through the LVDS receiving driver, the decoding module, the bit width converter and the code stream converter, and the parallel bus data is placed in the data receiving buffer module for being read by a processor.
For the LVDS data transmission functional unit, the content comprises a data transmission buffer module, a code stream converter, a bit width converter, a coding module and an LVDS transmission driver. The back board bus data to be transmitted reach the data transmission buffer memory module, and the parallel data in the buffer memory is converted into a 32bit parallel data code stream by the code stream converter; converting the 32bit data code stream into an 8bit byte code stream through a bit width converter; the encoding module encodes the 8-bit byte code stream and converts the 8-bit byte code stream into a 10-bit LVDS code stream; and finally, converting the 10bit LVDS code stream into a serial LVDS differential signal with a clock by an LVDS transmitting driver for transmitting.
For the LVDS data receiving functional unit, the content includes an LVDS receiving driver, a decoding module, a bit width converter, a code stream converter, and a data receiving buffer module. The serial LVDS differential signals are converted into 10bit LVDS code streams through an LVDS driver; then the decoding module converts the 10bit LVDS code stream into an 8bit byte code stream; converting the 8bit byte code stream into a 32bit data code stream through a bit width converter; and then the code stream converter converts the 32bit data code stream into 32bit parallel backboard bus data which is stored in the data receiving buffer module for being read by a processor of a receiving board card.
The data sending buffer module and the data receiving buffer module are jointly realized by a control IP core of the BRAM and a block_memory storage IP core in the FPGA and are used for temporarily buffering and managing parallel backboard bus data which are required to be sent or received by each board card processor.
The code stream converter is realized by a FIFO generator IP card of the FPGA, and mainly completes the conversion of parallel FIFO bus data and 32bit data code streams in the two functional units of transmission and reception.
The bit width converter is realized by an axis_ dwidth _converter IP card of the FPGA, and mainly completes the conversion of a 32bit data code stream and an 8bit byte code stream in a transmitting and receiving two functional units.
The coding module and the decoding module adopt an 8B/10B high-speed serial bus coding mechanism to realize the mutual conversion of a 10bit LVDS code stream and an 8bit byte code stream.
The LVDS receiving driver and the LVDS transmitting driver are respectively configured by SelectIO interfaces in the FPGA, so that the conversion from LVDS differential level signals to 10bit LVDS code stream data is realized.
The utility model is described in further detail below with reference to the accompanying drawings.
Fig. 1 is a functional schematic diagram of an LVDS signal conversion device. The LVDS signal conversion device is positioned on the board, when the board 1 is used as a transmitting end to transmit data to the board 2, a transmitting functional unit of the LVDS signal conversion device in the board 1 processes data of a data bus, an address bus and a control bus, converts the data into LVDS signals and outputs the LVDS signals for a receiving functional unit of the board 2 to read; the receiving function unit of the board card 2 picks up serial LVDS differential level signals, and the serial LVDS differential level signals are converted into readable bus data by the LVDS signal conversion device for the main function module to use. When the board 2 serves as a transmitting end to transmit data to the board 1, the principle is the same.
Fig. 2 is a schematic diagram of an LVDS signal conversion device. The LVDS signal conversion device comprises an LVDS transmitting driver, an LVDS receiving driver, a coding module, a decoding module, a bit width converter, a code stream converter, a data transmitting buffer module and a data receiving buffer module. The data transmission buffer module, the code stream converter, the bit width converter, the coding module and the LVDS transmission driver are sequentially connected, so that the transmission function of converting parallel bus data into serial LVDS differential level signals is realized; the LVDS receiving driver, the decoding module, the bit width converter, the code stream converter and the data receiving buffer module are sequentially connected, so that the function of converting serial LVDS differential level signals into parallel bus data is realized.
The LVDS transmitting driver converts serial LVDS differential level signals into 10bit LVDS parallel code streams; the LVDS receiving driver converts the 10bit LVDS parallel code stream into a serial LVDS differential level signal.
The LVDS transmitting driver and the LVDS receiving driver both adopt SelectIO IP cores of the FPGA, an interface is set as LVDS_25 level standard, DDR mode clock is selected, and serialization factor is set to be 10. Setting the following clock as 600MHz, the parallel clock as 120MHz, the pattern value as 0xe9, and waiting for the synchronization of the transmitting and receiving end to realize the data receiving and transmitting function.
The coding module recognizes the 10bit control K code according to the 8b/10b high-speed serial bus coding principle, searches a code stream data packet, and converts the 10bit LVDS parallel code stream into an 8bit character code stream; the decoding module converts the 8bit character code stream into a 10bit LVDS parallel code stream according to the 8b/10b high-speed serial bus coding principle, and generates a 10bit control K code to control the transmission of code stream data packets.
The bit width converter adopts an axis_ dwidth _converter IP core of the FPGA to complete the mutual conversion between an 8-bit byte code stream and a 32-bit data code stream.
The code stream converter adopts vivado self FIFO generator IP core to write 32bit code stream into FIFO, and changes the 32bit parallel data. The S end of the IP core is a 32bit code stream, and the M end is a 32bit parallel data area of the FIFO end.
The data sending buffer module and the data receiving buffer module are jointly realized by a control IP core and a block_memory storage IP core of the BRAM. The open space of the data buffer area in the program is 32KB, and the data is stored in the FIFO and can be read and written by the processor software. For the data transmission buffer module, the processor writes the information such as 32bit bus data or control command to be transmitted into the buffer area, and the information is acquired and converted by the LVDS conversion device; for the data receiving buffer module, the LVDS conversion device stores the converted 32-bit parallel data in a data buffer area for being read by processor software.
In summary, the LVDS signal conversion device for the parallel backboard bus communication mode provided by the utility model adopts the hardware description language on the FPGA, so that the conversion from parallel bus data to serial LVDS differential level signals is realized, and the data communication between boards in the device can be performed at a higher speed. Meanwhile, the number of pins required by the external connector of the board card is greatly reduced, and PCB wiring resources are saved.
Claims (6)
1. An LVDS signal conversion device for parallel backplane bus communication, wherein the LVDS signal conversion device is located on each board, and the LVDS signal conversion device includes: the LVDS data transmitting unit and the LVDS data receiving unit, wherein the LVDS data transmitting unit comprises: the LVDS transmitting device comprises an LVDS transmitting driver, a first code stream converter, a first bit width converter, a coding module and a data transmitting buffer module; the LVDS data receiving unit includes: the LVDS receiving driver, the decoding module, the second bit width converter, the second code stream converter and the data receiving buffer module;
The output end of the main functional module of the first board card is connected with the input end of the data transmission buffer module through a 32-bit parallel data bus and a plurality of control buses respectively; the output end of the data transmission buffer module is connected with the input end of the first code stream converter through a 32-bit parallel data bus; the output end of the first code stream converter is connected with the input end of the first bit width converter through a serial data bus; the output end of the first bit width converter is connected with the input end of the coding module through a serial data bus; the output end of the coding module is connected with the input end of the transmitting driver through a serial data bus; the output end of the LVDS transmitting driver is connected with the input end of the LVDS receiving driver of the second board card through an LVDS serial differential bus;
The output end of the LVDS transmitting driver of the second board card is connected with the input end of the LVDS receiving driver of the first board card through an LVDS serial differential bus; the output end of the LVDS receiving driver is connected with the input end of the decoding module through a serial data bus; the output end of the decoding module is connected with the input end of the second bit width converter through a serial data bus; the output end of the second bit width converter is connected with the input end of the second code stream converter through a serial data bus; the output end of the second code stream converter is connected with the data receiving buffer module through a 32-bit parallel data bus, and the output end of the data receiving buffer module is connected with the input end of the main function module of the first board card through a 32-bit parallel data bus and a plurality of control buses respectively.
2. The LVDS signal conversion device according to claim 1, wherein the LVDS transmitting driver and the LVDS receiving driver are SelectIO IP cores.
3. The LVDS signal conversion device of claim 1, wherein the first bit-width converter and the second bit-width converter are axis_ dwidth _converter IP cores.
4. The LVDS signal conversion device according to claim 1, wherein the first code stream converter and the second code stream converter are fifo_generator IP cores.
5. The LVDS signal conversion device according to claim 4, wherein the fifo_generator IP core of the first and second code stream converters has an S-terminal of 32bit code stream and an M-terminal of 32bit parallel data area.
6. The LVDS signal conversion device for parallel backplane bus communication according to claim 1, wherein the data sending buffer module and the data receiving buffer module each include a control IP core and a block_memory storage IP core of BRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322637363.3U CN221008254U (en) | 2023-09-27 | 2023-09-27 | LVDS signal conversion device for parallel backboard bus communication mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322637363.3U CN221008254U (en) | 2023-09-27 | 2023-09-27 | LVDS signal conversion device for parallel backboard bus communication mode |
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| Publication Number | Publication Date |
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| CN221008254U true CN221008254U (en) | 2024-05-24 |
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| CN202322637363.3U Active CN221008254U (en) | 2023-09-27 | 2023-09-27 | LVDS signal conversion device for parallel backboard bus communication mode |
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2023
- 2023-09-27 CN CN202322637363.3U patent/CN221008254U/en active Active
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