CN220913640U - Communication protocol conversion device for CAN bus - Google Patents
Communication protocol conversion device for CAN bus Download PDFInfo
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- CN220913640U CN220913640U CN202322485094.3U CN202322485094U CN220913640U CN 220913640 U CN220913640 U CN 220913640U CN 202322485094 U CN202322485094 U CN 202322485094U CN 220913640 U CN220913640 U CN 220913640U
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Abstract
The utility model provides a communication protocol conversion device for CAN bus, comprising: the device comprises a processor, a filtering unit, a crystal oscillator unit, a JTAG interface unit and a CAN transceiver unit arranged between the processor and a CAN bus and used for converting interface level; the current input end of the processor is connected with input current, the filtering unit is arranged on a circuit for inputting the current, the clock signal input end of the processor is connected with the clock signal output end of the crystal oscillator unit, the instruction input end of the processor is connected with the instruction output end of the JTAG interface unit, and the instruction output end of the processor is connected with the instruction input end of the JTAG interface unit. The utility model provides a communication protocol conversion device for a CAN bus, which is formed by arranging a CAN receiving and transmitting unit at a joint of the CAN bus, a processor U1, a crystal oscillator unit, a JTAG interface unit and a filtering unit, and the communication protocol conversion device for the CAN bus is used for completing data conversion between two CAN nodes through the CAN receiving and transmitting unit.
Description
Technical Field
The utility model relates to the technical field of communication, in particular to a communication protocol conversion device for a CAN bus.
Background
At present, bus communication is increasingly applied to communication technology.
The common serial communication has RS-485, but the RS-485 bus communication network is a master-slave distributed control system, the real-time communication cannot be carried out, the fault tolerance and error detection capability of the system are set through software, and when two different buses are communicated with each other, the incompatibility phenomenon caused by different parameters between the two buses often occurs.
Accordingly, it is necessary to provide a communication protocol conversion device for CAN bus to solve the above-mentioned problems.
Disclosure of utility model
The utility model provides a communication protocol conversion device for a CAN bus, which solves the problems that an RS-485 bus communication network in the prior art cannot carry out real-time communication and the two different buses are incompatible due to different parameters when the two different buses communicate with each other.
In order to solve the above technical problems, the present utility model provides a communication protocol conversion device for CAN bus, including:
The device comprises a processor, a filtering unit, a crystal oscillator unit, a JTAG interface unit and a CAN transceiver unit arranged between the processor and a CAN bus and used for converting interface level;
The current input end of the processor is connected with input current, the filtering unit is arranged on a circuit of the input current, the clock signal input end of the processor is connected with the clock signal output end of the crystal oscillator unit, the instruction input end of the processor is connected with the instruction output end of the JTAG interface unit, and the instruction output end of the processor is connected with the instruction input end of the JTAG interface unit;
The voltage regulator first capacitor end of the processor is connected with the first end of the first capacitor, the voltage regulator second capacitor end of the processor is connected with the first end of the second capacitor, the second end of the second capacitor is connected with the second end of the first capacitor, the second end of the second capacitor is connected with digital ground, the battery power supply end of the processor is connected with the first end of the third capacitor, the second end of the third capacitor is connected with digital ground, the analog power supply end of the processor is connected with the fourth capacitor and the fifth capacitor, the second end of the fifth capacitor is connected with the second end of the fourth capacitor, the starting end of the processor is connected with the first end of the first resistor, and the second end of the first resistor is respectively connected with the second end of the fifth capacitor, the second end of the fourth capacitor and the analog ground end of the processor.
Preferably, the filtering unit includes: the digital current input end of the processor, the first end of the seventh capacitor, the first end of the eighth capacitor, the first end of the ninth capacitor and the first end of the tenth capacitor are respectively connected with the first end of the sixth capacitor, the second end of the seventh capacitor, the second end of the eighth capacitor, the second end of the ninth capacitor and the second end of the tenth capacitor.
Preferably, the crystal oscillator unit comprises a clock chip, a power end of the clock chip is respectively connected with an input current and an eleventh capacitor, a second end of the eleventh capacitor is grounded, and a clock signal output end of the clock chip is connected with a clock signal input end of the processor.
Preferably, the CAN transceiver unit includes: the device comprises a level conversion chip, a twelfth capacitor, a second resistor and a third resistor, wherein a transmitting signal input end of the level conversion chip is connected with a CAN bus transmitting end of the processor, a receiving signal output end of the level conversion chip is connected with a CAN bus receiving end of the processor, a power end of the level conversion chip is connected with a first end of the twelfth capacitor, a grounding end of the level conversion chip is connected with a second end of the twelfth capacitor, an operating end of the level conversion chip is connected with a first end of the second resistor, a second end of the second resistor is connected with digital ground, a high-level end of the level conversion chip is connected with a first end of the third resistor, and a low-level end of the level conversion chip is connected with a second end of the third resistor.
Preferably, the level shift chip is of the type SN65HVD230.
Preferably, the JTAG interface unit includes: the connector is connected with the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor and the ninth resistor through wires respectively.
Compared with the related art, the communication protocol conversion device for the CAN bus has the following beneficial effects:
The utility model provides a communication protocol conversion device for a CAN bus, which is formed by arranging a CAN receiving and transmitting unit at the joint of the CAN bus, a processor U1, a crystal oscillator unit, a JTAG interface unit and a filtering unit, and finishes data conversion between two CAN nodes through the CAN receiving and transmitting unit, so that the outside of the CAN bus is not required to be connected with a CAN interface control chip any more, and meanwhile, test and debugging signals CAN be accessed through arranging the JTAG interface unit, so that the two CAN nodes have uniform communication protocols, are compatible with each other and CAN transmit data more quickly.
Drawings
Fig. 1 is a schematic structural diagram of a preferred embodiment of a communication protocol conversion device for CAN bus according to the present utility model;
FIG. 2 is a circuit diagram of a portion of the processor U1 shown in FIG. 1;
FIG. 3 is a circuit diagram of the filtering unit shown in FIG. 1;
FIG. 4 is a circuit diagram of the crystal oscillator unit shown in FIG. 1;
FIG. 5 is a circuit diagram of the CAN transceiver unit shown in FIG. 1;
fig. 6 is a circuit diagram of the JTAG interface unit shown in fig. 1.
Reference numerals in the drawings: c1, first capacitor, C2, second capacitor, C3, third capacitor, C4, fourth capacitor, C5, fifth capacitor, C6, sixth capacitor, C7, seventh capacitor, C8, eighth capacitor, C9, ninth capacitor, R1, first resistor, R2, second resistor, R3, third resistor, R4, fourth resistor, R5, fifth resistor, R6, sixth resistor, R7, seventh resistor, R8, eighth resistor, R9, ninth resistor, B1, clock chip, U1, processor, U2, level conversion chip, J1, connector.
Detailed Description
The utility model will be further described with reference to the drawings and embodiments.
Referring to fig. 1, fig. 2, fig. 3, fig. 4, fig. 5 and fig. 6 in combination, fig. 1 is a schematic structural diagram of a preferred embodiment of a communication protocol conversion device for CAN bus according to the present utility model;
FIG. 2 is a circuit diagram of a portion of the processor U1 shown in FIG. 1; FIG. 3 is a circuit diagram of the filtering unit shown in FIG. 1; FIG. 4 is a circuit diagram of the crystal oscillator unit shown in FIG. 1; FIG. 5 is a circuit diagram of the CAN transceiver unit shown in FIG. 1; fig. 6 is a circuit diagram of the JTAG interface unit shown in fig. 1. A CAN bus communication protocol conversion device comprising:
the device comprises a processor U1, a filtering unit, a crystal oscillator unit, a JTAG interface unit and a CAN transceiver unit which is arranged between the processor U1 and a CAN bus and used for converting interface level;
The current input end of the processor U1 is connected with input current, the filtering unit is arranged on a circuit of the input current, the clock signal input end (OSC pin) of the processor U1 is connected with the clock signal output end of the crystal oscillator unit, the instruction input end of the processor U1 is connected with the instruction output end of the JTAG interface unit, and the instruction output end of the processor U1 is connected with the instruction input end of the JTAG interface unit;
the voltage regulator first capacitor end (VCAP-1 pin) of the processor U1 is connected with the first end of the first capacitor C1, the voltage regulator second capacitor end (VCAP-2 pin) of the processor U1 is connected with the first end of the second capacitor C2, the second end of the second capacitor C2 is connected with the second end of the first capacitor C1, the second end of the second capacitor C2 is connected with digital ground, the battery power supply end (VBAT pin) of the processor U1 is connected with the first end of the third capacitor C3, the second end of the third capacitor C3 is connected with digital ground, the analog power supply end (VDDA pin) of the processor U1 is connected with the fourth capacitor C4 and the fifth capacitor C5, the second end of the fifth capacitor C5 is connected with the second end of the fourth capacitor C4, the starting end (BOOT pin) of the processor U1 is connected with the first end of the first resistor R1, and the second end of the second resistor R1 is connected with the analog ground end of the fourth capacitor C4 and the analog power supply end of the processor U1 is connected with the digital ground (VSSA) of the second end of the fourth capacitor C1.
The processor U1 adopts STM32F4 series chips, the STM32F4 series chips have two bxCAN (namely Basic Extended CAN) interfaces, the interfaces support CAN protocols 2.0A and 2.0B, and the STM32F4 series chips CAN efficiently process a large number of received messages with minimum CPU load.
The filtering unit includes: the first end of the sixth capacitor C6 is connected with the digital current input end (VDD pin) of the processor U1, the first end of the seventh capacitor C7, the first end of the eighth capacitor C8, the first end of the ninth capacitor C9 and the first end of the tenth capacitor C10, respectively, and the second end of the sixth capacitor C6 is connected with the digital ground end (VSS pin) of the processor U1, the second end of the seventh capacitor C7, the second end of the eighth capacitor C8, the second end of the ninth capacitor C9 and the second end of the tenth capacitor C10, respectively.
The crystal oscillator unit comprises a clock chip B1 (VCC pin), wherein a power end of the clock chip B1 is respectively connected with an input current and an eleventh capacitor C11, a second end of the eleventh capacitor C11 is grounded, a clock signal output end (C1 KOut pin) of the clock chip B1 is connected with a clock signal input end (OSC-IN pin) of the processor U1, and a ground end (GND pin) of the clock chip B1 is grounded.
The CAN transceiver unit comprises: the level conversion chip U2, twelfth electric capacity C12, second resistance R2 and third resistance R3, the transmission signal input (the D pin) of level conversion chip U2 with the CAN bus transmitting terminal (CAN 1-TX pin) of treater U1 is connected, the received signal output (the R pin) of level conversion chip U2 with the CAN bus receiving terminal (CAN 1-RX pin) of treater U1, the power end (VCC pin) of level conversion chip U2 with the first end of twelfth electric capacity C12 is connected, the ground terminal (GND pin) of level conversion chip U2 and the second end of twelfth electric capacity C12 are connected, the operation end (RS pin) of level conversion chip U2 and the first end of second resistance R2 are connected, the second termination digital ground of second resistance R2, the high level end (CANH pin) of level conversion chip U2 and the first end of third resistance R3 are connected, the low level end (CANH pin) of level conversion chip U2 and the third resistance NL 3 are connected.
The model of the level shift chip U2 is SN65HVD230.
The level conversion chip U2 converts the CAN differential signal received from the CAN bus into a single-ended signal, and transmits the converted single-ended signal to the CAN bus receiving end (CAN 1-RX pin) of the processor U1 through the receiving signal output end (R pin), and similarly, the processor U1 may also transmit the single-ended signal to be transmitted to the level conversion chip U2 through the CAN bus transmitting end (CAN 1-TX pin), and the transmitting signal input end (D pipe teaching) of the level conversion chip U2 receives the single-ended signal and converts the received single-ended signal into a standard CAN differential signal to transmit to the CAN bus.
The JTAG interface unit includes: the connector J1 is connected with the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 through wires, and the connector J1 is connected with the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 through wires.
R4 is a pull-down resistor, which ensures that the pin is normally at a low level, and R5-R9 are pull-up resistors, which ensure that the pin is normally at a high level.
Compared with the related art, the communication protocol conversion device for the CAN bus has the following beneficial effects:
The utility model provides a communication protocol conversion device for a CAN bus, which is characterized in that a CAN receiving and transmitting unit is arranged at a joint of the CAN bus, a processor U1, a crystal oscillator unit, a JTAG interface unit and a filtering unit are used for completing data conversion between two CAN nodes through the CAN receiving and transmitting unit, so that the outside of the CAN bus is not required to be connected with a CAN interface control chip; meanwhile, by the aid of the JTAG interface unit, test and debugging signals CAN be accessed, unified communication protocols exist between two CAN nodes, and the two CAN nodes are compatible with each other and CAN transmit data more quickly. The utility model has simple circuit, stable effect and convenient maintenance.
The foregoing description is only illustrative of the present utility model and is not intended to limit the scope of the utility model, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present utility model.
Claims (6)
1. A communication protocol conversion device for a CAN bus, comprising:
The device comprises a processor, a filtering unit, a crystal oscillator unit, a JTAG interface unit and a CAN transceiver unit arranged between the processor and a CAN bus and used for converting interface level;
The current input end of the processor is connected with input current, the filtering unit is arranged on a circuit of the input current, the clock signal input end of the processor is connected with the clock signal output end of the crystal oscillator unit, the instruction input end of the processor is connected with the instruction output end of the JTAG interface unit, and the instruction output end of the processor is connected with the instruction input end of the JTAG interface unit;
The voltage regulator first capacitor end of the processor is connected with the first end of the first capacitor, the voltage regulator second capacitor end of the processor is connected with the first end of the second capacitor, the second end of the second capacitor is connected with the second end of the first capacitor, the second end of the second capacitor is connected with digital ground, the battery power supply end of the processor is connected with the first end of the third capacitor, the second end of the third capacitor is connected with digital ground, the analog power supply end of the processor is connected with the fourth capacitor and the fifth capacitor, the second end of the fifth capacitor is connected with the second end of the fourth capacitor, the starting end of the processor is connected with the first end of the first resistor, and the second end of the first resistor is respectively connected with the second end of the fifth capacitor, the second end of the fourth capacitor and the analog ground end of the processor.
2. The CAN bus communication protocol conversion device according to claim 1, wherein the filtering unit includes: the digital current input end of the processor, the first end of the seventh capacitor, the first end of the eighth capacitor, the first end of the ninth capacitor and the first end of the tenth capacitor are respectively connected with the first end of the sixth capacitor, the second end of the seventh capacitor, the second end of the eighth capacitor, the second end of the ninth capacitor and the second end of the tenth capacitor.
3. The CAN bus communication protocol conversion device of claim 1, wherein the crystal oscillator unit comprises a clock chip, a power supply terminal of the clock chip is connected with an input current and an eleventh capacitor, a second terminal of the eleventh capacitor is grounded, and a clock signal output terminal of the clock chip is connected with a clock signal input terminal of the processor.
4. The CAN bus communication protocol conversion device according to claim 1, wherein the CAN transceiver unit includes: the device comprises a level conversion chip, a twelfth capacitor, a second resistor and a third resistor, wherein a transmitting signal input end of the level conversion chip is connected with a CAN bus transmitting end of the processor, a receiving signal output end of the level conversion chip is connected with a CAN bus receiving end of the processor, a power end of the level conversion chip is connected with a first end of the twelfth capacitor, a grounding end of the level conversion chip is connected with a second end of the twelfth capacitor, an operating end of the level conversion chip is connected with a first end of the second resistor, a second end of the second resistor is connected with digital ground, a high-level end of the level conversion chip is connected with a first end of the third resistor, and a low-level end of the level conversion chip is connected with a second end of the third resistor.
5. The CAN bus communication protocol conversion device according to claim 4, wherein the level conversion chip is of a model SN65HVD230.
6. The CAN bus communication protocol conversion device according to claim 1, wherein the JTAG interface unit comprises: the connector is connected with the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor and the ninth resistor through wires respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322485094.3U CN220913640U (en) | 2023-09-13 | 2023-09-13 | Communication protocol conversion device for CAN bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322485094.3U CN220913640U (en) | 2023-09-13 | 2023-09-13 | Communication protocol conversion device for CAN bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220913640U true CN220913640U (en) | 2024-05-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322485094.3U Active CN220913640U (en) | 2023-09-13 | 2023-09-13 | Communication protocol conversion device for CAN bus |
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| Country | Link |
|---|---|
| CN (1) | CN220913640U (en) |
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2023
- 2023-09-13 CN CN202322485094.3U patent/CN220913640U/en active Active
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