CN220894539U - Satellite signal receiving system - Google Patents
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- CN220894539U CN220894539U CN202322197733.6U CN202322197733U CN220894539U CN 220894539 U CN220894539 U CN 220894539U CN 202322197733 U CN202322197733 U CN 202322197733U CN 220894539 U CN220894539 U CN 220894539U
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Abstract
The utility model discloses a satellite signal receiving system. The satellite signal receiving system includes: the satellite signal acquisition system and the digital signal processing development board; the satellite signal acquisition system comprises: a radio frequency signal processing circuit and a connector; the radio frequency signal processing circuit is connected with the digital signal processing development board through the connector, the received satellite signals are processed through the radio frequency signal processing circuit to obtain digital intermediate frequency signals, and the digital intermediate frequency signals are transmitted to the digital signal processing development board through the connector, so that the digital signal processing development board performs signal processing on the digital intermediate frequency signals. The utility model solves the problems that the satellite navigation receiver in the prior art cannot output the digital intermediate frequency signal and the debugging difficulty and the hardware cost are increased due to the fact that the satellite navigation receiver is used as integrated equipment, thereby reducing the hardware cost and being convenient for debugging and use.
Description
Technical Field
The present utility model relates to the field of communications technologies, and in particular, to a satellite signal receiving system.
Background
With the gradual operation of the global positioning system (Global Positioning System, GPS), the global navigation satellite system (GLONASS), the beidou navigation system and the galileo navigation system, the multimode multi-frequency satellite navigation receiving terminal has become a major trend and research hotspot for the technical development of satellite navigation receivers.
On the one hand, the radio frequency front end module is used for amplifying, filtering, down-converting and digitizing satellite signals received by the antenna in the satellite navigation receiver, and providing a control clock with high stability for subsequent baseband processing and navigation resolving, and the multi-frequency compatibility of the radio frequency front end module directly determines the signal frequency band which can be processed by the receiver, and the performance of the radio frequency front end module also has important influence on the final performance of the receiver.
On the other hand, research and verification of advanced baseband signal processing technology of satellite navigation receivers requires support of digital intermediate frequency signals, and the current receiver cannot directly output the digital intermediate frequency signals. In addition, the radio frequency front-end module and the module for baseband processing and navigation settlement in the prior art are integrated together, namely, the satellite navigation receiver is integrated equipment, so that the debugging difficulty and the hardware cost are increased.
Disclosure of utility model
The utility model provides a satellite signal receiving system, which aims to solve the problems that a receiver in the prior art cannot directly output a digital intermediate frequency signal and the debugging difficulty and the hardware cost are increased due to the fact that a satellite navigation receiver is used as integrated equipment.
According to an aspect of the present utility model, there is provided a satellite signal receiving system including: the satellite signal acquisition system and the digital signal processing development board; wherein, satellite signal acquisition system includes: a radio frequency signal processing circuit and a connector;
The radio frequency signal processing circuit is connected with the digital signal processing development board through the connector, and is used for processing the received satellite signals to obtain intermediate frequency signals through the radio frequency signal processing circuit, and transmitting the intermediate frequency signals to the digital signal processing development board through the connector so that the digital signal processing development board can perform signal processing on the intermediate frequency signals.
In one embodiment, the radio frequency signal processing circuit includes at least two radio frequency front end chips; each radio frequency front end chip comprises two signal processing paths for processing satellite signals of different satellite systems.
In an embodiment, each of the radio frequency front end chips includes: zero intermediate frequency receiver architecture and low intermediate frequency receiver architecture.
In an embodiment, each of the radio frequency front end chips covers the following bands: E5/L5, L2, E6, E1/L1 bands.
In one embodiment, the rf front-end chip supports satellite signals of at least one of the following satellite systems: GPS, GLONASS, galileo, QZSS, IRNSS and Beidou navigation satellite system.
In an embodiment, the satellite signal acquisition system further comprises: a full-band antenna and a splitter;
The splitter is respectively connected with each radio frequency front end chip, and is used for separating the satellite signals of various frequency bands of different satellite systems into satellite signals of a single frequency band through the splitter after receiving the satellite signals through the full-frequency band antenna, and outputting the satellite signals to different signal processing paths of the radio frequency front end chips.
In an embodiment, the satellite signal acquisition system further comprises: a power supply module and a clock circuit;
The input end of the power supply module is connected with the digital signal processing development board through the connector and is used for supplying power to the power supply module;
The output end of the power supply module is respectively connected with the radio frequency signal processing circuit and the clock circuit and is used for respectively supplying power to the radio frequency signal processing circuit and the clock circuit.
In one embodiment, the power supply module includes a frequency oscillator and a reference voltage regulator, and outputs a voltage of 2.85V to the radio frequency signal processing circuit through one output terminal of the power supply module, and outputs a voltage of 3.3V to the clock circuit directly through the other output terminal of the power supply module.
In one embodiment, the power module employs two MAX8510 chips.
In one embodiment, the rf front-end chip is a MAX2771 chip.
According to the technical scheme, the radio frequency signal processing circuit is connected with the digital signal processing development board through the connector, the received satellite signals are processed through the radio frequency signal processing circuit to obtain the digital intermediate frequency signals, and the digital intermediate frequency signals are transmitted to the digital signal processing development board through the connector, so that the problems that the satellite navigation receiver in the prior art cannot output the digital intermediate frequency signals, and the debugging difficulty and the hardware cost are increased due to the fact that the satellite navigation receiver is used as integrated equipment are solved, the hardware cost is reduced, and the debugging and the use are facilitated.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a satellite signal receiving system according to an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of a zero intermediate frequency receiver according to an embodiment of the present utility model;
fig. 3 is a schematic structural diagram of a low intermediate frequency receiver according to an embodiment of the present utility model;
Fig. 4 is a block diagram of another satellite signal receiving system according to an embodiment of the present utility model;
FIG. 5 is a schematic circuit diagram of a power module according to an embodiment of the present utility model;
FIG. 6 is a schematic diagram of a clock circuit according to an embodiment of the present utility model;
fig. 7 is a schematic circuit diagram of a radio frequency front end chip according to an embodiment of the present utility model.
Detailed Description
In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In an embodiment, fig. 1 is a block diagram of a satellite signal receiving system according to an embodiment of the present utility model, where the embodiment is applicable to a situation where a digital intermediate frequency signal is output at low cost, and the satellite signal receiving system may be implemented in a hardware form. Among them, the satellite signal receiving system may also be called a satellite navigation receiver. As shown in fig. 1, the satellite signal receiving system includes: a satellite signal acquisition system 10 and a digital signal processing development board 20; wherein, the satellite signal acquisition system 10 comprises: a radio frequency signal processing circuit 101 and a connector 102;
The rf signal processing circuit 101 is connected to the digital signal processing development board 20 through the connector 102, processes the received satellite signal through the rf signal processing circuit 101 to obtain a digital intermediate frequency signal, and transmits the digital intermediate frequency signal to the digital signal processing development board 20 through the connector 102, so that the digital signal processing development board 20 performs signal processing on the digital intermediate frequency signal.
It should be noted that the satellite signal acquisition system 10 may also be referred to as a radio frequency front-end module, and is configured to amplify, filter, downconvert, and digitize a received satellite signal to obtain a digital intermediate frequency signal. In designing the circuit board of the satellite signal acquisition system 10, a double-sided board may be used to reduce the cost of the single board. Illustratively, the circuit board of the satellite signal acquisition system 10 may have a board thickness of 1.2mm. In an embodiment, the connector 102 may be a2×20 2.54mm pitch common connector, for example, the connector 102 directly uses dupont wires, and may be connected to the GPIO port of the digital signal processing and development board 20, so that the hardware cost may be reduced. In an embodiment, the digital signal processing development board 20 may include a field programmable gate array (Field Programmable GATE ARRAY, FPGA) and a random access memory (Random Access Memory, RAM), that is, may have signal processing capability. The digital signal processing development board 20 is also used for position resolving and baseband processing, i.e. the digital signal processing development board 20 may also be referred to as a position resolving platform for resolving a position for positioning based on received satellite signals.
In an embodiment, after the connector 102 is connected with the digital signal processing development board 20, a satellite signal receiving system can be directly formed, and the baseband signal can be processed and the performance of the digital intermediate frequency signal can be verified, so that convenience is provided. Meanwhile, the satellite signal acquisition system and the digital signal processing development board for processing the digital intermediate frequency signals corresponding to the satellite signals are separated, so that the hardware cost of the satellite signal receiving system is reduced, and the satellite signal acquisition system and the satellite signal receiving system are convenient to debug and use.
According to the technical scheme, the radio frequency signal processing circuit is connected with the digital signal processing development board through the connector, the received satellite signals are processed through the radio frequency signal processing circuit to obtain digital intermediate frequency signals, the digital intermediate frequency signals are transmitted to the digital signal processing development board through the connector, the problems that in the prior art, the satellite navigation receiver cannot output the digital intermediate frequency signals, and the debugging difficulty and the hardware cost are increased due to the fact that the satellite navigation receiver is used as integrated equipment are solved, and therefore the hardware cost is reduced, and debugging and use are facilitated
In one embodiment, the radio frequency signal processing circuit includes at least two radio frequency front end chips; each radio frequency front end chip comprises two signal processing paths for processing satellite signals of different satellite systems. In an embodiment, each rf front-end chip includes at least two signal processing paths for processing satellite signals of different satellite systems. The rf signal processing circuit includes two rf front-end chips, and each rf front-end chip includes two signal processing paths, that is, the rf signal processing circuit includes four signal processing paths for respectively processing satellite signals corresponding to four satellite systems, that is, a GPS system, a GLONASS system, a beidou navigation system, and a galileo navigation system.
A signal portion and a power portion are included in each radio frequency front end chip. In general, a radio frequency receiver framework in a radio frequency front end chip may include: the system comprises five structures of a superheterodyne receiver, a low intermediate frequency receiver, a zero intermediate frequency receiver, an image rejection receiver and a digital intermediate frequency receiver. The five receiver structures have advantages and disadvantages, and various receiver structures are flexibly adopted according to different application occasions, so that the requirements of various applications in wireless communication can be met. In one embodiment, the radio frequency signals received by the full band antenna are processed using a zero intermediate frequency receiver architecture and a low intermediate frequency receiver architecture. It may be understood that each of the radio frequency front end chips includes: zero intermediate frequency receiver architecture and low intermediate frequency receiver architecture. The zero intermediate frequency receiver is also called as a direct conversion receiver (Direct conversion receiver).
Fig. 2 is a schematic structural diagram of a zero intermediate frequency receiver according to an embodiment of the present utility model. The structure of which is shown in figure 2. The zero intermediate frequency receiver selects the same frequency as the local oscillation signal and the radio frequency signal, in fig. 2, LO is the local oscillation signal, in the zero intermediate frequency receiver structure, the mixer directly down-converts the required frequency band into the frequency band with if=0, and then directly processes the multi-baseband signal. Since if=0, the intermediate frequency filter is replaced by a low pass filter, which is easier to implement on-chip. Since the zero intermediate frequency architecture receiver omits intermediate frequency stages, it has many advantages over superheterodyne receivers. The zero intermediate frequency receiver does not need a mirror filter, so that the structure of the receiver is simplified; the intermediate frequency of the zero intermediate frequency receiver is zero, so that only a low-pass filter which is easy to integrate is needed, and the energy consumption and the cost are greatly reduced.
Fig. 3 is a schematic structural diagram of a low intermediate frequency receiver according to an embodiment of the present utility model. The structure of which is shown in figure 3. For a receiver with a low intermediate frequency structure, the intermediate frequency is relatively low, and the structure is similar to that of a receiver with a direct conversion structure, except that an intermediate frequency signal is output after the frequency conversion. Compared with a zero intermediate frequency receiver, the low-frequency interference such as direct current offset is overcome, and compared with a superheterodyne receiver, a high-frequency band-pass filter is not needed, so that the receiver becomes one of the selection structures of the design of the integrated receiver.
In fig. 2 and 3, the BPF refers to a Band pass filter (Band PASS FILTER), the LPF refers to a Low pass filter (Low PASS FILTER), the LNA refers to a Low noise amplifier (Low Noise Amplifier), and the AGC refers to automatic gain control (Automatic Gain Control).
In an embodiment, each of the radio frequency front end chips covers the following bands: E5/L5, L2, E6, E1/L1 bands.
In one embodiment, the rf front-end chip supports satellite signals of at least one of the following satellite systems: GPS, GLONASS, galileo, QZSS, IRNSS and Beidou navigation satellite system.
In one embodiment, the rf front-end chip may be a MAX2771 chip. In an embodiment, the rf front-end chip may use a MAX2771 chip, which is a multi-band general-purpose chip and may be used as an rf front-end chip in a receiver system. The single chip can cover E5/L5, L2, E6 and E1/L1 wave bands, and can support GPS, GLONASS, galileo, QZSS, IRNSS and Beidou navigation satellite systems. Meanwhile, the MAX2771 chip can be configured through SPI, and can select between a zero intermediate frequency receiver structure and a low intermediate frequency receiver structure. And the total noise figure of the chip is as low as 1.4dB.
In an embodiment, fig. 4 is a block diagram of another satellite signal receiving system according to an embodiment of the present utility model. The present embodiment further describes the configuration of the satellite signal receiving system based on the above embodiments. As shown in fig. 4, the satellite signal acquisition system 10 of the present embodiment further includes: full band antenna 103, splitter 104, power module 105, and clock circuit 106. An LNA107 is also included in the satellite signal acquisition system 10 for improving the signal-to-noise ratio of the satellite signal output.
The splitter 104 is respectively connected to each of the rf front-end chips in the rf signal processing circuit 101, and is configured to split, after receiving satellite signals through the full-band antenna 103, satellite signals in multiple frequency bands of different satellite systems into satellite signals in a single frequency band through the splitter 104, and output the satellite signals to different signal processing paths of the rf front-end chips. The full-band antenna 103 refers to an antenna system capable of receiving each frequency band, and may also be referred to as a full-mode antenna; the splitter 104 is configured to split the multiple frequency band signals input by the full-band antenna 103 into satellite signals with a single frequency band, and output the satellite signals with the single frequency band to one of the signal processing paths of the rf front-end chip. It will be appreciated that each signal processing path in the rf front-end chip is used to process satellite signals of one frequency band. Of course, in the full-band antenna 103, a plurality of satellite systems are input, and a satellite signal of one frequency band in each satellite system is input to the splitter 104, and the splitter 104 may input the satellite signal of each satellite system to a different signal processing path, so as to process the satellite signal of each satellite system through the signal processing path, thereby obtaining a corresponding digital intermediate frequency signal or an analog intermediate frequency signal.
Under the condition that the radio frequency front end chip does not have the capability of converting the analog signal into the digital signal, an analog-to-digital converter (Analog To Digital Converter, ADC) can be additionally arranged between the radio frequency signal processing circuit and the digital signal processing development board so as to convert the analog intermediate frequency signal output by the radio frequency front end chip into the digital intermediate frequency signal and transmit the digital intermediate frequency signal to the digital signal processing development board. The ADC can be additionally arranged between the radio frequency signal processing circuit and the connector, and can also be additionally arranged between the connector and the digital signal processing development board.
In one embodiment, the input end of the power module 105 is connected to the digital signal processing development board 20 through the connector 102, so as to supply power to the power module 105;
The output end of the power module 105 is respectively connected with the radio frequency signal processing circuit 101 and the clock circuit 106, and is used for respectively supplying power to the radio frequency signal processing circuit 101 and the clock circuit 106. In an embodiment, the digital signal processing development board 20 may be externally connected with a power supply, and supply power to the power module 105 through a connector; and then supplies power to the radio frequency signal processing circuit 101 and the clock circuit 106 through the output terminals of the power supply module 105, respectively. In an embodiment, the clock circuit 106 may use an active temperature compensation crystal oscillator, so that the clock circuit 106 may provide a more accurate reference clock, and the accuracy of the clock circuit 106 is guaranteed to be higher.
In one embodiment, the power supply module includes a frequency oscillator and a reference voltage regulator, and outputs a voltage of 2.85V to the radio frequency signal processing circuit through one output terminal of the power supply module, and outputs a voltage of 3.3V to the clock circuit directly through the other output terminal of the power supply module.
In one embodiment, the power module employs two MAX8510 chips. In an embodiment, a MAX8510 chip may be used as the power chip in the power module, and a voltage of 2.85V may be constantly output. The radio frequency signal processing circuit can be designed by adopting a MAX8510EXK29+ power chip according to the electrical characteristics of the MAX2771 chip of the radio frequency front end chip. Wherein MAX8510EXK29+ is a low-dropout linear voltage regulator, and has the characteristics of ultra-low noise and low dropout; the high-efficiency voltage stabilizing circuit is composed of a fixed frequency oscillator and a reference voltage stabilizer, and can provide 120mA continuous output current by using the device with very few peripheral devices, wherein the voltage output is preset to be 2.85V when the device leaves a factory.
In an embodiment, fig. 5 is a schematic circuit diagram of a power module according to an embodiment of the utility model. As shown in fig. 5, the MAX8510 chip is used as the power supply chip in the power supply module, and the capacitors C1, C2, C3 and C4 in the MAX8510 chip are all peripheral circuit elements necessary for the power supply chip. Meanwhile, a voltage of 3.3V is input through an input terminal of the power chip, and a voltage of 2.8V is output through an output terminal.
In an embodiment, fig. 6 is a schematic circuit diagram of a clock circuit according to an embodiment of the utility model. As shown in fig. 6, D2 is an active temperature compensation crystal oscillator, and peripheral circuit elements necessary for C5 and C6 are all provided. And, directly provide 3.3V voltage for clock circuit through power module.
In an embodiment, fig. 7 is a schematic circuit diagram of a radio frequency front end chip according to an embodiment of the utility model. As shown in fig. 7, it is assumed that the rf front-end chip adopts a MAX2771 chip, and D3A and D3B are two parts of the MAX2771 chip, where D3A is a signal part, D3B is a power supply part, and all devices such as a capacitor, a resistor, and an inductor are necessary peripheral circuits.
It should be appreciated that various forms of the structures shown above may be used, with components being rearranged, added, or deleted. For example, the components and structures described in the present utility model may be combined in any manner so long as the desired results according to the technical aspects of the present utility model can be achieved, and the present utility model is not limited herein.
The above embodiments do not limit the scope of the present utility model. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the scope of the present utility model.
Claims (10)
1. A satellite signal receiving system, comprising: the satellite signal acquisition system and the digital signal processing development board; wherein, satellite signal acquisition system includes: a radio frequency signal processing circuit and a connector;
The radio frequency signal processing circuit is connected with the digital signal processing development board through the connector, processes the received satellite signals through the radio frequency signal processing circuit to obtain digital intermediate frequency signals, and transmits the digital intermediate frequency signals to the digital signal processing development board through the connector so that the digital signal processing development board performs signal processing on the digital intermediate frequency signals.
2. The satellite signal receiving system of claim 1, wherein the radio frequency signal processing circuit comprises at least two radio frequency front end chips; each radio frequency front end chip comprises two signal processing paths for processing satellite signals of different satellite systems.
3. The satellite signal receiving system of claim 2, wherein each of the radio frequency front end chips comprises: zero intermediate frequency receiver architecture and low intermediate frequency receiver architecture.
4. The satellite signal receiving system of claim 2, wherein each of the radio frequency front end chips covers the following bands: E5/L5, L2, E6, E1/L1 bands.
5. The satellite signal receiving system of claim 2, wherein the radio frequency front-end chip supports satellite signals of at least one of the following satellite systems: GPS, GLONASS, galileo, QZSS, IRNSS and Beidou navigation satellite system.
6. The satellite signal receiving system of claim 2, wherein the satellite signal acquisition system further comprises: a full-band antenna and a splitter;
The splitter is respectively connected with each radio frequency front end chip, and is used for separating the satellite signals of various frequency bands of different satellite systems into satellite signals of a single frequency band through the splitter after receiving the satellite signals through the full-frequency band antenna, and outputting the satellite signals to different signal processing paths of the radio frequency front end chips.
7. The satellite signal receiving system of claim 1, wherein the satellite signal acquisition system further comprises: a power supply module and a clock circuit;
The input end of the power supply module is connected with the digital signal processing development board through the connector and is used for supplying power to the power supply module;
The output end of the power supply module is respectively connected with the radio frequency signal processing circuit and the clock circuit and is used for respectively supplying power to the radio frequency signal processing circuit and the clock circuit.
8. The satellite signal receiving system of claim 7, wherein the power module includes a frequency oscillator and a reference voltage regulator, and wherein the voltage of 2.85V is output to the radio frequency signal processing circuit through one output terminal of the power module, and the voltage of 3.3V is output to the clock circuit directly through the other output terminal of the power module.
9. The satellite signal receiving system of claim 7, wherein the power module employs two MAX8510 chips.
10. The satellite signal receiving system of claim 2, wherein the radio frequency front-end chip is a MAX2771 chip.
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| CN202322197733.6U CN220894539U (en) | 2023-08-15 | 2023-08-15 | Satellite signal receiving system |
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| CN202322197733.6U CN220894539U (en) | 2023-08-15 | 2023-08-15 | Satellite signal receiving system |
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