CN220821061U - 4K eDP liquid crystal drive board based on SoC - Google Patents
4K eDP liquid crystal drive board based on SoC Download PDFInfo
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- CN220821061U CN220821061U CN202321425085.9U CN202321425085U CN220821061U CN 220821061 U CN220821061 U CN 220821061U CN 202321425085 U CN202321425085 U CN 202321425085U CN 220821061 U CN220821061 U CN 220821061U
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 50
- 238000004891 communication Methods 0.000 claims abstract description 17
- 238000012545 processing Methods 0.000 claims description 17
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- GJWAPAVRQYYSTK-UHFFFAOYSA-N [(dimethyl-$l^{3}-silanyl)amino]-dimethylsilicon Chemical group C[Si](C)N[Si](C)C GJWAPAVRQYYSTK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model discloses a 4KeDP liquid crystal drive board based on an SoC, which relates to the technical field of liquid crystal drive boards and comprises an SoC main control chip, an HDMI input unit, an eDP output unit, a USB communication unit, a power supply unit and a liquid crystal drive unit, wherein the HDMI input unit, the eDP output unit, the USB communication unit, the power supply unit and the liquid crystal drive unit are all electrically connected with the SoC main control chip, the power supply unit is electrically connected with the SoC main control chip and the liquid crystal drive unit, and the power supply unit is used for supplying power to the SoC main control chip, the HDMI input unit, the eDP output unit, the USB communication unit and the liquid crystal drive unit. The utility model has the advantages that: the 4KeDP liquid crystal driving board based on the SoC is provided, the reliability and the safety of video transmission are greatly improved, and the video driving board can be adapted to places with severe environments and severe safety requirements.
Description
Technical Field
The utility model relates to the technical field of liquid crystal driving boards, in particular to a 4K eDP liquid crystal driving board based on SoC.
Background
With the increase of the resolution of the display, the requirements on performance are improved, the data processing capacity is required to be greatly improved, and the requirements of the traditional single chip microcomputer and ARM chip are difficult to meet. Because the FPGA can process a large amount of parallel data at the same time, the design scheme of the liquid crystal display panel in the current mainstream adopts the FPGA as a control module, a logic circuit program is written in the FPGA to read and control, and HDMI video signals are received and transmitted and displayed on a display in real time.
The current mainstream 4K eDP liquid crystal drive board is designed by mostly adopting imported Xilinx and Intel FPGA as core control devices, and domestic FPGA has less application in this respect, so that the existing product has stronger dependence on imported FPGA chips. In addition, the traditional display screen driving interface mostly adopts an LVDS interface, is limited by LVDS speed, and is difficult to meet the display requirement of high resolution.
Disclosure of utility model
In order to solve the technical problems, the technical scheme provides the 4K eDP liquid crystal driving board based on the SoC, and the technical scheme solves the problem that the current mainstream 4K eDP liquid crystal driving board is mostly designed by adopting imported Xilinx and Intel FPGA as core control devices, so that domestic FPGA is less in application in the aspect, and the existing product has stronger dependence on imported FPGA chips. In addition, the traditional display screen driving interface mostly adopts an LVDS interface, is limited by LVDS speed, and is difficult to meet the display requirement of high resolution.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
The utility model provides a 4K eDP liquid crystal drive board based on SoC, includes SoC main control chip, HDMI input unit, eDP output unit, USB communication unit, power supply unit and liquid crystal drive unit, soC main control chip model is FMQL T900, HDMI input unit and SoC main control chip electric connection, eDP output unit and SoC main control chip electric connection, USB communication unit and SoC main control chip's USB link electric connection, eDP output unit's output and liquid crystal drive unit electric connection, soC main control chip and liquid crystal drive unit electric connection, power supply unit and SoC main control chip and liquid crystal drive unit electric connection, power supply unit is used for supplying power to SoC main control chip, HDMI input unit, eDP output unit, USB communication unit and liquid crystal drive unit.
Preferably, the HDMI input unit includes a plurality of HDMI ports and at least two HDMI signal processing chips, at least one of the HDMI ports is configured to receive an input HDMI video signal, at least one of the HDMI ports is configured to output an HDMI video signal, at least one of the HDMI signal processing chips is configured to process the input HDMI video signal, at least one of the HDMI signal processing chips is configured to process the output HDMI video signal, and the type of the HDMI signal processing chip is GSV2011.
Preferably, the eDP output unit includes an eDP interface conversion chip, and the model of the eDP interface conversion chip is NCS8805.
Preferably, the USB communication unit includes a USB bus control chip and a high-speed USB transceiver chip, where the high-speed USB transceiver chip is electrically connected to the USB bus control chip, the type of the USB bus control chip is CH334U, and the type of the high-speed USB transceiver chip is CH132F.
Preferably, the power supply unit includes a plurality of primary buck management chips and a plurality of secondary buck management chips, at least one primary buck management chip output and a plurality of secondary buck management chips electric connection, at least one secondary buck management chip output electric connection has tertiary buck management chip, primary buck management chip model is C42203, secondary buck management chip model is SM4644, tertiary buck management chip model is SM51200.
Preferably, the liquid crystal driving unit includes a video signal receiving port and a control signal receiving port, the video signal receiving port is electrically connected with the eDP output unit, and the control signal receiving port is electrically connected with the SoC main control chip.
Compared with the prior art, the utility model has the beneficial effects that:
The utility model utilizes the IP core of the SoC to realize the functions of scaling, OSD superposition and eDP output driving of video data; the system control of the functions is realized by utilizing an AXI bus of an ARM controller at a PS end, and USB and IIC control interfaces are constructed by utilizing USB and IIC controllers of the ARM, so that the management of the USB interfaces and the IIC backlight adjustment control are realized; constructing PWM waves by using a PL terminal, and realizing PWM regulation through an AXI bus;
In addition, the proposal adopts the output display and configuration of the eDP/DP coding protocol, and the transmission is not provided with a channel clock any more based on an 8b/10b coding mode, and only has a high-speed differential data line. By the coding mode, data and clock information can be transmitted simultaneously by only one pair of differential signal lines, and compared with the conventional video interface protocols such as HDMI, the transmission rate and stability are greatly improved. And (3) performing video scaling on the resolution of the display by utilizing bilinear interpolation or a trilinear interpolation algorithm, so as to support scaling of videos with various different resolutions to a specific resolution supported by the liquid crystal panel.
Drawings
Fig. 1 is a block diagram of a 4K eDP liquid crystal driving board based on SoC according to the present utility model;
Fig. 2 is a block diagram of the structure of an HDMI input unit in the present utility model;
FIG. 3 is a block diagram showing the structure of an eDP output unit in the present utility model;
fig. 4 is a block diagram of the power supply unit in the present utility model;
FIG. 5 is a block diagram showing the structure of a USB communication unit according to the present utility model;
fig. 6 is a schematic diagram of a liquid crystal driving software scheduling in the present utility model.
Detailed Description
The following description is presented to enable one of ordinary skill in the art to make and use the utility model. The preferred embodiments in the following description are by way of example only and other obvious variations will occur to those skilled in the art.
Referring to fig. 1-6, a 4K eDP liquid crystal driving board based on SoC includes a SoC main control chip, an HDMI input unit, an eDP output unit, a USB communication unit, a power supply unit and a liquid crystal driving unit, where the type of the SoC main control chip is FMQL T900, the HDMI input unit is electrically connected with the SoC main control chip, the eDP output unit is electrically connected with the SoC main control chip, the USB communication unit is electrically connected with a USB connection end of the SoC main control chip, an output end of the eDP output unit is electrically connected with the liquid crystal driving unit, the SoC main control chip is electrically connected with the liquid crystal driving unit, the power supply unit is electrically connected with the SoC main control chip and the liquid crystal driving unit, and the power supply unit is used for supplying power to the SoC main control chip, the HDMI input unit, the eDP output unit, the USB communication unit and the liquid crystal driving unit.
The scaling, OSD superposition and eDP output driving functions of video data are realized by utilizing the IP core of the SoC; the system control of the functions is realized by utilizing an AXI bus of an ARM controller at a PS end, and USB and IIC control interfaces are constructed by utilizing USB and IIC controllers of the ARM, so that the management of the USB interfaces and the IIC backlight adjustment control are realized; constructing PWM waves by using a PL terminal, and realizing PWM regulation through an AXI bus;
In addition, the proposal adopts the output display and configuration of the eDP/DP coding protocol, and the transmission is not provided with a channel clock any more based on an 8b/10b coding mode, and only has a high-speed differential data line. By the coding mode, data and clock information can be transmitted simultaneously by only one pair of differential signal lines, and compared with the conventional video interface protocols such as HDMI, the transmission rate and stability are greatly improved. And (3) performing video scaling on the resolution of the display by utilizing bilinear interpolation or a trilinear interpolation algorithm, so as to support scaling of videos with various different resolutions to a specific resolution supported by the liquid crystal panel.
The HDMI input unit comprises a plurality of HDMI ports and at least two HDMI signal processing chips, wherein at least one HDMI port is used for receiving input HDMI video signals, at least one HDMI port is used for outputting HDMI video signals, at least one HDMI signal processing chip is used for processing the input HDMI video signals, at least one HDMI signal processing chip is used for processing the output HDMI video signals, the HDMI signal processing chip model is GSV2011, the GSV2011 chip can convert 4K high-definition HDMI signals into 48bitTTL levels or 12 pairs of differential LVDS signals, the chip supports HDMI1.4/2.0 protocols, the highest pixel clock is supported to 600MHz, 4Kx2K@60Hz4:4:48bit high-definition video signal decoding can be achieved, and the chip also supports 4KHDMI signal looping.
Referring to fig. 2, GSV2011 has HDMIRXPHY and TXPHY inside the chip. The RXPHY interface analyzes the TMDS signal into LVDS or TTL level signals, sends the signals into the SoC, and outputs the processed video data through the eDP interface after the SoC processes other video data. Its TXPHY may loop out the input video. The chip has an IIC interface, and internal functional blocks, such as output format LVDS or TTL selection, downScaler and the like, can be configured through the IIC interface.
Referring to fig. 3, the eDP output unit includes an eDP interface conversion chip, the type of the eDP interface conversion chip is NCS8805, and NCS8805 is a high-definition RGB/LVDS-to-eDP interface conversion chip of the new port coast company, supporting 1/2/4Lane, and having a rate of 1.62/2.7Gbps per Lane. RGB input supports 18/24bit, highest pixel clock 270MHz, and SDR/DDR sampling; LVDS supports single/dual channel 6/8bit inputs, with each pair of LVDS rates of 400 Mbps-1 Gbps, eDP output supporting a maximum 3840x2160 resolution. The chip has a pair of IIC control interfaces, and the registers and working states of the chip are configured through the IIC interfaces.
Referring to fig. 5, the USB communication unit includes a USB bhub control chip and a high-speed USB transceiver chip, the high-speed USB transceiver chip is electrically connected to the USB bhub control chip, the USB bhub control chip is CH334U, and the high-speed USB transceiver chip is CH132F.
The USB interface on the display drive board mainly realizes the control of the PC on the display screen, and in addition, the touch interface of the display screen with the USB interface also needs to be connected to the PC, so that a USBHub link from the PC to the touch interface of the display drive board and the display screen is constructed, wherein the PC is a Host. The CH334U chip of Nanjing Hengqin corporation is a 4-port USBHub control chip conforming to the USB2.0 protocol specification, the uplink port supports USB2.0 high speed and full speed, the downlink port supports USB2.0 high speed 480Mbps, full speed 12Mbps and low speed 1.5Mbps, and supports STT and high performance MTT. Fig. 5 is a schematic diagram of USBHub link, wherein the PC is usbhast, and the SoC controls the USB interface and touches the downstream port of the USB interface, so as to control the SoC and the touch screen. And simultaneously, resetting CH334U and CH132F is connected with the IO port of the SoC, so that the controllable turn-off of the USB interface is realized.
Because the SoC only has a USB1.0 controller and does not have USBPHY interfaces, a constant CH132F is synchronously selected as a USB2.0PHY chip, the chip is a high-speed USB transceiver chip of an ULPI interface, is compatible with the USB1.0 specification and the UTMI+ LowPinInterface (ULPI) 1.1 protocol specification, supports high-speed, full-speed and low-speed data transceiver of the USB2.0, and is completely compatible with a USBULPI interface of the SoC.
Referring to fig. 4, the power supply unit includes a plurality of primary buck management chips and a plurality of secondary buck management chips, at least one primary buck management chip output is electrically connected to the plurality of secondary buck management chips, at least one secondary buck management chip output is electrically connected to a tertiary buck management chip, the primary buck management chip is C42203, the secondary buck management chip is SM4644, and the tertiary buck management chip is SM51200.
The power input is DC24V, and DC12V, DC, 10V, DC V, DC3.3V, DC2.5V, DC1.8V, DC1.5V, DC1.2V and DC1.0V are required for supplying power to the liquid crystal driving panel. In the embodiment, 3C 42203 pieces are selected firstly to reduce +24V to +12V, wherein 1 piece drives 2 pieces of SM4644, and low-voltage power supplies needed by various ICs are output through LDOs; the second piece of driving display screen needs reserved +12V; and the third piece provides +10V and 3A power for supplying power to the liquid crystal display. The additional 0.75V reference voltage required by the on-board DDR3 memory is realized by SM 51200.
The Shenzhen elegance core electronic C42203 is a wide input 4.5V-40V,3A output buck power management chip, and the first output 12V and 3A is needed for supplying power to the display drive board IC. The maximum power consumption IC of the display driving plate is a complex micro SoC, the estimated power consumption is 6W, and the whole power consumption of the display driving plate is estimated to be within 10W. C42203 provides that the maximum power consumption reaches 36W, and meets the power consumption requirement.
SM4644Y is used as a buck management chip, the chip has 4 paths of output, 4 paths of output current can be provided for maximum 4A by a single path, 4 paths of output current can be provided for maximum 16A by parallel connection, and the working temperature and the power supply range of the chip meet the requirements of indexes. In different voltage output application scenarios, only the ADJ resistance configuration needs to be adjusted; the chip supports EN enabling control, and the peripheral circuit of the product is simple, mature and stable, and can meet the power supply requirement of each chip.
The liquid crystal driving unit comprises a video signal receiving port and a control signal receiving port, wherein the video signal receiving port is electrically connected with the eDP output unit, and the control signal receiving port is electrically connected with the SoC main control chip.
The scheduling schematic diagram of the liquid crystal driving software of the liquid crystal driving unit in the embodiment is shown in fig. 6, wherein ARMA9 is an SDK running core and is connected with all functional modules through an AXI-Lite bus, and mainly realizes the communication of system control, USB/IIC and the like; HDMI DATA IN, displayPort TX, etc. are PL-side video acquisition and display drivers. The Video data Stream is sent into VDMADDR buffer memory by HDMI through AXI-Stream bus, then scaled, and sent to AXI Video out until being sent into DisplayPort TX, and finally output and display through eDP interface.
In summary, the utility model has the advantages that: the 4K eDP liquid crystal drive board based on the SoC is provided, 100% domestic components and operation systems are adopted, an internal digital eDP interface based on a DisplayPort architecture and a protocol is utilized, a simpler connector and fewer pins are used for transmitting high-resolution signals, the transmission rate is far higher than that of LVDS, the lossless transmission of 4K high-definition video data can be realized, the certainty and the instantaneity of video signal transmission are greatly improved, meanwhile, the complete health management function is realized, the reliability and the safety of video transmission are greatly improved, and the video drive board can be adapted to places with severe environments and severe safety requirements.
The foregoing has shown and described the basic principles, principal features and advantages of the utility model. It will be understood by those skilled in the art that the present utility model is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present utility model, and various changes and modifications may be made therein without departing from the spirit and scope of the utility model, which is defined by the appended claims. The scope of the utility model is defined by the appended claims and equivalents thereof.
Claims (6)
1. The utility model provides a 4KeDP liquid crystal drive board based on SoC, its characterized in that includes SoC main control chip, HDMI input unit, eDP output unit, USB communication unit, power supply unit and liquid crystal drive unit, soC main control chip model is FMQL T900, HDMI input unit and SoC main control chip electric connection, eDP output unit and SoC main control chip electric connection, USB communication unit and SoC main control chip's USB link electric connection, eDP output unit's output and liquid crystal drive unit electric connection, soC main control chip and liquid crystal drive unit electric connection, power supply unit and SoC main control chip and liquid crystal drive unit electric connection, power supply unit is used for supplying power to SoC main control chip, HDMI input unit, eDP output unit, USB communication unit and liquid crystal drive unit.
2. The SoC-based 4KeDP liquid crystal drive board of claim 1, wherein the HDMI input unit includes a plurality of HDMI ports and at least two HDMI signal processing chips, at least one of the HDMI ports is for receiving an input HDMI video signal, at least one of the HDMI ports is for outputting an HDMI video signal, at least one of the HDMI signal processing chips is for processing an input HDMI video signal, at least one of the HDMI signal processing chips is for processing an output HDMI video signal, and the HDMI signal processing chip is GSV2011.
3. The SoC-based 4KeDP liquid crystal driver board of claim 2, wherein the eDP output unit includes an eDP interface conversion chip, and the model of the eDP interface conversion chip is NCS8805.
4. The SoC-based 4KeDP liquid crystal driving board as in claim 3, wherein the USB communication unit includes a USB hub control chip and a high-speed USB transceiver chip, the high-speed USB transceiver chip is electrically connected to the USB hub control chip, the type of the USB hub control chip is CH334U, and the type of the high-speed USB transceiver chip is CH132F.
5. The SoC-based 4KeDP liquid crystal driver board of claim 4, wherein the power supply unit includes a plurality of primary buck management chips and a plurality of secondary buck management chips, at least one of the primary buck management chip outputs is electrically connected to a plurality of the secondary buck management chips, at least one of the secondary buck management chip outputs is electrically connected to a tertiary buck management chip, the primary buck management chip is C42203, the secondary buck management chip is SM4644, and the tertiary buck management chip is SM51200.
6. The SoC-based 4KeDP liquid crystal driver board of claim 5, wherein the liquid crystal driver unit includes a video signal receiving port and a control signal receiving port, the video signal receiving port is electrically connected to the eDP output unit, and the control signal receiving port is electrically connected to the SoC main control chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321425085.9U CN220821061U (en) | 2023-06-06 | 2023-06-06 | 4K eDP liquid crystal drive board based on SoC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202321425085.9U CN220821061U (en) | 2023-06-06 | 2023-06-06 | 4K eDP liquid crystal drive board based on SoC |
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| CN220821061U true CN220821061U (en) | 2024-04-19 |
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| CN202321425085.9U Active CN220821061U (en) | 2023-06-06 | 2023-06-06 | 4K eDP liquid crystal drive board based on SoC |
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2023
- 2023-06-06 CN CN202321425085.9U patent/CN220821061U/en active Active
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