CN220796714U

CN220796714U - Low thermal resistance power module

Info

Publication number: CN220796714U
Application number: CN202322488284.0U
Authority: CN
Inventors: 陈智超
Original assignee: Geely Maijie Investment Co ltd; Zhejiang Jingneng Microelectronics Co ltd; Zhejiang Geely Holding Group Co Ltd
Current assignee: Geely Maijie Investment Co ltd; Zhejiang Jingneng Microelectronics Co ltd; Zhejiang Geely Holding Group Co Ltd
Priority date: 2023-09-12
Filing date: 2023-09-12
Publication date: 2024-04-16
Anticipated expiration: 2033-09-12

Abstract

The application provides a low thermal resistance power module, including insulating ceramic base plate and locate a plurality of chips of insulating ceramic base plate, insulating ceramic base plate includes upper bridge arm and the lower bridge arm of arranging along first direction, and upper bridge arm is located to some chip, and lower bridge arm is located to another part chip. The chips arranged on the upper bridge arm and the chips arranged on the lower bridge arm are symmetrically arranged, two adjacent chips along the first direction are staggered along the second direction, and the first direction is perpendicular to the second direction. According to the low thermal resistance power module, the thermal coupling effect between chips can be reduced by using the staggered chip layout, the thermal resistance of the power module is reduced, and the power density of the module is improved.

Description

Low thermal resistance power module

Technical Field

The application relates to the technical field of semiconductors, in particular to a low thermal resistance power module.

Background

In the field of power semiconductors, conventional silicon devices have been developed and utilized for decades, the performance has been close to the physical limit of the conventional silicon devices, and in recent years, with the progress of semiconductor manufacturing processes, the development of third generation wide bandgap power semiconductors is rapid, wherein silicon carbide is considered as the best choice for manufacturing the power semiconductor devices by replacing silicon materials at present due to the superior material characteristics of the silicon carbide, and compared with silicon materials, silicon carbide has lower conduction loss and switching loss and can realize higher switching frequency and power density. The power module is used as a key component of the electric control system of the new energy vehicle, and influences the energy density and the working efficiency of the new energy vehicle. The silicon carbide power module can realize higher power density due to the characteristics of high efficiency and high switching frequency. However, high power density means a greater heat flux density of the output, which creates more stringent conditions for the heat dissipation design of the module. This poses a serious challenge to the thermal output characteristics of silicon carbide power modules, and conventional chip layouts are clearly unable to support their full use potential.

Disclosure of Invention

The present application provides a low thermal resistance power module to solve at least some of the problems in the related art.

In a first aspect, the present application provides a low thermal resistance power module, including an insulating ceramic substrate and a plurality of chips disposed on the insulating ceramic substrate, where the insulating ceramic substrate includes an upper bridge arm and a lower bridge arm arranged along a first direction, a part of chips are disposed on the upper bridge arm, and another part of chips are disposed on the lower bridge arm; the chips arranged on the upper bridge arm and the chips arranged on the lower bridge arm are symmetrically arranged, and two adjacent chips along the first direction are staggered along the second direction; the first direction is perpendicular to the second direction.

Optionally, the upper bridge arm includes a first upper bridge arm and a second upper bridge arm arranged along the second direction; the first upper bridge arm and the second upper bridge arm are symmetrically arranged along a first direction, a plurality of chips positioned on the first upper bridge arm and a plurality of chips positioned on the second upper bridge arm are symmetrically arranged along the first direction, a plurality of chips positioned on the first upper bridge arm are arranged at intervals along the first direction, and two adjacent chips are staggered along a second direction; the chips positioned on the second upper bridge arm are arranged at intervals along the first direction, and two adjacent chips are staggered along the second direction.

Optionally, the lower bridge arm includes a first lower bridge arm and a second lower bridge arm arranged along the second direction; the first lower bridge arm and the second lower bridge arm are symmetrically arranged along a first direction, a plurality of chips positioned on the first lower bridge arm and a plurality of chips positioned on the second lower bridge arm are symmetrically arranged along the first direction, a plurality of chips positioned on the first lower bridge arm are arranged at intervals along the first direction, and two adjacent chips are staggered along a second direction; the chips positioned on the second lower bridge arm are arranged at intervals along the first direction, and two adjacent chips are staggered along the second direction.

Optionally, the chip includes a first surface and a second surface that are disposed opposite to each other, the first surface is connected to the insulating ceramic substrate, and the power module further includes a conductive member, where the conductive member is connected to the second surface and the insulating ceramic substrate by welding or sintering, respectively.

Optionally, the insulating ceramic substrate includes an insulating layer and a first metal layer, the first metal layer is disposed on a surface of one side of the insulating layer, and the chip is connected to the first metal layer.

Optionally, the insulating layer is a ceramic layer, and the first metal layer is a copper layer.

Optionally, the chip includes a first surface and a second surface disposed opposite to each other, the first surface being connected to the first metal layer by a silver sintering process.

Optionally, the second surface is provided with a signal electrode, and the signal electrode is connected to the first metal layer through a wire.

Optionally, the insulating ceramic substrate further includes a second metal layer, the second metal layer is disposed on a side of the insulating layer opposite to the chip, and the second metal layer is a copper layer.

Optionally, the power module further includes a heat dissipation substrate and a housing, the heat dissipation substrate is disposed on a side of the insulating ceramic substrate opposite to the chip, the heat dissipation substrate is connected with the housing and forms a containing cavity, and the insulating ceramic substrate and the chip are disposed in the containing cavity.

Optionally, the accommodating cavity is filled with silica gel, and the insulating ceramic substrate and the chip are encapsulated in the silica gel.

Alternatively, the chip is a silicon carbide chip.

Optionally, the chip located on the upper bridge arm and the chip located on the lower bridge arm face the same or opposite.

The low thermal resistance power module comprises an insulating ceramic substrate and a plurality of chips arranged on the insulating ceramic substrate, wherein the insulating ceramic substrate comprises an upper bridge arm and a lower bridge arm which are arranged along a first direction, one part of chips are arranged on the upper bridge arm, and the other part of chips are arranged on the lower bridge arm. The chips arranged on the upper bridge arm and the chips arranged on the lower bridge arm are symmetrically arranged, two adjacent chips along the first direction are staggered along the second direction, and the first direction is perpendicular to the second direction. According to the low thermal resistance power module, the thermal coupling effect between chips can be reduced by using the staggered chip layout, the thermal resistance of the power module is reduced, and the power density of the module is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic diagram illustrating a power module according to an exemplary embodiment of the present application;

fig. 2 is a schematic structural diagram of a power module according to another exemplary embodiment of the present application;

FIG. 3 is a schematic view showing the structure of an insulating ceramic substrate according to an exemplary embodiment of the present application;

fig. 4 is a schematic structural view of an insulating ceramic substrate according to another exemplary embodiment of the present application;

fig. 5 is a schematic structural view of an insulating ceramic base plate according to still another exemplary embodiment of the present application;

FIG. 6 illustrates a cross-sectional view of a power module according to an exemplary embodiment of the present application;

fig. 7 is a partial enlarged view of a cross-sectional view of the power module shown in fig. 6.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and/or "upper" and the like are merely for convenience of description and are not limited to one location or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

According to the low thermal resistance power module, the thermal coupling effect between chips can be reduced by using the staggered chip layout, the thermal resistance of the power module is reduced, and the power density of the module is improved.

The application provides a low thermal resistance power module. The low thermal resistance power module of the present application is described in detail below with reference to the accompanying drawings. The features of the examples and embodiments described below may be combined with each other without conflict.

Fig. 1 is a schematic structural view of a power module 1 according to an exemplary embodiment of the present application, fig. 2 is a schematic structural view of a power module 1 according to another exemplary embodiment of the present application, fig. 3 is a schematic structural view of an insulating ceramic substrate 4 according to an exemplary embodiment of the present application, fig. 4 is a schematic structural view of an insulating ceramic substrate 4 according to another exemplary embodiment of the present application, fig. 5 is a schematic structural view of an insulating ceramic substrate 4 according to another exemplary embodiment of the present application, fig. 6 is a cross-sectional view of a power module 1 according to an exemplary embodiment of the present application, and fig. 7 is a partially enlarged cross-sectional view of a power module 1 shown in fig. 6. Referring to fig. 1 to 7, the present application provides a low thermal resistance power module, comprising: the insulating ceramic substrate 4 and a plurality of chips 5 provided on the insulating ceramic substrate 4, the insulating ceramic substrate 4 includes an upper arm 7 and a lower arm 6 arranged along the first direction X1, and one part of the chips 5 is provided on the lower arm 6 and the other part of the chips 5 is provided on the upper arm 7. The chips 5 arranged on the upper bridge arm 7 and the chips 5 arranged on the lower bridge arm 6 are symmetrically arranged, two adjacent chips 5 are staggered along the first direction X1, and the first direction X1 is perpendicular to the second direction X2.

In the embodiment shown in fig. 3, the power module 1 includes an insulating ceramic substrate 4 and twelve chips 5, six chips 5 are respectively disposed on a lower bridge arm 6 and an upper bridge arm 7, the six chips 5 are symmetrically disposed in pairs along a first direction X1, and three chips 5 disposed on the same side are staggered in a second direction X2 and are disposed at intervals along the first direction X1. Similarly, referring to fig. 4 and 5, the chips 5 may also have a plurality of staggered arrangements, and the staggered arrangement of the chips 5 is not limited in the present application. Through the staggered chips 5, the gaps among the chips 5 can be increased, better heat dissipation is promoted, the thermal coupling effect among the chips 5 is reduced, and the thermal resistance of the power module 1 is reduced.

In some embodiments, lower leg 6 includes a first lower leg 60 and a second lower leg 61 arranged along a second direction X2, second direction X2 being perpendicular to first direction X1. The first lower bridge arm 60 and the second lower bridge arm 61 are symmetrically arranged along the first direction X1, the plurality of chips 5 located in the first lower bridge arm 60 and the plurality of chips 5 located in the second lower bridge arm 61 are symmetrically arranged along the first direction X1, the plurality of chips 5 located in the first lower bridge arm 60 are arranged at intervals along the first direction X1, and two adjacent chips 5 are staggered along the second direction X1. The chips 5 located in the second lower bridge arm 61 are arranged at intervals along the first direction X1, and two adjacent chips 5 are staggered along the second direction X1. In the embodiment shown in fig. 1 to 5, six chips 5 are disposed in the lower bridge arm 6, wherein three chips 5 are disposed in the first lower bridge arm 60, the remaining three chips 5 are disposed in the second lower bridge arm 61, the three chips 5 disposed in the first lower bridge arm 60 and the three chips 5 disposed in the second lower bridge arm 61 are symmetrically disposed along the first direction X1, and two adjacent chips 5 are disposed at intervals along the first direction X1 and staggered along the second direction X2. Referring to fig. 1 and 3, two chips 5, which are not adjacent among the three chips 5, are disposed near the edge of the insulating ceramic base plate 4, and the remaining chips 5 are disposed near the middle of the insulating ceramic base plate 4. In the embodiment shown in fig. 4, two chips 5, which are not adjacent, among the three chips 5 located in the first lower leg 60 are disposed near the middle of the insulating ceramic base plate 4, and the remaining one chip 5 is disposed near the edge of the insulating ceramic base plate 4. The arrangement of the three chips 5 located in the second lower leg 61 corresponds to the embodiment shown in fig. 3. In the embodiment shown in fig. 5, the arrangement of the three chips 5 located in the first lower leg 60 is identical to the embodiment shown in fig. 3, and two chips not adjacent among the three chips 5 located in the second lower leg 61 are disposed near the middle of the insulating ceramic base plate 4, and the remaining one chip 5 is disposed near the edge of the insulating ceramic base plate 4. The chips 5 may also have various staggered arrangements, and the staggered arrangement of the chips 5 is not limited in the present application. By increasing the gaps between the chips 5, better heat dissipation can be promoted, the thermal coupling effect between the chips 5 is reduced, the thermal resistance of the power module 1 is reduced, and the module power density is improved.

In some embodiments, upper leg 7 includes a first upper leg 70 and a second upper leg 71 arranged along a second direction X2, second direction X2 being perpendicular to first direction X1. The first upper bridge arm 70 and the second upper bridge arm 71 are symmetrically arranged along the first direction X1, the plurality of chips 5 located on the first upper bridge arm 70 and the plurality of chips 5 located on the second upper bridge arm 71 are symmetrically arranged along the first direction X1, the plurality of chips 5 located on the first upper bridge arm 70 are arranged at intervals along the first direction X1, and two adjacent chips 5 are staggered along the second direction X1. The chips 5 located in the second upper bridge arm 71 are arranged at intervals along the first direction X1, and two adjacent chips 5 are staggered along the second direction X1. In the embodiment shown in fig. 1 to 5, six chips 5 are disposed in the upper bridge arm 7, wherein three chips 5 are disposed in the first upper bridge arm 70, the remaining three chips 5 are disposed in the second upper bridge arm 71, the three chips 5 disposed in the first upper bridge arm 70 and the three chips 5 disposed in the second upper bridge arm 71 are symmetrically disposed along the first direction X1, and two adjacent chips 5 are disposed at intervals along the first direction X1 and staggered along the second direction X2. Referring to fig. 1 and 3, two chips 5, which are not adjacent among the three chips 5, are disposed near the edge of the insulating ceramic base plate 4, and the remaining chips 5 are disposed near the middle of the insulating ceramic base plate 4. In the embodiment shown in fig. 4, two chips 5, which are not adjacent, of the three chips 5 located in the first upper bridge arm 70 are disposed near the middle of the insulating ceramic base plate 4, and the remaining one chip 5 is disposed near the edge of the insulating ceramic base plate 4. The arrangement of the three chips 5 located in the second upper leg 71 corresponds to the embodiment shown in fig. 3. In the embodiment shown in fig. 5, the arrangement of the three chips 5 located in the first upper arm 70 is identical to the embodiment shown in fig. 3, and two chips not adjacent among the three chips 5 located in the second upper arm 71 are disposed near the middle of the insulating ceramic base plate 4, and the remaining one chip 5 is disposed near the edge of the insulating ceramic base plate 4. The chips 5 may also have various staggered arrangements, and the staggered arrangement of the chips 5 is not limited in the present application. By increasing the gaps between the chips 5, better heat dissipation can be promoted, the thermal coupling effect between the chips 5 is reduced, the thermal resistance of the power module 1 is reduced, and the module power density is improved.

In some embodiments, the chips 5 located on the upper leg 7 and the chips 5 located on the lower leg 6 are oriented the same or opposite. In the embodiment shown in fig. 4, the chips 5 located in the upper leg 7 and the chips 5 located in the lower leg 6 are oriented in opposite directions. In the embodiment shown in fig. 5, the chip 5 located in the upper bridge arm 7 and the chip 5 located in the lower bridge arm 6 are oriented in the same direction, which is not limited in this application.

In some embodiments, the insulating ceramic base plate 4 includes an insulating layer 40 and a first metal layer 41, the first metal layer 41 is disposed on one side surface of the insulating layer 40, and the chip 5 is connected to the first metal layer 41. The insulating ceramic base plate 4 further comprises a second metal layer 42, the second metal layer 42 is disposed on a side of the insulating layer 40 facing away from the chip 5, and the second metal layer 42 is a copper layer. The first metal layer 41 is used for connecting power devices and other electronic components. The insulating layer 40 is used to provide electrical isolation, ensure safe isolation between different voltages, and prevent current shorts. Referring to fig. 7, in the embodiment of the present application, the insulating layer 40 is a ceramic layer, the first metal layer 41 is a copper layer, and the second metal layer 42 is a copper layer. The ceramic has high insulativity and high temperature resistance, can effectively isolate circuits between different voltages, and can also avoid the reduction of insulating property caused by overhigh temperature. In some embodiments, insulating layer 40 may be a silicon nitride ceramic layer that utilizes an active metal braze copper-clad technique to achieve a pyrometallurgical bond of silicon nitride to copper. The silicon nitride ceramic layer has good thermal conductivity and high reliability.

In the embodiment shown in fig. 3, the chip 5 comprises a first surface (not shown) and a second surface 50 arranged opposite each other, the first surface being connected to the insulating ceramic substrate 4. The power module 1 further comprises a conductive member 10, and the conductive member 10 is connected to the second surface 50 and the insulating ceramic substrate 4 by welding or sintering, respectively. In the embodiment of the present application, the conductive member 10 is a copper foil, one end of the conductive member 10 is connected to the second surface 50 of the chip 5, and the other end is connected to the first metal layer 41 of the insulating ceramic substrate 4. In other embodiments, the conductive member 10 may be a copper wire. Compared with copper wires, the copper foil has larger conductive sectional area, can provide lower resistance and higher current capacity, improves the reliability of signal transmission, and can also improve the stability and durability of connection.

In some embodiments, the chip 5 includes oppositely disposed first and second surfaces 50, the first surface being connected to the first metal layer 41 by a silver sintering process, as shown in fig. 7. Compared with the traditional welding mode, the thickness of the sintering layer is reduced, good electrical connectivity, mechanical strength and heat conduction performance can be provided, the reliability, the heat dissipation effect and the service life of the power module 1 can be improved, and the packaging structure of the power module 1 can be simplified.

In some embodiments, the second surface 50 is provided with signal poles 11, the signal poles 11 being connected to the first metal layer 41 by wires 12. The surface of the chip 5 is provided with signal electrodes 11 and is connected to the first metal layer 41 by means of wires 12. The signal pole 11 is used for inputting or outputting a signal. Referring to fig. 3, in the embodiment of the present application, a transmission and control circuit of signals is implemented between the signal electrode 11 of the chip 5 and the first metal layer 41 through an aluminum wire and using an aluminum wire bonding process. By this arrangement, a reliable connection between the signal pole 11 and the control circuit can be ensured, and the transmission of signals and the function of the control circuit can be realized.

In the embodiment shown in fig. 2, 6 and 7, the power module 1 further includes a heat dissipation substrate 13 and a housing 2, the heat dissipation substrate 13 is disposed on a side of the insulating ceramic substrate 4 opposite to the chip 5, the heat dissipation substrate 13 is connected to the housing 2 and forms a receiving cavity 14, and the insulating ceramic substrate 4 and the chip 5 are disposed in the receiving cavity 14. The housing 2 provides mechanical support for the power module 1 and isolates the interior of the power module 1 from the external environment. The area of the heat dissipation substrate 13 is larger than the area of the insulating ceramic substrate 4. The insulating ceramic substrate 4 and the heat dissipation substrate 13 may be connected by a silver sintering process. The heat dissipation substrate 13 is usually made of copper or aluminum, has better heat conductivity, and can effectively dissipate heat and reduce the temperature of the chip 5. In addition, the fixing and supporting functions of the chip 5 and other components can be realized, and the structural stability and reliability of the whole power module 1 can be enhanced.

In some embodiments, the housing 2 is provided with a power terminal 8, the positive electrode of the power terminal 8 is divided into two paths inside the housing 2 and connected to the left and right sides of the upper bridge arm 7, the negative electrode of the power terminal 8 is connected to the lower bridge arm 6, and the power terminal 8 can be connected to an interface of an external power supply and a load.

In some embodiments, a plurality of pin fins 15 may be provided at an end of the heat dissipating substrate 13 remote from the housing 2, as shown in fig. 6 and 7. The pin fins 15 are placed in the cooling liquid to perform water-cooling heat dissipation, so that the heat dissipation efficiency of the power module 1 can be further improved.

In some embodiments, the housing 2 includes a first housing 20 and a second housing 21, the first housing 20 is formed around an edge of the insulating ceramic substrate 4, and the power terminal 8 is provided on the first housing 20. The second housing 21 is provided on a side of the insulating ceramic substrate 4 close to the chip 5, for sealing the insulating ceramic substrate 4 and the chip 5.

In some embodiments, the accommodating cavity 14 is filled with a silicone gel (not shown), in which the insulating ceramic substrate 4 and the chip 5 are encapsulated. The silicone gel has good insulating properties, and can prevent electrical components in the accommodating chamber 14 from being short-circuited or electrically failed, and also prevent dust, moisture, chemical substances, or the like from damaging the electrical components.

In the embodiment of the present application, the chip 5 is a silicon carbide chip. Silicon carbide has lower conduction loss and switching loss, and can realize higher switching frequency and power density.

In some embodiments, the insulating ceramic base plate 4 is provided with a plurality of signal terminals 16 for receiving control signals from a control circuit or an external control system, so that parameters such as a switching state, an operation mode, an output voltage or a current of the power module 1 can be controlled.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A low thermal resistance power module, comprising: the device comprises an insulating ceramic substrate and a plurality of chips arranged on the insulating ceramic substrate, wherein the insulating ceramic substrate comprises an upper bridge arm and a lower bridge arm which are arranged along a first direction, one part of the chips are arranged on the upper bridge arm, and the other part of the chips are arranged on the lower bridge arm; the chips arranged on the upper bridge arm and the chips arranged on the lower bridge arm are symmetrically arranged, two adjacent chips in the first direction are staggered in the second direction, and the first direction is perpendicular to the second direction.

2. The low thermal resistance power module of claim 1, wherein the upper leg comprises a first upper leg and a second upper leg arranged along the second direction; the first upper bridge arm and the second upper bridge arm are symmetrically arranged along the first direction, the chips positioned on the first upper bridge arm and the chips positioned on the second upper bridge arm are symmetrically arranged along the first direction, the chips positioned on the first upper bridge arm are arranged at intervals along the first direction, and two adjacent chips are staggered along the second direction; the chips positioned on the second upper bridge arm are arranged at intervals along the first direction, and two adjacent chips are staggered along the second direction; and/or

The lower bridge arm comprises a first lower bridge arm and a second lower bridge arm which are arranged along the second direction; the first lower bridge arm and the second lower bridge arm are symmetrically arranged along the first direction, the chips positioned on the first lower bridge arm and the chips positioned on the second lower bridge arm are symmetrically arranged along the first direction, the chips positioned on the first lower bridge arm are arranged at intervals along the first direction, and two adjacent chips are staggered along the second direction; the chips positioned on the second lower bridge arm are arranged at intervals along the first direction, and two adjacent chips are staggered along the second direction.

3. The low thermal resistance power module of claim 1, wherein the die comprises oppositely disposed first and second surfaces, the first surface being connected to the insulating ceramic substrate, the power module further comprising conductive members connected to the second surface and the insulating ceramic substrate by soldering or sintering, respectively.

4. The low thermal resistance power module of claim 1, wherein the insulating ceramic substrate comprises an insulating layer and a first metal layer, the first metal layer is disposed on a side surface of the insulating layer, and the chip is connected to the first metal layer.

5. The low thermal resistance power module of claim 4, wherein the insulating layer is a ceramic layer and the first metal layer is a copper layer.

6. The low thermal resistance power module of claim 4, wherein the die comprises oppositely disposed first and second surfaces, the first surface being connected to the first metal layer by a silver sintering process.

7. The low thermal resistance power module of claim 6, wherein the second surface is provided with signal poles connected to the first metal layer by wires.

8. The low thermal resistance power module of claim 4, wherein the insulating ceramic substrate further comprises a second metal layer disposed on a side of the insulating layer facing away from the chip, the second metal layer being a copper layer.

9. The low thermal resistance power module of claim 1, further comprising a heat dissipating substrate and a housing, the heat dissipating substrate being disposed on a side of the insulating ceramic substrate opposite the chip, the heat dissipating substrate being connected to the housing and forming a receiving cavity, the insulating ceramic substrate and the chip being disposed within the receiving cavity.

10. The low thermal resistance power module of claim 9, wherein the receiving cavity is filled with a silicone gel, the insulating ceramic substrate, and the chip is encapsulated in the silicone gel.

11. The low thermal resistance power module of claim 1, wherein the die is a silicon carbide die.

12. The low thermal resistance power module of claim 1, wherein the chips located on the upper leg and the chips located on the lower leg are oriented the same or opposite.