CN220732363U - Surge protection circuit - Google Patents

Abstract

The utility model relates to a surge protection circuit which comprises a power supply surge voltage detection circuit, an operation clamping control circuit, an H-bridge control logic and an H-bridge driving circuit, wherein the power supply surge voltage detection circuit is respectively connected with the H-bridge control logic and the operation clamping control circuit, the operation clamping control circuit is connected with the H-bridge control logic, the H-bridge driving circuit is connected with the operation clamping control circuit, and the H-bridge control logic is connected with the H-bridge driving circuit. When an external power supply surge arrives, the surge protection circuit can quickly discharge current through the H-bridge driving circuit on the chip, so that the power supply voltage is prevented from exceeding the chip withstand voltage to directly breakdown and burn the chip, no additional device is needed, the reliability of the chip is improved, and the cost is reduced.

Description

Surge protection circuit

Technical Field

The utility model relates to the technical field of surge protection, in particular to a surge protection circuit.

Background

In the application of a motor drive system, some instruments or power supply equipment can generate instantaneous surge energy to be output to a power end of a chip in the working process, and when large energy generated by the surge passes, if the energy cannot be discharged in time, the power voltage exceeds the withstand voltage of the chip to directly break down and burn the chip, so that irreversible damage is caused.

Disclosure of Invention

The utility model aims to provide a surge protection circuit, which can quickly release current when surge energy is transmitted to a power end of a chip, and prevent the chip from being damaged due to overlarge power supply voltage, thereby playing a role in protection.

Based on the above object, the utility model provides a surge protection circuit, which comprises a power supply surge voltage detection circuit, an operation clamping control circuit, an H-bridge control logic and an H-bridge driving circuit, wherein the power supply surge voltage detection circuit is respectively connected with the H-bridge control logic and the operation clamping control circuit, the operation clamping control circuit is connected with the H-bridge control logic, the H-bridge driving circuit is connected with the operation clamping control circuit, and the H-bridge control logic is connected with the H-bridge driving circuit.

Further, the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube of the H-bridge driving circuit, wherein the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with a power supply, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and forms a first output end of the H-bridge driving circuit, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube and forms a second output end of the H-bridge driving circuit, the source electrodes of the first NMOS tube and the second NMOS tube are grounded, and a load is connected between the first output end and the second output end of the H-bridge driving circuit.

Further, the power supply surge voltage detection circuit comprises a first zener diode Z1, a second zener diode Z2, a third zener diode Z3, a fourth zener diode Z4, a fifth zener diode Z5, a first resistor R1, a second resistor R2, a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4, wherein the cathode of the first zener diode Z1 and the first end of the first resistor R1 are connected with a power supply VCC; the anode of the first zener diode Z1, the cathode of the second zener diode Z2, the second end of the first resistor R1, the gate of the third transistor M3, and the gate of the fourth transistor M4 are connected to each other; the anode of the second zener diode Z2 is connected with the cathode of the third zener diode Z3, the anode of the third zener diode Z3 is connected with the cathode of the fourth zener diode Z4, the anode of the fourth zener diode Z4, the cathode of the fifth zener diode Z5, the first end of the second resistor R2, the grid electrode of the first transistor M1 and the grid electrode of the second transistor M2 are connected with each other; the anode of the fifth zener diode Z5, the second end of the second resistor R2, the source of the first transistor M1, and the source of the second transistor M2 are connected to each other and grounded; the grid electrode of the second transistor M2 and the source electrode of the second transistor M2 are also respectively connected with an operation clamping control circuit; the source electrode of the third transistor M3 is connected with a second PMOS tube of the H-bridge driving circuit, and the second output end of the H-bridge control logic is connected with the grid electrode of the second PMOS tube of the H-bridge driving circuit; the drain of the third transistor M3 is connected to the drain of the first transistor M1; the source electrode of the fourth transistor M4 is connected with the grid electrode of the first PMOS tube of the H-bridge driving circuit, and the first output end of the H-bridge control logic is connected with the grid electrode of the first PMOS tube of the H-bridge driving circuit; the drain of the fourth transistor M4 is connected to the drain of the second transistor M2.

Further, the operation clamp control circuit comprises a first stage clamping circuit, wherein the first stage clamping circuit comprises a fifth transistor and a first inverter INV1, a grid electrode of the fifth transistor M0 is connected with a grid electrode of the second transistor M2, a source electrode of the fifth transistor M0 is connected with a source electrode of the second transistor M2, a drain electrode of the fifth transistor M0 is connected with an input end of the first inverter INV1, and an output end of the first inverter INV1 is connected with a first input end of the H-bridge control logic.

Further, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4 and the fifth transistor M0 are PMOS transistors or NMOS transistors.

Further, the operation clamp control circuit further comprises a second-stage clamping circuit, the second-stage clamping circuit comprises a first comparator COMP1 and a second comparator COMP2, the inverting input end of the first comparator COMP1 and the inverting input end of the second comparator COMP2 are connected with a reference voltage VREF, the non-inverting input end of the first comparator COMP1 is connected with the grid electrode of the first NMOS tube of the H bridge driving circuit, and the non-inverting input end of the second comparator COMP2 is connected with the grid electrode of the second NMOS tube of the H bridge driving circuit; an output terminal of the first comparator COMP1 is connected to a second input terminal of the H-bridge control logic, and an output terminal of the second comparator COMP2 is connected to a third input terminal of the H-bridge control logic.

Further, the H-bridge control logic includes a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a NOR gate NOR, a first NAND gate NAND1 and a second NAND gate NAND2, the input terminal of the second inverter INV2 being formed as a first input terminal of the H-bridge control logic, and the two input terminals of the NOR gate NOR being formed as a second input terminal and a third input terminal of the H-bridge control logic, respectively; the output end of the second inverter INV2 is respectively connected with the input end of the third inverter INV3, the input end of the fourth inverter INV4 and the second input end of the second NAND gate NAND 2; the output end of the third inverter INV3 is connected with the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 is formed into a first output end of the H-bridge control logic and is connected with the grid electrode of the first PMOS tube of the H-bridge driving circuit; the output end of the fourth inverter INV4 is respectively connected with the input end of the sixth inverter INV6 and the first input end of the first NAND gate NAND1, and the output end of the sixth inverter INV6 is formed as a second output end of the H-bridge control logic and is connected with the grid electrode of the second PMOS tube of the H-bridge driving circuit; the output end of the NOR gate NOR is respectively connected with the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND 2; the output end of the first NAND gate NAND1 is connected with the input end of a seventh inverter INV7, and the output end of the seventh inverter INV7 is formed as a third output end of the H-bridge control logic and is connected with a first NMOS tube of the H-bridge driving circuit; the output end of the second NAND gate NAND2 is connected with the input end of the eighth inverter INV8, and the output end of the eighth inverter INV8 is formed as a fourth output end of the H-bridge control logic and is connected with a second NMOS tube of the H-bridge driving circuit.

When an external power supply surge arrives, the surge protection circuit can quickly discharge current through the H-bridge driving circuit on the chip, so that the power supply voltage is prevented from exceeding the chip withstand voltage to directly breakdown and burn the chip, no additional device is needed, the reliability of the chip is improved, and the cost is reduced.

Drawings

FIG. 1 is a block schematic diagram of a surge protection circuit according to the present utility model;

FIG. 2 is a schematic diagram of an H-bridge driving circuit according to the present utility model;

FIG. 3 is a schematic diagram of a surge protection circuit according to the present utility model;

fig. 4 is a schematic diagram of the H-bridge control logic according to the present utility model.

Detailed Description

Preferred embodiments of the present utility model will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, an embodiment of the present utility model provides a surge protection circuit, which includes a power supply surge voltage detection circuit 101, an operation clamp control circuit 102, an H-bridge control logic 103 and an H-bridge driving circuit 104, wherein the power supply surge voltage detection circuit 101 is respectively connected to the H-bridge control logic 103 and the operation clamp control circuit 102, the operation clamp control circuit 102 is connected to the H-bridge control logic 103, the H-bridge driving circuit 104 is connected to the operation clamp control circuit 102, and the H-bridge control logic 103 is connected to the H-bridge driving circuit 104. The power supply surge voltage detection circuit 101 is configured to detect a power supply surge voltage exceeding a preset value, and then output a logic control signal to the operation clamp control circuit 102 and the H-bridge control logic 103, where the operation clamp control circuit 102 also outputs a logic control signal to the H-bridge control logic 103, and the H-bridge control logic 103 outputs a logic control signal to the H-bridge driving circuit 104 to perform current leakage through the H-bridge driving circuit 104.

As shown in fig. 2, the H-bridge driving circuit 104 includes a first PMOS transistor 201 (i.e., PMOS 1), a second PMOS transistor 202 (i.e., PMOS 2), a first NMOS transistor 203 (i.e., NMOS 1), and a second NMOS transistor 204 (i.e., NMOS 2), wherein the source of the first PMOS transistor 201 and the source of the second PMOS transistor 202 are connected to a power supply VCC (i.e., a chip power supply), the drain of the first PMOS transistor 201 is connected to the drain of the first NMOS transistor 203 and forms a first output terminal OUT1 of the H-bridge driving circuit 104, the drain of the second PMOS transistor 202 is connected to the drain of the second NMOS transistor 204 and forms a second output terminal OUT2 of the H-bridge driving circuit 104, the source of the first NMOS transistor 203 and the source of the second NMOS transistor 204 are both grounded PGND, an inductive load 205 (e.g., a motor coil) is connected between the first output terminal OUT1 and the second output terminal OUT2, the gate of the first PMOS transistor 201 is connected to a first gate control signal OUTP1, the gate of the second PMOS transistor 202 is connected to a second gate control signal OUTP2, the gate of the first NMOS transistor 203 is connected to a third gate control signal output 2, and the gate of the third NMOS transistor 203 is connected to a fourth gate control signal output 2. According to the properties of the PMOS tube and the NMOS tube, the gate voltage of the PMOS tube is increased to represent the closing action, and the gate voltage of the PMOS tube is reduced to represent the opening action; the gate voltage of the NMOS transistor increases to represent the on-state and decreases to represent the off-state. When the H-bridge driving circuit 104 is operating normally, if the first gate control signal OUTP1 is high, the third gate control signal OUTN1 is high, the second gate control signal OUTP1 is low, and the fourth gate control signal OUTN2 is low, the first PMOS transistor 201 is turned off, the first NMOS transistor 203 is turned on, the second PMOS transistor 202 is turned on, and the second NMOS transistor 204 is turned off, and the current flows as follows: power vcc→the second PMOS transistor 202→the second output terminal OUT2→the load 205→the first output terminal OUT1→the first NMOS transistor 203→ground PGND (as shown by the path (3) in fig. 2); if the first gate control signal OUTP1 is low, the third gate control signal OUTN1 is low, the second gate control signal OUTP1 is high, and the fourth gate control signal OUTN2 is high, the first PMOS transistor 201 will be turned on, the first NMOS transistor 203 will be turned off, the second PMOS transistor 202 will be turned off, and the second NMOS transistor 204 will be turned on, and the current flows as follows: power vcc→the first PMOS transistor 201→the first output terminal OUT1→the load 205→the second output terminal OUT2→the second NMOS transistor 204→the ground PGND. When a surge comes, there are mainly two paths for current to bleed, including the path (1) as in fig. 2: power vcc→first PMOS 201→first NMOS 203→ground PGND (also referred to as left side single side current bleed path) as path (2) in fig. 2: power vcc→the second PMOS transistor 202→the second NMOS transistor 204→ground PGND (also referred to as a right side single side current bleed path). In the case of discharging the current, the current may be discharged through one of the two paths, or the current may be discharged through both paths.

As shown in fig. 3, the power supply surge voltage detection circuit 301 includes a first zener diode Z1, a second zener diode Z2, a third zener diode Z3, a fourth zener diode Z4, a fifth zener diode Z5, a first resistor R1, a second resistor R2, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4, wherein a negative electrode of the first zener diode Z1 and a first end of the first resistor R1 are connected to a power supply VCC; the anode of the first zener diode Z1, the cathode of the second zener diode Z2, the second end of the first resistor R1, the gate of the third transistor M3, and the gate of the fourth transistor M4 are connected to each other; the anode of the second zener diode Z2 is connected with the cathode of the third zener diode Z3, the anode of the third zener diode Z3 is connected with the cathode of the fourth zener diode Z4, the anode of the fourth zener diode Z4, the cathode of the fifth zener diode Z5, the first end of the second resistor R2, the grid electrode of the first transistor M1 and the grid electrode of the second transistor M2 are connected with each other; the anode of the fifth zener diode Z5, the second end of the second resistor R2, the source of the first transistor M1, and the source of the second transistor M2 are connected to each other and grounded PGND; the grid electrode of the second transistor M2 and the source electrode of the second transistor M2 are also respectively connected with the operation clamp control circuit 102; the source electrode of the third transistor M3 is connected with the grid electrode of the second PMOS tube 202 of the H-bridge driving circuit 104; the drain of the third transistor M3 is connected to the drain of the first transistor M1; the source electrode of the fourth transistor M4 is connected with the grid electrode of the first PMOS tube 201 of the H-bridge driving circuit 104; the drain of the fourth transistor M4 is connected to the drain of the second transistor M2.

The first resistor R1 is a large resistor of the power supply VCC for connecting the gates of the third transistor M3 and the fourth transistor M4, and can form a current path from VCC to the gate of M4; the second resistor R2 is a large resistor with the gates of the first transistor M1 and the second transistor M2 connected to the ground, and may form a current path of the gates of the first transistor M1 and the second transistor M2 to the ground.

In some embodiments, the transistors M0-M4 may be PMOS or NMOS transistors.

The operation clamp control circuit 102 includes a first stage clamping circuit 1021 and a second stage clamping circuit 1022, wherein the first stage clamping circuit 1021 includes a fifth transistor M0 and a first inverter INV1, a gate of the fifth transistor M0 is connected to a gate of the second transistor M2, a source of the fifth transistor M0 is connected to a source of the second transistor M2, a drain of the fifth transistor M0 is connected to an input terminal of the first inverter INV1, and an output terminal of the first inverter INV1 is configured to output a first control logic out_s and is connected to a first input terminal of the H-bridge control logic 103. The second stage clamping circuit 1022 comprises a first comparator COMP1 and a second comparator COMP2, wherein an inverting input end of the first comparator COMP1 and an inverting input end of the second comparator COMP2 are connected with a reference voltage VREF, a non-inverting input end of the first comparator COMP1 is connected with a gate of the first NMOS tube 203 of the H-bridge driving circuit 104, and a non-inverting input end of the second comparator COMP2 is connected with a gate of the second NMOS tube 204 of the H-bridge driving circuit 104; an output terminal of the first comparator COMP1 is connected to a second input terminal of the H-bridge control logic 103 for outputting the second control logic out_ss1, and an output terminal of the second comparator COMP2 is connected to a third input terminal of the H-bridge control logic 103 for outputting the third control logic out_ss2.

As shown in fig. 4, the H-bridge control logic 103 includes second to eighth inverters INV2 to INV8, a NOR gate NOR, a first NAND gate NAND1 and a second NAND gate NAND2, an input terminal of the second inverter INV2 is formed as a first input terminal of the H-bridge control logic 103 to receive the first control logic out_s, and two input terminals of the NOR gate NOR are respectively formed as a second input terminal and a third input terminal of the H-bridge control logic 103 to receive the second control logic out_ss1 and the third control logic out_ss2, respectively; the output end of the second inverter INV2 is respectively connected with the input end of the third inverter INV3, the input end of the fourth inverter INV4 and the second input end of the second NAND gate NAND 2; the output end of the third inverter INV3 is connected with the input end of the fifth inverter INV5, the output end of the fifth inverter INV5 is formed as the first output end of the H-bridge control logic 103, and the signal output by the first output end of the H-bridge control logic 103 and the potential signal of the source end of the fourth transistor M4 together form a first gate control signal OUTP1; the output end of the fourth inverter INV4 is respectively connected with the input end of the sixth inverter INV6 and the first input end of the first NAND gate NAND1, the output end of the sixth inverter INV6 is formed as the second output end of the H-bridge control logic 103, and the signal output by the second output end of the H-bridge control logic 103 and the potential signal of the source end of the third transistor M3 together form the second gate control signal OUTP2; the output end of the NOR gate NOR is respectively connected with the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND 2; the output end of the first NAND gate NAND1 is connected with the input end of a seventh inverter INV7, and the output end of the seventh inverter INV7 is formed as a third output end of the H-bridge control logic 103 for outputting a third gate control signal OUTN1; the output terminal of the second NAND gate NAND2 is connected to the input terminal of the eighth inverter INV8, and the output terminal of the eighth inverter INV8 is formed as a fourth output terminal of the H-bridge control logic 103 for outputting the fourth gate control signal OUTN2.

As can be seen from fig. 4, OUTP1, OUTP2, OUTN1 and OUTN2 are controlled by out_ S, OUT _ss1 and out_ss2, OUTP1 and OUTN2 can feedback out_ss2, OUTP2 and OUTN1 can feedback out_ss1, so the logic priority is: out_s→out_ss1 or out_ss2→outp1, OUTP2, OUTN1 and OUTN2. The feedback relationship of OUTP1, OUTP2, OUTN1, and OUTN2 to out_ S, OUT _ss1 and out_ss2 is exemplified as follows ("+" in fig. 4 represents positive feedback, "-" represents negative feedback):

(1)OUT_S→OUTP1→ ^{(front and back)Feed-back} OUT_SS2→OUTN2；

(2)OUT_S→OUTP2→ ^{(Positive feedback)} OUT_SS1→OUTN1；

(3)OUT_S→OUTN2→ ^{(negative feedback)} OUT_SS2→OUTN1→ ^{(negative feedback)} OUT_SS1→OUTN2。

The working principle of the surge protection circuit of the present utility model is described below from the a case and the B case, respectively:

a: if the initial state of the H-bridge drive circuit 104 is OUT2 voltage higher than OUT1, it indicates that current is flowing from OUT2 to OUT1, or if the initial state is OUT1 higher than OUT2, it indicates that current is flowing from OUT1 to OUT2. Taking the example of the current flowing from OUT2 to OUT1, at this time, the second PMOS transistor 202 and the first NMOS transistor 203 are turned on, the first PMOS transistor 201 and the second NMOS transistor 204 are turned off, the OUTP1 is at a high level, the OUTP2 is at a low level, the OUTN1 is at a high level, the OUTN2 is at a low level, the out_s is at a low level, the out_ss1 is at a high level, and the out_ss2 is at a low level. As shown in fig. 3, after the surge energy HVCC is suddenly input to the power supply terminal VCC inside the chip, the power supply surge voltage detection circuit 101 detects whether the voltage of the power supply terminal VCC is higher than a preset value, and when the voltage is higher than the preset value, the voltage exceeds the breakdown voltages of a plurality of reverse connection zener diodes Z1 to Z4, and a current I is formed, and the current I flows through R2, and then the voltage at both ends of R2 is v=i×r2 and is used as bias voltages of the transistors M0, M1, M2, the turned-on fifth transistor M0 changes out_s from low level to high level, out_s enters the H-bridge control logic 103, so that the potential of OUTP1 becomes low, the potential of OUTP2 becomes high, and therefore, the second PMOS transistor 202 of the H-bridge driving circuit 104 is turned off and logic of the surge protection circuit is started; simultaneously, the OUTN1 keeps a high level according to an initial state, the first NMOS tube 203 is fully conducted, and the first PMOS tube 201 is slowly opened, so that current is discharged through the first PMOS tube 201 and the first NMOS tube 203, namely a left unilateral current discharge passage (1) is formed; as the potential of OUTN2 becomes high, the potential of out_ss2 is turned from low to high, after the potential passes through the H-bridge control logic 103, both OUTP1 and OUTP2 are at low level, both PMOS transistors are opened (and the opening degree is determined by the energy of the power supply surge HVCC, the opening degree is larger as the energy is larger), when the current is discharged, the gate voltage of M0 drops below the threshold voltage, out_s is recovered from high level to low level, out_ss1 and out_ss2 are recovered to initial potential, and OUTN1, OUTN2, OUTP1 and OUTP2 are recovered to normal working logic. The signal changes throughout the process are as follows: OUTS rise, OUTN1 rise, OUTP1 fall, OUT_SS2 rise, OUTN2 rise, OUTP2 fall, OUTN2 fall, OUTP2 rise.

B: if the initial state of the H-bridge driving circuit 104 (i.e. the state when the chip circuit is operating normally and the surge is not yet coming) is OUT1 and OUT2 are both low, it indicates that the first NMOS transistor 201 and the second NMOS transistor 202 are all on, and out_ss1 and out_ss2 are both high, and as the H-bridge control logic 103 knows, the OUTP1 and OUTP2 will become low, so the first PMOS transistor 201 and the second PMOS transistor 202 will be turned on gradually, and the H-bridge driving circuit 104 will drain through the paths (1) and (2) simultaneously.

In the above case a, the second NMOS transistor 204 (or the first NMOS transistor 203) is turned on gradually according to the surge energy, under the control of out_s and out_ss1 (or under the control of out_s and out_ss2), PMOS2 is turned off weakly for a period of time to avoid the direct connection of PMOS2 to NMOS2, PMOS2 is turned on again after NMOS2 is completely turned on, and finally VCC is clamped to a designated potential through PMOS1 and PMOS2 transistors; in the process B, as the NMOS1 and NMOS2 tubes are all conducted, VCC can be clamped to a specified potential directly through the PMOS1 and PMOS2 tubes.

After the large current generated by the surge energy is discharged, Z1 to Z4 of the power surge voltage detection circuit 101 are in an off state, and the grid potentials of transistors M1 and M2 in the power surge voltage detection circuit 101 are pulled down to the ground by a path formed by R2, so that the transistors M0, M1 and M2 are all turned off; since the Z1 tube is turned off, the GATE end potentials of the M3 and M4 tubes are pulled up to VCC through R1, turning off the M3 and M4 tubes. Then, the out_ S, OUT _ss1 and out_ss2 are immediately restored to the original potential, the power supply surge voltage detection circuit 101 and the operation clamp control circuit 102 in fig. 3 are stopped, and the chip continues to operate according to the original logic. During the release of the surge energy, where Z5 may clamp the gate potential that protects M1, M2, and M0.

According to the surge protection circuit provided by the embodiment of the utility model, when an external power supply surge arrives, the current can be rapidly discharged through the H-bridge driving circuit 101 on the chip, so that the phenomenon that the power supply voltage exceeds the chip withstand voltage to directly break down and burn the chip is avoided, no additional device is required to be added, the reliability of the chip is improved, and the cost is reduced.

The foregoing description is only a preferred embodiment of the present utility model, and is not intended to limit the scope of the present utility model, and various modifications can be made to the above-described embodiment of the present utility model. All simple, equivalent changes and modifications made in accordance with the claims and the specification of this application fall within the scope of the patent claims. The present utility model is not described in detail in the conventional art.

Claims (7)

1. The surge protection circuit is characterized by comprising a power supply surge voltage detection circuit, an operation clamp control circuit, an H-bridge control logic and an H-bridge driving circuit, wherein the power supply surge voltage detection circuit is respectively connected with the H-bridge control logic and the operation clamp control circuit, the operation clamp control circuit is connected with the H-bridge control logic, the H-bridge driving circuit is connected with the operation clamp control circuit, and the H-bridge control logic is connected with the H-bridge driving circuit.

2. The surge protection circuit of claim 1, wherein the H-bridge driving circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein the source of the first PMOS transistor and the source of the second PMOS transistor are both connected to a power supply, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and forms a first output of the H-bridge driving circuit, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and forms a second output of the H-bridge driving circuit, the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded, and a load is connected between the first output and the second output of the H-bridge driving circuit.

3. The surge protection circuit of claim 2, wherein the power supply surge voltage detection circuit comprises a first zener diode Z1, a second zener diode Z2, a third zener diode Z3, a fourth zener diode Z4, a fifth zener diode Z5, a first resistor R1, a second resistor R2, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4, wherein a negative electrode of the first zener diode Z1 and a first end of the first resistor R1 are connected to a power supply VCC; the anode of the first zener diode Z1, the cathode of the second zener diode Z2, the second end of the first resistor R1, the gate of the third transistor M3, and the gate of the fourth transistor M4 are connected to each other; the anode of the second zener diode Z2 is connected with the cathode of the third zener diode Z3, the anode of the third zener diode Z3 is connected with the cathode of the fourth zener diode Z4, the anode of the fourth zener diode Z4, the cathode of the fifth zener diode Z5, the first end of the second resistor R2, the grid electrode of the first transistor M1 and the grid electrode of the second transistor M2 are connected with each other; the anode of the fifth zener diode Z5, the second end of the second resistor R2, the source of the first transistor M1, and the source of the second transistor M2 are connected to each other and grounded; the grid electrode of the second transistor M2 and the source electrode of the second transistor M2 are also respectively connected with an operation clamping control circuit; the source electrode of the third transistor M3 is connected with a second PMOS tube of the H-bridge driving circuit, and the second output end of the H-bridge control logic is connected with the grid electrode of the second PMOS tube of the H-bridge driving circuit; the drain of the third transistor M3 is connected to the drain of the first transistor M1; the source electrode of the fourth transistor M4 is connected with the grid electrode of the first PMOS tube of the H-bridge driving circuit, and the first output end of the H-bridge control logic is connected with the grid electrode of the first PMOS tube of the H-bridge driving circuit; the drain of the fourth transistor M4 is connected to the drain of the second transistor M2.

4. The surge protection circuit of claim 3 wherein the operational clamp control circuit comprises a first stage clamping circuit, wherein the first stage clamping circuit comprises a fifth transistor and a first inverter INV1, wherein a gate of the fifth transistor M0 is connected to a gate of the second transistor M2, wherein a source of the fifth transistor M0 is connected to a source of the second transistor M2, wherein a drain of the fifth transistor M0 is connected to an input of the first inverter INV1, and wherein an output of the first inverter INV1 is connected to a first input of the H-bridge control logic.

5. The surge protection circuit of claim 4 wherein the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M0 are PMOS or NMOS transistors.

6. The surge protection circuit of claim 4 wherein the operational clamp control circuit further comprises a second stage clamping circuit comprising a first comparator COMP1 and a second comparator COMP2, the inverting input of the first comparator COMP1 and the inverting input of the second comparator COMP2 are both connected to the reference voltage VREF, the non-inverting input of the first comparator COMP1 is connected to the gate of the first NMOS transistor of the H-bridge drive circuit, and the non-inverting input of the second comparator COMP2 is connected to the gate of the second NMOS transistor of the H-bridge drive circuit; an output terminal of the first comparator COMP1 is connected to a second input terminal of the H-bridge control logic, and an output terminal of the second comparator COMP2 is connected to a third input terminal of the H-bridge control logic.

7. The surge protection circuit of claim 6, wherein the H-bridge control logic comprises a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a NOR gate NOR first NAND gate NAND1 and a second NAND gate NAND2, an input of the second inverter INV2 being formed as a first input of the H-bridge control logic, two inputs of the NOR gate NOR being formed as a second input and a third input of the H-bridge control logic, respectively; the output end of the second inverter INV2 is respectively connected with the input end of the third inverter INV3, the input end of the fourth inverter INV4 and the second input end of the second NAND gate NAND 2; the output end of the third inverter INV3 is connected with the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 is formed into a first output end of the H-bridge control logic and is connected with the grid electrode of the first PMOS tube of the H-bridge driving circuit; the output end of the fourth inverter INV4 is respectively connected with the input end of the sixth inverter INV6 and the first input end of the first NAND gate NAND1, and the output end of the sixth inverter INV6 is formed as a second output end of the H-bridge control logic and is connected with the grid electrode of the second PMOS tube of the H-bridge driving circuit; the output end of the NOR gate NOR is respectively connected with the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND 2; the output end of the first NAND gate NAND1 is connected with the input end of a seventh inverter INV7, and the output end of the seventh inverter INV7 is formed as a third output end of the H-bridge control logic and is connected with a first NMOS tube of the H-bridge driving circuit; the output end of the second NAND gate NAND2 is connected with the input end of the eighth inverter INV8, and the output end of the eighth inverter INV8 is formed as a fourth output end of the H-bridge control logic and is connected with a second NMOS tube of the H-bridge driving circuit.