CN220709660U - Arbitrary multichannel multiplexing processor - Google Patents

Abstract

The utility model relates to the technical field of electronic circuits, in particular to an arbitrary multichannel multiplexing processor. By adding a simple dual-port random access memory accompanying module in the circuit, all the input and output of the simple dual-port random access memory are connected to the simple dual-port random access memory accompanying module, and the output signal of the simple dual-port random access memory accompanying module is used as an input signal of the simple dual-port random access memory accompanying module to replace the read data of the simple dual-port random access memory module and is used as new read data (the previous state) to be input into the common processing logic part. If the simple dual-port random access memory accompanying module and the simple dual-port random access memory are packaged into a new module (which can be named as SDP_RAM_S), the input and output signals of the SDP_RAM_S and the simple dual-port random access memory are identical, the design is convenient for upgrading and replacing the existing design, and only the simple dual-port random access memory is needed to be replaced by the SDP_RAM_S, so that the workload is greatly saved.

Description

Arbitrary multichannel multiplexing processor

Technical Field

The utility model relates to the technical field of electronic circuits, in particular to an arbitrary multichannel multiplexing processor.

Background

The multi-channel multiplexing process is a technology frequently used in circuit design or chip design, and uses the same logic resource to process tasks of different channels in a time sharing way, which has the advantages of saving logic resources, and saving more logic resources as the number of channels is increased. The multi-channel multiplexing processing circuit basically consists of common processing logic and sdp_ram (simple dual-port random access memory). The common processing logic is typically purely combinational logic, completed in 1 clock cycle (also called 1 beat), which is not part of our discussion and attention here. Sdp_ram (simple dual-port random access memory) contains one write port and one read port. The channel number is used as a read address, the previous state is read after delaying N beats, the previous state and the external signal are processed by the common processing logic to generate a new state, which is written through the writing port. To align the channels, the channel number is delayed by N beats and then used as the write address. Assuming that the sdp_ram (simple dual-port random access memory) has a read delay of N (equal to or greater than 0), a write delay of M (equal to or greater than 1), and a minimum interval of the same channel number of D (equal to or greater than 1), the condition that the circuit can operate normally is D > = (m+n).

However, in some applications, the system requirement D is equal to 1 (i.e. the same channel number may occur at any time, the channel multiplexing relationship is not limited at all), and the requirement cannot be met when m+n is greater than 1 (typically, the number of channels is too large or (and) the clock frequency is high, and m+n is equal to 1 and cannot meet the timing index).

Disclosure of Invention

In order to solve the defects in the prior art, the utility model aims to provide an arbitrary multi-channel multiplexing processor, which can realize that the same channel number can appear at any time, and the channel multiplexing relation is not limited at all, namely, the multiplexing processor solves the problem that D is equal to 1 and M+N is larger than 1 in the background art.

The technical scheme adopted by the utility model is as follows: an arbitrary multi-channel multiplexing processor comprises a common processing logic unit, a simple dual-port random access memory and a delayer; the system also comprises a simple dual-port random access memory accompanying module; the public processing logic is connected with the simple dual-port random access memory through signals, the simple dual-port random access memory is connected with the simple dual-port random access memory accompanying module through signals, the public processing logic is also connected with external signals, the simple dual-port random access memory and the simple dual-port random access memory accompanying module are both connected with write enable signals and channel number signals, and the channel number signals are also connected with the public processing logic through signals through a time delay device; the simple dual-port random access memory accompanying module comprises a data selector, an input shift register and a multiplexing controller, wherein the input shift register is connected with the data selector, the data selector is connected with read data of the simple dual-port random access memory, the input of the input shift register is connected with write data of the simple dual-port random access memory, the output of the data selector is used as the output of the simple dual-port random access memory accompanying module and is connected with the common processing logic, and the multiplexing controller is connected with a write enable signal, a write address signal and a read address signal of the simple dual-port random access memory;

further, the data selector adopts a four-out data selector, the four-out data selector is connected with three paths of input shift registers, the three paths of input shift registers are respectively marked as a first shift register, a second shift register and a third shift register, the output of the first shift register is used as the input of the four-out data selector and the second shift register, the output of the second shift register is used as the input of the four-out data selector and the third shift register, and the output of the third shift register is used as the input of the four-out data selector; the read data signal of the simple dual port random access memory is used as the input of the one-out-of-four data selector.

Further, the data selector adopts one-out-of-four data selector, the output of the one-out-of-four data selector is also connected with an output register, and the output of the output register is used as the output of the simple dual-port random access memory accompanying module; the four-way data selector is connected with two ways of input shift registers, and is respectively marked as a first shift register and a second shift register; the four-out data selector is also connected with a read data signal and a write data signal of the simple double-port random access memory, wherein the write data signal of the simple double-port random access memory is used as the input of the first shift register, the output of the first shift register is respectively connected with the four-out data selector and the second shift register to be used as the input of the four-out data selector and the second shift register, and the output of the first shift register is connected with the four-out data selector to be used as the output of the four-out data selector.

The beneficial effects are that: the utility model provides an arbitrary multi-channel multiplexing processor, a simple dual-port random access memory accompanying module is added in a circuit, all inputs and outputs of a simple dual-port random access memory are connected to the simple dual-port random access memory accompanying module, the input signals of the simple dual-port random access memory accompanying module are used as input signals of the simple dual-port random access memory accompanying module, the output signals of the simple dual-port random access memory accompanying module replace the read data of the simple dual-port random access memory module, and the read data are used as new read data (the previous state) to be input to a public processing logic part. If the simple dual-port random access memory accompanying module and the simple dual-port random access memory are packaged into a new module (which can be named as SDP_RAM_S), the input and output signals of the SDP_RAM_S and the simple dual-port random access memory are identical, the design is convenient for upgrading and replacing the existing design, and only the simple dual-port random access memory is needed to be replaced by the SDP_RAM_S, so that the workload is greatly saved.

Drawings

FIG. 1 is a schematic diagram of an arbitrary multi-channel multiplexing processor according to the present utility model;

FIG. 2 is a schematic diagram of a simple dual port RAM companion module of embodiment 1 of an arbitrary multi-channel multiplexing processor according to the present utility model;

FIG. 3 is a schematic diagram of a simple dual port RAM companion module of embodiment 2 of an arbitrary multi-channel multiplexing processor according to the present utility model;

FIG. 4 is a schematic diagram of the basic architecture of the multi-channel multiplexing circuit mentioned in the background art;

wherein, the A-common processing logic, SDP_RAM-simple dual-port random access memory, Y-delayer, SDP_RAM_Mate-simple dual-port random access memory accompanying module, MUX-data selector, MUX_CTL-multiplexing controller, ISR 1-first shift register, ISR 2-second shift register, ISR 3-third shift register, OR-output register.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the utility model, fall within the scope of protection of the utility model.

An arbitrary multi-channel multiplexing processor as shown in fig. 1, comprising a common processing logic a, a simple dual-port random access memory sdp_ram, and a delay Y; the system also comprises a simple dual-port random access memory accompanying module SDP_RAM_Mate; the public processing logic A is connected with a simple dual-port random access memory SDP_RAM through signals, the simple dual-port random access memory SDP_RAM is connected with a simple dual-port random access memory accompanying module SDP_RAM_Mate through signals, the public processing logic A is also connected with external signals, the simple dual-port random access memory SDP_RAM and a simple dual-port random access memory accompanying module SDP_RAM_Mate block are both connected with write enable signals and channel number signals, and the channel number signals are also connected with the public processing logic A through signals of a delay device Y; the simple dual-port random access memory accompanying module SDP_RAM_Mate comprises a data selector MUX, an input shift register and a multiplexing controller MUX_CTL, wherein the input shift register is connected with the data selector MUX, the data selector MUX is connected with a read data interface of the simple dual-port random access memory SDP_RAM, the input of the input shift register is connected with a write data interface of the simple dual-port random access memory SDP_RAM, the output of the data selector MUX is used as the output of the simple dual-port random access memory SDP_RAM_Mate and is connected with a common processing logic A, and the multiplexing controller MUX is connected with a write enable signal, a write address signal and a read address signal of the simple dual-port random access memory SDP_RAM.

Example 1:

the simple dual-port random access memory accompanying module shown in fig. 2, the data selector MUX adopts a four-way data selector, the four-way data selector is connected with three paths of input shift registers, which are respectively marked as a first shift register ISR1, a second shift register ISR2 and a third shift register ISR3, the output of the first shift register ISR1 is used as the input of the four-way data selector and the second shift register ISR2, the output of the second shift register ISR2 is used as the input of the four-way data selector and the third shift register ISR3, and the output of the third shift register ISR3 is used as the input of the four-way data selector; the read data signal of the simple dual port random access memory sdp_ram is used as the input to the one-out-of-four data selector.

The data selector MUX adopts a four-out data selector, which selects a corresponding input signal as output according to the value of the input signal MUX_SEL [1:0], and the specific actions are as follows: MUX_SEL [1:0] is equal to 0, the output of the first shift register ISR1 is selected as the output of the data selector MUX, MUX_SEL [1:0] is equal to 1, the output of the second shift register ISR2 is selected as the output of MUX, MUX_SEL [1:0] is equal to 2, the output of the third shift register ISR3 is selected as the output of MUX, MUX_SEL [1:0] is equal to 3, and simple dual-port random access memory SDP_RAM read data is selected as the output of MUX. The first shift register ISR1 is the 1 st input shift register, and the output of the first shift register ISR1 is equal to the simple dual-port random access memory sdp_ram write data under the simple dual-port random access memory sdp_ram write enable. The second shift register ISR2 is the 2 nd input shift register, and the output of the second shift register ISR2 is equal to the output of ISR1 with the simple dual port random access memory sdp_ram write enabled. The third shift register ISR3 is the 3 rd input shift register, and the output of the third shift register ISR3 is equal to the output of the second shift register ISR2 with the simple dual port random access memory sdp_ram write enabled. The number of input shift registers is equal to M + N-1, here 3 input shift registers are used to illustrate the case where M + N is equal to 4, as this is a more common case. The multiplexing controller MUX_CTL module generates selection signals MUX_SEL [1:0] of the data selector MUX according to the write enabling of the SDP_RAM of the simple dual-port random access memory, and the write address and the read address, wherein the MUX_SEL [1:0] selects proper data from the SDP_RAM read data of the simple dual-port random access memory, the output of the first shift register ISR1, the output of the second shift register ISR2 and the output of the third shift register ISR3 as the output of the SDP_RAM_Mate of the simple dual-port random access memory. It can be seen that the mux_ctl module logic implementation of the multiplexing controller is the core of the present utility model, and its working logic is as follows:

if the current write enable is active and the current write address is equal to the read address lagging by 1 beat, MUX_SEL [1:0] is equal to 0, the first shift register ISR1 is selected.

If the lag 1 beat write enable is valid and the lag 1 beat write address is equal to the lag 1 beat read address, if the previous 1 beat is not write enable, the input shift register is not shifted, so MUX_SEL [1:0] is equal to 0, or the third shift register ISR1 is selected; if the previous 1 beat has write enable, the input shift register is shifted 1 time, so MUX_SEL [1:0] equals 1, selecting the second shift register ISR2.

If the lag 2 beat write enable is valid and the lag 2 beat write address is equal to the lag 1 beat read address, if the previous 2 beats have no write enable, the input shift register has no shift, so MUX_SEL [1:0] is equal to 0, or the third shift register ISR1 is selected; if the first 2 beats have 1 write enable, the input shift register shifts 1 time, so MUX_SEL [1:0] is equal to 1, and the second shift register ISR2 is selected; if 2 beats have 2 write enables, the input shift register shifts 2 times, so MUX_SEL [1:0] equals 2, selecting the third shift register ISR3.

In other cases than the above, MUX_SEL [1:0] is equal to 3, and simple dual port random access memory SDP_RAM is selected to read data.

As can be seen from the SDP_RAM_Mate module of the simple dual-port random access memory accompanying module, the first-stage data selector MUX is introduced and then the first-stage data selector MUX is not used for outputting, so that the whole circuit has more first-stage logic layers, and the time sequence index can not be met in the occasion of higher clock frequency. Thus, the present utility model provides another modification of the simple dual port random access memory companion module sdp_ram_mate module, see in detail example 2.

Example 2:

as shown in fig. 3, the simple dual-port random access memory accompanying module sdp_ram_mate adopts a data selector MUX, and the output of the data selector MUX is further connected with an output register OR, where the output of the output register OR is used as the output of the simple dual-port random access memory accompanying module sdp_ram_mate; the four-way data selector is connected with two ways of input shift registers, and is respectively marked as a first shift register ISR1 and a second shift register ISR2; the four-out data selector is also connected with a read data signal and a write data signal of the simple dual-port random access memory SDP_RAM, wherein the write data signal of the simple dual-port random access memory SDP_RAM is used as the input of a first shift register ISR1, the output of the first shift register ISR1 is respectively connected with the four-out data selector and a second shift register ISR2 to be used as the input of the four-out data selector and the second shift register ISR2, and the output of the first shift register ISR1 is connected with the four-out data selector to be used as the output of the four-out data selector

The improved form of the simple dual-port random access memory accompanying module SDP_RAM_Mate has little difference from the form of the embodiment 1, one path of input bit registers are removed, and an output register OR is added, so that the output of the simple dual-port random access memory accompanying module SDP_RAM_Mate is changed from combination logic to register output, the circuit logic level is reduced, and the time sequence performance is improved. Of course, the read data output delay of the SDP_RAM of the simple dual-port random access memory should be reduced by 1 beat, so as to ensure that the time sequence beat of the whole circuit is unchanged. The mux_ctl module of this form of multiplexing controller is logically as follows:

if the current write enable is valid and the current write address is equal to the read address lagging by 1 beat, MUX_SEL [1:0] is equal to 0, the simple dual port random access memory SDP_RAM is selected to write data.

If the lag 1 beat write enable is active and the lag 1 beat write address is equal to the lag 1 beat read address, MUX_SEL [1:0] is equal to 1, the first shift register ISR1 is selected.

If the lag 2 beat write enable is valid and the lag 2 beat write address is equal to the lag 1 beat read address, if the previous 1 beat has no write enable, the input shift register has no shift, MUX_SEL [1:0] is equal to 1, and the first shift register ISR1 is selected; in other cases, MUX_SEL [1:0] is equal to 2, selecting the second shift register ISR2.

In other cases than the above, MUX_SEL [1:0] is equal to 3, and simple dual-port random access memory SDP_RAM is selected to read data

The present specification exemplifies only the case where m+n is equal to 4, and for m+n is equal to 2 or 3, the selection logic is simpler than this, but the principle is the same and is also protected by the present utility model.

Claims (3)

1. An arbitrary multichannel multiplexing processor, including public processing logic ware, simple two mouthfuls of random access memory and delayer, its characterized in that: the system also comprises a simple dual-port random access memory accompanying module; the public processing logic is connected with the simple dual-port random access memory through signals, the simple dual-port random access memory is connected with the simple dual-port random access memory accompanying module through signals, the public processing logic is also connected with external signals, the simple dual-port random access memory and the simple dual-port random access memory accompanying module are both connected with write enable signals and channel number signals, and the channel number signals are also connected with the public processing logic through signals through a time delay device; the simple dual-port random access memory accompanying module comprises a data selector, an input shift register and a multiplexing controller, wherein the input shift register is connected with the data selector, the data selector is connected with read data of the simple dual-port random access memory, the input of the input shift register is connected with write data of the simple dual-port random access memory, the output of the data selector is used as the output of the simple dual-port random access memory accompanying module and is connected with the common processing logic, and the multiplexing controller is connected with a write enable signal, a write address signal and a read address signal of the simple dual-port random access memory.

2. An arbitrary multi-channel multiplexing processor as defined in claim 1, wherein: the data selector adopts a four-out data selector, the four-out data selector is connected with three paths of input shift registers, the three paths of input shift registers are respectively marked as a first shift register, a second shift register and a third shift register, the output of the first shift register is used as the input of the four-out data selector and the second shift register, the output of the second shift register is used as the input of the four-out data selector and the third shift register, and the output of the third shift register is used as the input of the four-out data selector; the read data signal of the simple dual port random access memory is used as the input of the one-out-of-four data selector.

3. An arbitrary multi-channel multiplexing processor as defined in claim 1, wherein: the data selector adopts one-out-of-four data selector, the output of the one-out-of-four data selector is also connected with an output register, and the output of the output register is used as the output of the simple dual-port random access memory accompanying module; the four-way data selector is connected with two ways of input shift registers, and is respectively marked as a first shift register and a second shift register; the four-out data selector is also connected with a read data signal and a write data signal of the simple double-port random access memory, wherein the write data signal of the simple double-port random access memory is used as the input of the first shift register, the output of the first shift register is respectively connected with the four-out data selector and the second shift register to be used as the input of the four-out data selector and the second shift register, and the output of the first shift register is connected with the four-out data selector to be used as the input of the four-out data selector.