CN220652000U

CN220652000U - Semiconductor packaging device

Info

Publication number: CN220652000U
Application number: CN202322270404.XU
Authority: CN
Inventors: 林正蓝; 廖国成
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2023-08-23
Filing date: 2023-08-23
Publication date: 2024-03-22
Anticipated expiration: 2033-08-23

Abstract

The application proposes a semiconductor packaging device comprising: an electronic component and a conductive layer over the electronic component; the conductive layer includes: a signal line layer; a patterned heat conductive layer configured to conduct heat generated by the electronic component to an outside of the device; the patterned heat conducting layer is closer to the electronic element than the signal circuit layer. According to the electronic component, the patterned heat conducting layer is arranged in the conductive layer above the electronic component, so that heat generated by the electronic component is conducted to the outside of the device, and the patterned heat conducting layer is arranged in the conductive layer and is closer to the electronic component than the signal circuit layer in the conductive layer, so that a better heat dissipation effect can be achieved, and the manufacturing process difficulty is reduced compared with that of directly arranging the heat conducting structure on the electronic component.

Description

Semiconductor packaging device

Technical Field

The present disclosure relates to the field of semiconductor packaging technology, and in particular, to a semiconductor packaging apparatus.

Background

The processor of the 5G handset mostly completes the package in a POP (Package on Package, laminate package) structure. POP structures include HBPOP (high bandwidth package on package, high bandwidth stack package) and FOPOP (fan out package on package, fan-out stack package), among others.

As packaging requirements for high-end products increase, heat dissipation problems become more serious. In the current HBPOP structure, an AP (Applicat ion Processor ) chip is mounted on a substrate and is encapsulated by a Mold Compound, and the heat conductivity coefficients of the substrate material and the Mold Compound are low, so that the heat dissipation efficiency is low, overheating is caused, and the product performance is reduced.

In order to improve heat dissipation performance, some POP-structured products may provide a heat conductive structure on the AP chip, where the heat conductive structure includes a pad (pad) connected to the AP chip and a solder (holder) connected to the pad. However, providing the heat conducting structure directly on the AP chip increases the process difficulty.

Disclosure of Invention

The application provides a semiconductor packaging device for solve in the POP packaging structure set up the technical problem that heat conduction structure can increase the processing procedure degree of difficulty on the AP chip.

The application provides a semiconductor packaging device, includes: an electronic component and a conductive layer over the electronic component; the conductive layer includes: a signal line layer; a patterned heat conductive layer configured to conduct heat generated by the electronic component to an outside of the device; the patterned heat conducting layer is closer to the electronic element than the signal circuit layer.

In some alternative embodiments, the patterned heat conductive layer is exposed on the lower surface of the conductive layer, and the width of the patterned heat conductive layer is greater than or equal to the width of the electronic component.

In some alternative embodiments, the semiconductor packaging apparatus further includes: a bottom substrate, which is positioned below the electronic element to bear the electronic element; the electric connector is positioned on at least one side of the electronic element and is used for electrically connecting the conductive layer and the bottom substrate; wherein an edge of the patterned thermally conductive layer is closer to the electrical connection than the electronic component.

In some alternative embodiments, the patterned thermally conductive layer includes a thermally conductive metal face directly over the electronic component that covers the electronic component in a top view.

In some alternative embodiments, the bottom surface of the thermally conductive metal face includes a plurality of protrusions.

In some alternative embodiments, the semiconductor packaging apparatus further includes: the mold sealing material is positioned below the conductive layer and covers the electronic element; wherein the convex portion extends into the mold seal material.

In some alternative embodiments, the protrusion contacts the electronic component.

In some alternative embodiments, the conductive layer further includes a plurality of thermal vias connecting the patterned thermal conductive layer, the thermal vias passing through the signal line layer.

In some alternative embodiments, the conductive layer further comprises: the signal through holes are positioned at the outer sides of the heat conducting through holes, and the distribution density of the heat conducting through holes is larger than that of the signal through holes.

In some alternative embodiments, the thermally conductive vias have a smaller diameter than the signal vias.

In some optional embodiments, the conductive layer further includes a patterned heat dissipation layer disposed above the signal line layer and exposed on an upper surface of the conductive layer, and the patterned heat dissipation layer is connected to the heat conductive via.

In some alternative embodiments, the upper and lower surfaces of the conductive layer have solder masks, respectively, with openings exposing the patterned thermally conductive layer and the patterned heat sink layer.

In order to solve the technical problem that the extra heat conduction structure arranged on the AP chip in the POP packaging structure can increase the processing difficulty, the application provides a semiconductor packaging device, and the heat generated by an electronic element is conducted to the outside of the device by arranging a patterned heat conduction layer in a conductive layer above the electronic element.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:

fig. 1 is a schematic longitudinal sectional structure of one embodiment 1a of a semiconductor package apparatus according to the present application;

FIGS. 2-4 are schematic diagrams of the L1-L3 layers, respectively, of the conductive layers in the semiconductor package apparatus shown in FIG. 1;

fig. 5 is a schematic longitudinal sectional structure of an embodiment 5a of a semiconductor package apparatus according to the present application;

fig. 6 is a schematic longitudinal sectional structure of an embodiment 6a of a semiconductor package apparatus according to the present application.

Reference numerals/symbol description:

10-an underlying substrate; 11-an electronic component; 12-underfill; 13-a first electrical connection; 14-molding a sealing material; 15-a second electrical connection; 16-integrated passive devices; 20-a conductive layer; 21-a signal line layer; 22-patterning the heat conducting layer; 220-a thermally conductive metal face; 221-a protrusion; 23-a dielectric layer; 24-heat conducting through holes; 25-signal vias; 26-patterning a heat dissipation layer; 260-heat dissipating metal surface; 27-a solder mask layer; 270-opening.

Detailed Description

The technical problems to be solved by the present application and the technical effects to be produced will be readily apparent to those skilled in the art from the descriptions of the present application, which are described in the following detailed description of the present application with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant utility model and are not limiting of the utility model. In addition, for convenience of description, only parts related to the relevant utility model are shown in the drawings.

It should be readily understood that the meanings of "on," "above," and "above" in this application should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

The term "redistribution layer (RDL)" as used herein may be composed of conductive and Dielectric materials (Dielectric). It should be noted that the process may use currently known or future developed techniques for forming the re-wiring layer, which are not limited in this application, and may include, for example, photolithography, electroplating (plating), electroless plating (Electroless plating), etc. Here, the dielectric material may include organic and/or inorganic matters, wherein the organic matters may be, for example: polyamide fibers (PA), polyimide (PI), epoxy resins (Epoxy), poly-p-phenylene benzobisoxazole, PBO) fibers, FR-4 Epoxy glass laminates, PP (pre reg, prePreg, or semi-cured resins, prepregs), ABF (Aj inomoto Build-up films), etc., while the inorganic material may be, for example, silicon (Si), glass, ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), or the like, and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the descriptions of the embodiments and should not be construed as limiting the applicable limitations of the present application, so that any modification, variation of proportions, or adjustment of sizes of structures, proportions, etc. which are not intended to affect the efficacy of the present application or the objects achieved, are still within the scope of what is disclosed herein. Also, the terms "upper", "first", "second", and "a" and "an" as used in the present specification are merely for descriptive purposes and are not intended to limit the scope of the utility model in which the utility model may be practiced or their relative relationships may be altered or modified without materially altering the technical context.

It should be further noted that, in the embodiment of the present application, the corresponding longitudinal section may be a section corresponding to a front view direction, the corresponding transverse section may be a section corresponding to a right view direction, and the corresponding horizontal section may be a section corresponding to an upper view direction.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Referring to fig. 1, fig. 1 is a schematic longitudinal sectional structure of one embodiment 1a of a semiconductor package apparatus according to the present application. As shown in fig. 1, a semiconductor package apparatus 1a of the present application includes: an electronic component 11 and a conductive layer 20 located above the electronic component 11; the conductive layer 20 includes a signal wiring layer 21 and a patterned heat conductive layer 22, the patterned heat conductive layer 22 being configured to conduct heat generated by the electronic component 11 to the outside of the device; wherein the patterned heat conductive layer 22 is closer to the electronic component 11 than the signal line layer 21.

Here, the electronic component 11 includes, but is not limited to, a chip, such as an AP (application processor) chip.

Here, the conductive layer 20 includes, but is not limited to, a substrate or an interposer or a rewiring layer, and may be, for example, a glass fiber resin substrate, or may be a ceramic substrate. The material of the signal line layer 21 and the patterned heat conductive layer 22 in the conductive layer 20 may be various metals such as copper. The conductive layer 20 may further include a dielectric layer 23 that separates the signal trace layer 21 and the patterned thermally conductive layer 22. The material of the dielectric layer 23 may be various insulating materials such as PI (polyimide).

Here, the patterned heat conducting layer 22 is disposed in the conductive layer 20 above the electronic component 11 to conduct the heat generated by the electronic component 11 to the outside of the device, and because the patterned heat conducting layer 22 is disposed in the conductive layer 20 and is closer to the electronic component 11 than the signal circuit layer 21 in the conductive layer 20, a better heat dissipation effect can be obtained and the difficulty of the manufacturing process is reduced.

In some alternative embodiments, the patterned thermally conductive layer 22 is interposed between the electronic component 11 and the signal line layer 21. Therefore, the patterned heat conductive layer 22 is closer to the electronic component 11 than the signal circuit layer 21, so as to obtain better heat conductive effect.

In some alternative embodiments, the patterned heat conductive layer 22 is exposed on the lower surface of the conductive layer 20, and the width of the patterned heat conductive layer 22 is greater than or equal to the width of the electronic component 11. And optionally, the patterned thermally conductive layer 22 overlaps (or covers) the electronic component 11 in a top view. Therefore, the patterned heat conducting layer 22 is closer to the electronic element 11, the heat conducting area is larger, and the heat conducting effect is better.

In some alternative embodiments, the conductive layer 20 further includes:

a patterned heat dissipation layer 26 located above the signal line layer 21;

the plurality of heat conducting through holes 24 are connected with the patterned heat conducting layer 22, and after passing through the signal circuit layer 21, are connected with the patterned heat dissipation layer 26.

Here, the heat conductive via 24 may be a metallized via.

Here, the patterned heat-conducting layer 22 is connected to the patterned heat-dissipating layer 26 through the plurality of heat-conducting through holes 24, the patterned heat-dissipating layer 26 is located outside the device, and the waste heat emitted by the electronic component 11 can be conducted to the patterned heat-dissipating layer 26, and the waste heat is dissipated to the outside through the patterned heat-dissipating layer 26.

In some alternative embodiments, the patterned heat dissipation layer 26 is exposed on the upper surface of the conductive layer 20 and directly contacts the outside to improve the heat dissipation efficiency.

In some alternative embodiments, the thermally conductive vias 24 are insulated from the signal wiring layer 21.

In some alternative embodiments, the conductive layer 20 further includes a plurality of signal vias 25 electrically connected to the signal trace layer 21. The signal via 25 may pass through the patterned conductive layer 22 downward to electrically connect with other structures under the conductive layer 20; the signal via 25 may also pass upward through the patterned heat spreader 26 to electrically connect with other structures located above the conductive layer 20.

In some alternative embodiments, the plurality of signal vias 25 are located outside the heat conductive vias 24, and the distribution density of the heat conductive vias 24 is greater than the signal vias 25.

In some alternative embodiments, the diameter of the thermally conductive via 24 is smaller than the signal via 25.

In some alternative embodiments, the upper and lower surfaces of the conductive layer 20 are each provided with a solder resist layer 27, the solder resist layer 27 including, but not limited to, a green paint. Here, the solder resist layer 27 may entirely cover the patterned heat conductive layer 22 and the patterned heat dissipation layer 26. Optionally, to increase the heat dissipation efficiency, the solder mask layer 27 may have openings 270 exposing the patterned heat conductive layer 22 and the patterned heat dissipation layer 26. Patterned thermally conductive layer 22 and patterned heat sink layer 26 may be fully exposed or partially exposed from opening 270. Thus, the heat conduction and heat dissipation efficiency is improved.

In some alternative embodiments, only one signal trace layer 21 is present in the conductive layer 20. At this time, the conductive layer 20 has three layers from bottom to top, denoted by L1 to L3, respectively. Referring to fig. 2-4, fig. 2-4 are schematic diagrams of the L1-L3 layers, respectively, of conductive layer 20. The layer L1 is a patterned heat conductive layer 22, the layer L2 is a signal line layer 21, and the layer L3 is a patterned heat dissipation layer 26.

In some alternative embodiments, in conjunction with fig. 1-4: the patterned thermally conductive layer 22 may include a thermally conductive metal face 220 directly over the electronic component 11, covering the electronic component 11 in a top view. The thermally conductive metal face 220 may be, for example, a large copper face. The patterned heat sink layer 26 may include a heat sink metal surface 260 directly above the heat conductive metal surface 220 and overlapping (fully overlapping or partially overlapping) the heat conductive metal surface 220 in a top view. The heat sink metal surface 260 may be, for example, a large copper surface. The patterned heat conductive layer 22 and the patterned heat dissipation layer 26 may be connected by a plurality of heat conductive vias 24 through the signal wiring layer 21. The plurality of heat conductive vias 24 may be arranged in a rectangular array. As can be seen from fig. 2 and 4, the signal via 25 is located outside (or on the periphery of) the heat conductive metal surface 220 and the heat dissipating metal surface 260 in a plan view.

As described above, the regions of the L1 layer and the L3 layer corresponding to the electronic component 11 may be designed with a complete bulk metal layer (copper layer), so as to form the large-area heat conductive metal surface 220 and the heat dissipation metal surface 260, thereby achieving good heat conduction and heat dissipation effects.

With continued reference to fig. 1, in some alternative embodiments, the semiconductor package apparatus 1a further includes:

a bottom substrate 10 located below the electronic component 11 to carry the electronic component 11;

the first electrical connector 13 is located on at least one side of the electronic component 11 and is used for electrically connecting the conductive layer 20 and the underlying substrate 10.

In some alternative embodiments, the semiconductor package apparatus 1a further includes:

the molding compound 14 is disposed below the conductive layer 20 and between the conductive layer 20 and the underlying substrate 10, and is used for encapsulating the electronic component 11 and the first electrical connector 13, and for carrying the conductive layer 20.

Here, the base substrate 10 may include a plurality of wiring layers and a plurality of dielectric layers. Alternatively, the base substrate 10 may be a fiberglass resin substrate, or may be a ceramic substrate.

Here, the electronic component 11 may be mounted on the base substrate 10 in a flip-chip manner and electrically connected to the base substrate 10 through bumps (bumps). Optionally, an underfill 12 may be disposed in the gap between the electronic component 11 and the underlying substrate 10, the underfill 12 being used to strengthen the electronic component 11 and protect the bumps.

Here, the first electrical connector 13 includes, but is not limited to, a Solder ball (Solder ball). The first electrical connection 13 may have a height higher than the electronic component 11.

Here, the Molding material 14 may be formed of various Molding materials (Molding Compound). For example, the molding material may include Epoxy (Epoxy resin), filler (Fi ller), catalyst (Pigment), release Agent (Release Agent), flame Retardant (Flame Retardant), coupling Agent (coupling Agent), hardener (Hardener), low stress absorber (Low Stress Absorber), adhesion promoter (Adhesion Promoter), ion trap Agent (Ion Trapping Agent), and the like.

In some alternative embodiments, the edges of the patterned thermally conductive layer 22 are closer to the first electrical connectors 13 than the electronic component 11. Thus, the heat conduction area of the patterned heat conduction layer 22 is larger, and the heat conduction efficiency is higher.

In some alternative embodiments, the semiconductor package apparatus 1a further includes: and a second electrical connector 15 disposed on the bottom surface of the base substrate 10. The second electrical connector 15 includes, but is not limited to, a solder ball, configured to connect to an external device.

In some alternative embodiments, the semiconductor package apparatus 1a further includes: the passive devices 16, such as resistors or capacitors or inductors, are integrated. The integrated passive devices 16 may be soldered to the bottom surface of the base substrate 10 by bumps, or may be provided on the bottom surface of the base substrate 10 by SMT (surface mount technology).

In some alternative embodiments, the thicknesses (heights) of the layers in the semiconductor package apparatus 1a are as follows:

the conductive layer 20 may have a thickness of 50 μm to 100 μm, for example, about 70 μm;

the thickness of the mold seal material 14 may be 200 μm to 300 μm, for example, about 260 μm;

the underlying substrate 10 may have a thickness of 100 μm to 200 μm, for example, about 140 μm;

the second electrical connection 15 may have a thickness of 100 μm to 200 μm, for example around 160 μm;

the overall thickness of the semiconductor package apparatus 1a may be 500 μm to 1000 μm, for example, about 600 μm.

Referring to fig. 5, fig. 5 is a schematic longitudinal sectional structure of an embodiment 5a of a semiconductor package apparatus according to the present application. The semiconductor packaging apparatus 5a shown in fig. 5 is similar to the semiconductor packaging apparatus 1a shown in fig. 1, except that:

in the semiconductor package apparatus 5a, the bottom surface of the patterned heat conductive layer 22 (i.e., the bottom surface of the heat conductive metal surface 220) may include a plurality of protrusions 221 facing the electronic component 11.

Here, the protrusion 221 may extend into the mold seal 14 closer to the electronic component 11 than the heat conductive metal face 220 of embodiment 1a shown in fig. 1 to improve the efficiency of waste heat conduction from the electronic component 11 to the heat conductive metal face 220.

In some alternative embodiments, the plurality of protrusions 221 may be arranged in a rectangular array.

In some alternative embodiments, the boss 221 may contact the electronic component 11. Thereby, the heat dissipation efficiency can be improved.

In some alternative embodiments, a thermally conductive interface material, such as thermally conductive silicone, may be provided between the boss 221 and the electronic component 11. Thereby, the heat dissipation efficiency can be improved.

Referring to fig. 6, fig. 6 is a schematic longitudinal sectional structure of an embodiment 6a of a semiconductor package apparatus according to the present application. The semiconductor packaging apparatus 6a shown in fig. 6 is similar to the semiconductor packaging apparatus 1a shown in fig. 1, except that:

in the semiconductor package apparatus 6a, the signal wiring layer 21 in the conductive layer 20 is not limited to one layer, and may be, for example, two layers.

It should be understood that the number of signal line layers 21 in the conductive layer 20 may be three or four or more, and the specific number of layers may be determined according to the product requirement.

While the present application has been described and illustrated with reference to particular embodiments thereof, the description and illustration is not intended to be limiting. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the application as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproduction and actual implementation in this application due to variables in the manufacturing process, etc. Other embodiments of the present application not specifically described may exist. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present application. Thus, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present application.

Claims

1. A semiconductor package apparatus, comprising:

an electronic component and a conductive layer over the electronic component; the conductive layer includes:

a signal line layer;

a patterned heat conductive layer configured to conduct heat generated by the electronic component to an outside of the device;

the patterned heat conducting layer is closer to the electronic element than the signal circuit layer.

2. The semiconductor package apparatus according to claim 1, wherein the patterned heat conductive layer is exposed from the lower surface of the conductive layer, and a width of the patterned heat conductive layer is greater than or equal to a width of the electronic component.

3. The semiconductor package apparatus according to claim 2, further comprising:

a bottom substrate, which is positioned below the electronic element to bear the electronic element;

the electric connector is positioned on at least one side of the electronic element and is used for electrically connecting the conductive layer and the bottom substrate;

wherein an edge of the patterned thermally conductive layer is closer to the electrical connection than the electronic component.

4. The semiconductor package apparatus according to claim 1, wherein the patterned heat conductive layer includes a heat conductive metal face directly above the electronic component, covering the electronic component in a top view.

5. The semiconductor package apparatus according to claim 4, wherein the bottom surface of the thermally conductive metal surface comprises a plurality of protrusions.

6. The semiconductor package apparatus according to claim 5, further comprising:

the mold sealing material is positioned below the conductive layer and covers the electronic element;

wherein the convex portion extends into the mold seal material.

7. The semiconductor package apparatus according to claim 6, wherein the convex portion contacts the electronic component.

8. The semiconductor package apparatus of claim 1, wherein the conductive layer further comprises a plurality of thermally conductive vias connecting the patterned thermally conductive layer, the thermally conductive vias passing through the signal trace layer.

9. The semiconductor package apparatus according to claim 8, wherein the conductive layer further comprises: the signal through holes are positioned at the outer sides of the heat conducting through holes, and the distribution density of the heat conducting through holes is larger than that of the signal through holes.

10. The semiconductor package apparatus of claim 9, wherein the thermally conductive via has a smaller diameter than the signal via.