CN220553846U - Battery control device for switching device and switching device - Google Patents

Abstract

Embodiments of the present disclosure provide a battery control device for a switching device and a switching device, the battery control device including: a switching circuit coupled at least between the battery and the load and comprising a control input for receiving a control signal for controlling the switching of the switching circuit, comprising a control input coupled to an external input unit of the switching device; a locking circuit coupled to the control input for outputting a locking signal for locking the on state of the switching circuit or an unlocking signal for locking the off state of the switching circuit to the switching circuit; a first delay circuit for inputting a turn-on control signal for turning on the switching circuit to the control input terminal for a first predetermined period of time; and a second delay circuit for outputting a lock signal to the switching circuit via the lock circuit for a second predetermined period of time. Therefore, when the switch device is started, the switch device can be started without long-time pressing of the starting switch, and therefore user experience is improved.

Description

Battery control device for switching device and switching device

Technical Field

Example embodiments of the present disclosure relate generally to the field of switching devices, and in particular, to a battery control device for a switching device and a switching device.

Background

In a switchgear such as an air switch, the trip mechanism typically uses dual power supplies, one of which is provided by a main circuit through a coil, and the other of which is a backup power supply, typically a lithium battery, in order to ensure that the switchgear can be tripped and restarted after power failure. The system power uses a battery or power supply depending on whether the coil power is normal or not, so there will be a battery-power switching. However, the existing product has no battery starting protection, so that the current is overlarge at the moment of starting the battery, and the service life of the battery is greatly influenced.

Disclosure of Invention

It is an object of the present disclosure to provide a battery control device for a switching device and a switching device to at least partially address the above-mentioned problems and/or other potential problems present in conventional switching devices.

In a first aspect of the present disclosure, a battery control device for a switching device is provided. The battery control device includes: a switching circuit coupled at least between the battery and the load and comprising a control input for receiving a control signal controlling the switching of the switching circuit, the control input being coupled to an external input unit of the switching device; a locking circuit coupled to the control input and including a plurality of inputs for outputting a locking signal for locking an on state of the switching circuit or an unlocking signal for locking an off state of the switching circuit to the switching circuit at least according to a signal from any one of the plurality of inputs; a first delay circuit coupled to the control input terminal and configured to input an on control signal for turning on the switching circuit to the control input terminal for a first predetermined period of time in response to an input of the external input unit; and a second delay circuit coupled to one of the plurality of inputs of the lock circuit and the control input for outputting a lock signal to the switch circuit via the lock circuit for a second predetermined period of time in response to the control input inputting an on control signal for turning on the switch circuit.

In an embodiment according to the present disclosure, when the external input unit inputs the on control signal for turning on the switching circuit, the first delay circuit takes over the input of the on control signal for turning on the switching circuit at the same time, inputs the on control signal for turning on the switching circuit to the control input terminal for a first predetermined period of time, and before the first predetermined time is ended, the second delay circuit outputs the lock signal to the switching circuit via the lock circuit for a second predetermined period of time. Therefore, when the switch device is started, a user can start the switch device by pressing the start switch for a short time without pressing the start switch for a long time, so that user experience is improved. Other benefits will be described below in connection with the corresponding embodiments.

In some embodiments, the battery control device further comprises: and a power supply monitoring circuit coupled to the locking circuit and configured to detect a supply voltage input to the load and to cause the locking circuit to output an unlock signal to the switching circuit if the supply voltage is detected to be less than a predetermined threshold.

In some embodiments, the battery control device further comprises a first or logic unit. The first common terminal of the first or logic unit is coupled to the control input terminal of the switching circuit, the first branch terminal of the first or logic unit is coupled to the first delay circuit, and the second branch terminal of the first or logic unit is coupled to the locking circuit.

In some embodiments, the battery control device further comprises a second or logic unit. The second common terminal of the second or logic unit is coupled to one of the plurality of input terminals of the lock circuit, the third sub-terminal of the second or logic unit is coupled to the second delay circuit, and the fourth sub-terminal of the second or logic unit is coupled to the lock signal output terminal of the microprocessor.

In some embodiments, the locking circuit includes an or gate unit. The output of the or-gate unit is coupled to the second branch of the first or-gate unit, and one of the plurality of inputs of the or-gate unit is coupled to the second common terminal of the second or-gate unit.

In some embodiments, the locking circuit comprises a current limiting resistor coupled between the output of the or gate unit and the first or logic unit and adapted to cause the locking circuit to output an unlocking signal to the switching circuit if the supply voltage is less than a predetermined threshold.

In some embodiments, the battery control device further comprises: an unlock circuit is coupled to any one of the plurality of inputs of the OR gate unit.

In some embodiments, the first delay circuit includes a first transistor. The emitter of the first triode is coupled between the load and the switching circuit, and the collector of the first triode is coupled to the first branch end of the first or logic unit through a first resistor.

In some embodiments, the second delay circuit includes a second transistor. The emitter of the second triode is coupled between the load and the switching circuit, and the collector of the second triode is coupled at a third terminal of the second or logic unit.

In some embodiments, the first delay circuit or the second delay circuit each comprises: the base electrode of the first triode or the second triode is coupled to the pair of parallel capacitors through the second resistor, and the pair of parallel capacitors are grounded; and one end of the third resistor is coupled with the emitter of the first triode or the second triode, and the other end of the third resistor is coupled between the second resistor and a pair of capacitors connected in parallel.

In some embodiments, the first predetermined period of time and the second predetermined period of time are between 0 and 100ms.

In some embodiments, the current limiting resistor has a resistance of 0 to 1KΩ.

In a second aspect of the present disclosure, a switching device is provided. The switching device includes: the tripping mechanism is used for controlling the on-off of a main loop in which the switching device is positioned; a main power supply and a standby power supply coupled to the trip mechanism; and the battery control device according to the first aspect is used for switching on a standby power supply to supply power for the tripping mechanism.

It should be understood that what is described in this section of the disclosure is not intended to limit key features or essential features of the embodiments of the disclosure, nor is it intended to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

fig. 1 illustrates an architectural schematic diagram of a battery control device according to some embodiments of the present disclosure;

fig. 2 illustrates a circuit schematic of a battery control device according to some embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been illustrated in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather, these embodiments are provided so that this disclosure will be more thorough and complete. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions are also possible below. The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As mentioned briefly above, a switching device such as an air switch is an important protection device in an electric power system for monitoring and controlling an abnormal situation such as overload, short circuit, and ground fault in a power supply line. When two independent main/backup power sources are used, conventional switching devices, some loads such as microprocessors or indicator lights in the switching devices need to quickly draw energy from the backup power source (e.g., a battery) to maintain operation when the main power source fails (e.g., trips or fails). However, in some cases, when a trip or power outage occurs, the system voltage (e.g., the voltage of the main and standby power supplies) may drop to a minimum operating voltage that is not required to maintain proper operation of the microprocessor (e.g., a single-chip microcomputer) or other controller. Because the system is not enough in power supply, the microprocessor or other controllers cannot continue to operate, in this case, because the locking circuit (also can be called as a latch circuit or a latch logic) in the traditional switching device has no power-on and power-off reset function, the locking circuit may be continuously opened and cannot be closed, and a high-level signal is continuously output to the switching element of the standby power supply, so that the standby power supply can be always opened and cannot be closed, and the output signal of the locking circuit is unreliable, so that the risk of damage of the standby power supply is caused.

After the system is powered off, for example, in order to check a fault state, a user needs to press a switch button for a long time to control a standby power supply to supply power to a microprocessor or other controllers, so that after the microprocessor or other controllers reach the minimum working voltage, after the microprocessor or other controllers are awakened, a locking circuit is controlled to output a high-level signal, so that a switching element of the standby power supply is turned on, and the standby power supply continuously supplies power. When the switching device is switched from the standby power supply to the power supply, the standby power supply is ended. In practical application, as the parts including the charge-discharge loop, the control logic and other related elements are simultaneously switched from the stop state to the working state when the starting is started, the transient current is overlarge, the high peak current generated in the transient process can cause adverse effects on the switching device, and the standby power supply is aged rapidly.

To solve or at least partially solve the above-described problems or other potential problems with conventional switching devices, embodiments of the present disclosure provide a battery control device solution for switching devices, such as air switches. In the battery control device, the switch circuit is turned on by pressing the external input unit for a short time, and the first delay circuit takes over the input action of the external input unit, so that the switch circuit is continuously turned on for a first preset time period, and before the first preset time period is ended, the second delay circuit outputs a locking signal to the switch circuit through the locking circuit for a second preset time period so as to lock the on state of the switch circuit. Therefore, when the switch device is started, a user can start the switch device by pressing the start switch for a short time without pressing the start switch for a long time, so that user experience is improved.

An example architecture and operation of the battery control device 100 of the switching device will be described below in conjunction with fig. 1-2. The switching device according to an embodiment of the present disclosure may include a trip mechanism, a load such as a microprocessor 110 and/or an indicator, a main power supply, a standby power supply, and a battery control device 100. The trip mechanism is used to control the switching device to trip (again referred to as trip) when the connected main circuit fails. A load such as microprocessor 110 and/or an indicator is used to store and/or indicate the status of the switching device. The main power supply is typically coupled to the main loop through a coil to power the trip mechanism and a load or the like, such as the microprocessor 110 and/or an indicator. The backup power source is typically a backup battery 120 coupled to the trip mechanism. The battery control device 100 is used to switch on a backup power source to power a load. For example, after the switching device is tripped, a load such as the microprocessor 110 and/or an indicator, etc., is powered by the backup power source. Also, when the switching device is activated, a load such as the microprocessor 110 and/or an indicator is powered by the backup power source, the primary power source is switched off and the backup power source is turned off after the microprocessor 110 or other controller is awakened.

As shown in fig. 1, a battery control device 100 according to an embodiment of the present disclosure generally includes a switch circuit 121, a lock circuit 126, and two delay circuits. For convenience of description, the two delay circuits will be hereinafter referred to as a first delay circuit 122 and a second delay circuit 124, respectively. In some embodiments, the battery control device 100 further includes a power monitoring circuit 111, a first or logic unit 123, a second or logic unit 125, and an unlocking circuit 129. For example, a switching circuit 121 is coupled between the battery 120 and the microprocessor 110. The first delay circuit 122 is coupled to the switching circuit 121. The second delay circuit 124 is coupled to the switching circuit 121 at one end and to the lock circuit 126 through the second or logic unit 125 at the other end. The lock circuit 126 is coupled to the switch circuit 121 through the first or logic unit 123. The lock signal output of the microprocessor 110 (e.g., the Vin1 terminal in fig. 2) is coupled to the lock circuit 126 through a second or logic unit 125. The power supply monitoring circuit 111 is coupled between the lock circuit 126 and the first or logic unit 123. The unlock circuit 129 is coupled to the lock circuit 126.

In the embodiment of the present disclosure, when the switch circuit 121 is turned on (may also be referred to as turned on) after receiving the on signal from the short-press of the external input unit 130, the on signal is continuously transmitted to the switch circuit 121 by the first delay circuit 122 instead of the short-press action of the external input unit 130, and before the first delay circuit 122 is turned off, the lock signal for causing the switch circuit 121 to be in the on state is transmitted to the lock circuit 126 by the second delay circuit 124. Although the user simply presses the external input unit 130 for a short time, the standby power supply can be enabled to continuously supply power to the load, and the power failure phenomenon does not occur during the starting process of the load, and the specific implementation will be described below. When the main power supply fails (e.g., trips or fails), the system voltage (V1 terminal shown in fig. 1) decreases to a minimum operating voltage (e.g., less than 1.6V) required for the microprocessor 110 (e.g., a single-chip microcomputer) or other controller to operate normally, the power supply monitoring circuit 111 monitors that the microprocessor 110 or other controller cannot continue to operate due to insufficient power supply of the system, and in this case, current is limited by the current limiting resistor 127 (which will be described in detail later), and a high level signal of the locking circuit is pulled down and then output, while the power supply monitoring circuit 111 outputs a low level signal to turn off the locking circuit 126, i.e., outputs an unlock signal for locking the off state of the switching circuit 121, thereby turning off the standby power supply, and damage to the standby power supply can be effectively prevented. In some embodiments, switching circuit 121 is coupled to soft start circuit 131. The standby power supply (V3 terminal shown in fig. 1) is coupled to the soft start circuit 131 via the soft start cancellation circuit 132. Soft start circuit 131 is coupled to microprocessor 110 via power switching circuit 150. The main power supply (V2 terminal shown in fig. 1) is coupled to the power supply switching circuit 150 via the main power supply detection circuit 140.

A specific circuit structure of the battery control device 100 will be described below with reference to fig. 1 and 2. As shown in fig. 1 and 2, in an embodiment of the present disclosure, the switching circuit 121 includes a control input. For example, the control input terminal is used for receiving a control signal for controlling the on-off of the switch circuit 121. The control input may have one or more. In some embodiments, the control input is coupled to an external input unit 130 of the switching device. In response to an input of the external input unit 130, the external input unit 130 inputs a turn-on control signal to turn on the switching circuit 121 to the control input terminal. For example, the external input unit 130 may be a switch button, to which embodiments of the present disclosure are not particularly limited. For example, referring to fig. 2, a standby power supply (V3 terminal shown in fig. 2) is coupled to the emitter of a switching transistor 1211, the collector of the switching transistor 1211 is connected to a virtual ground (e.g., GND terminal) of the circuit board via a capacitor 1212, and the base is connected to the emitter via a resistor 1213 and a resistor 1214. The switching transistor may be a PNP transistor. The switching circuit 121 may also include an NPN transistor 1215. The NPN transistor 1215 has a collector coupled between the resistor 1213 and the resistor 1214, an emitter connected to a virtual ground (e.g., GND terminal) of the circuit board, and a base coupled to a first common (i.e., output) of the first or logic unit 123 via the resistor 1216. A resistor 1217 is coupled between the base and emitter of NPN transistor 1215.

In the embodiments of the present disclosure, as mentioned previously, the lock-in circuit 126 includes the or gate unit 1261 and the current limiting resistor 127. The or gate unit 1261 has a plurality of inputs. According to a signal from any one of the plurality of input terminals, a lock signal is output to the switch circuit 121 to lock the switch circuit 121 in an on state. It will be appreciated that in order to lock the switch circuit 121 in the on state, the lock circuit 126 outputs a high signal to the switch circuit 121. In some embodiments, the locking circuit 126 outputs an unlock signal to the switch circuit 121 to lock the switch circuit 121 in an off state according to a signal from any one of the plurality of input terminals. It is understood that, in order to lock the off state of the switch circuit 121, the lock circuit 126 outputs a low level signal to the switch circuit 121. In some embodiments, as mentioned above, the current limiting resistor 127 is configured to enable the lock-in circuit 126 to output the unlock signal (e.g., a low level signal) to the switch circuit 121 in response to the supply voltage being less than a predetermined threshold. For example, referring to fig. 2, any of a plurality of inputs of the or gate unit 1261 are coupled to the unlock circuit 129, a specific implementation of which will be described below. At the same time, any of the plurality of inputs is coupled to a second common of the second or logic cell 125 via a resistor 1262. The second common terminal of the second or logic cell 125 is also connected to a virtual ground (e.g., GND terminal) of the circuit board via a resistor 1263. The output of OR gate unit 1261 is coupled to a second terminal of first OR logic unit 123 via current limiting resistor 127. The power supply monitoring circuit 111 is coupled between the current limiting resistor 127 and a second terminal of the first or logic unit 123, and between the current limiting resistor 127 and the second terminal is coupled to a system power supply (e.g., a main power supply and a standby power supply) via a resistor 1114 for monitoring a real-time supply voltage of the load. In some embodiments, the current limiting resistor 127 may have a resistance of 0 to 1KΩ. For example, 200Ω, 500Ω, or 800Ω may be employed, which is not particularly limited by the embodiments of the present disclosure.

In the embodiment of the present disclosure, as mentioned above, when the external input unit 130 stops outputting the signal (i.e., after stopping the short press), the first delay circuit 122 outputs the on control signal to the control input terminal of the switching circuit 121 in order to make the switching circuit 121 continue to be turned on. In some embodiments, the first delay circuit 122 includes a first transistor 1221, a first resistor 1226, a second resistor 1222, a third resistor 1225, and a pair of capacitors 1223 and 1224 in parallel. For example, the emitter of the first transistor 1221 is coupled to the collector of the switching transistor 1211 of the switching circuit 121, and the collector of the first transistor 1221 is coupled to the first terminal of the first or logic unit 123 via a first resistor 1226. The base of the first transistor 1221 is coupled to a pair of parallel capacitors 1223 and 1224 via a second resistor 1222, and the pair of parallel capacitors 1223 and 1224 is connected to a virtual ground (e.g., GND terminal) of the circuit board. A third resistor 1225 is coupled at one end to the emitter of the first transistor 1221 and at the other end between the second resistor 1222 and the parallel capacitors 1223 and 1224.

In the embodiment of the present disclosure, as mentioned before, before the first delay circuit 122 stops outputting the signal, in order to keep the switching circuit 121 on, the second delay circuit 124 outputs a lock signal for locking the on state of the switching circuit 121 to the switching circuit 121 via the lock circuit 126, and keeps the switching circuit 121 on continuously. In some embodiments, the second delay circuit 124 includes a second transistor 1241, a second resistor 1222, a third resistor 1225, and a pair of capacitors 1223 and 1224 in parallel. For example, an emitter of the second transistor 1241 is coupled to a collector of the switching transistor 1211 of the switching circuit 121, and a collector of the second transistor 1241 is coupled to one terminal (hereinafter, referred to as a third terminal for convenience of description) of the second or logic unit 125. The base of the second transistor 1241 is coupled to a pair of parallel capacitors 1223 and 1224 via a second resistor 1222, and the parallel capacitors 1223 and 1224 are connected to a virtual ground (e.g., GND terminal) of the circuit board. A third resistor 1225 has one end coupled to the emitter of the second transistor 1241 and the other end coupled between the second resistor 1222 and the parallel capacitors 1223 and 1224. In some embodiments, the first predetermined period of time and the second predetermined period of time may be 0 to 100ms. For example, 50ms or 80ms may be employed, which is not particularly limited by the embodiments of the present disclosure. When the microprocessor 110 or other controller is fully awake, the first delay circuit 122 and the second delay circuit 124 in the disclosed embodiments are automatically turned off. The power consumption of the first delay circuit 122 and the second delay circuit 124 after the load operation is stabilized is approximately equal to 0. In some embodiments, the values of the resistors and the capacitors in the first delay circuit 122 and the second delay circuit 124 may be adjusted according to the required delay time, and the values of the resistors and the capacitors in the first delay circuit 122 and the second delay circuit 124 may be the same or different, which is not particularly limited by the embodiments of the present disclosure.

In the embodiment of the present disclosure, when the system voltage as described above is reduced to the minimum operation voltage required for failing to maintain the normal operation of the microprocessor 110, the power supply monitoring circuit 111 may be used to detect the system voltage (V1 terminal shown in fig. 2), that is, to detect the supply voltage of the system power supply (e.g., the main power supply or the standby power supply) output to the microprocessor 110, and when detecting that the supply voltage is less than the predetermined threshold, cause the lock circuit 126 to output an unlock signal for locking the off state of the switch circuit 121 to the switch circuit 121. In other words, when the power supply monitoring circuit 111 detects that the supply voltage is less than the predetermined threshold, the or gate unit 1261 is limited by the current limiting resistor 127 and outputs a high level signal after being pulled down, and at the same time, the power supply monitoring circuit 111 outputs a low level signal to the switch circuit 121, so that the switch circuit 121 is turned off, and the switch circuit 121 is turned off. For example, the power supply monitoring circuit 111 may perform voltage monitoring and signal processing using a monitoring chip coupled between the resistor 1111 and the resistor 1112 and connected in parallel with a capacitor 1113. The monitor chip is coupled between the current limiting resistor 127 and the second terminal. The power supply monitoring circuit 111 according to the embodiment of the present disclosure does not require the use of a comparator, and adopts a simple circuit structure, thereby simplifying the circuit layout of the entire system.

In some embodiments, the first or logic unit 123 and the second or logic unit 125 are circuits that form an or relationship by a plurality of diodes, for turning on other circuits or logic units, which is not particularly limited by the embodiments of the present disclosure. For example, the first or logic unit 123 and the second or logic unit 125 may employ 2 diodes, the cathodes of the 2 diodes are all connected to a common node (i.e., common terminal), and their anodes are respectively connected to the input signal. The first or logic unit 123 and the second or logic unit 125 may also be connected in such a way as to form an or-relation circuit using 3 or more diodes.

In some embodiments, OR gate unit 1261 may include OR gate elements for performing OR operations in a logical operation. The or gate unit 1261 may receive two or more input signals and output a high level when any one of the inputs is a high level. The output is low only when all input signals are low.

As described above, in embodiments of the present disclosure, the high signal output by the lock circuit 126 may cause the switch circuit 121 to remain on when the microprocessor 110 (single chip or MCU) or other controller is fully awake. At this time, the lock circuit 126 may be unlocked from the high level signal to the low level signal by the unlock signal output (Vin 2 terminal shown in fig. 2) of the microprocessor 110 to the unlock circuit 129. At the same time, the microprocessor 110 cuts off the switch circuit 121, that is, cuts off the power supply of the standby power supply, and after the switch circuit 121 is powered down, even if the working state of the locking circuit 126 is unstable, the switch circuit 121 is not controlled to be opened. For example, in embodiments of the present disclosure, the lock circuit 126 will automatically reset when a preset switch threshold is reached after the switch circuit 121 is powered down. The switching threshold may be 0.5V, which is not particularly limited by the embodiments of the present disclosure. For example, in some embodiments, the unlock circuit 129 may employ a collector of a transistor 1291 coupled to any of a plurality of inputs of the or gate unit 1261, an emitter of the transistor 1291 being connected to a virtual ground (e.g., GND) of the circuit board. The base of transistor 1291 is coupled to the unlock signal output of microprocessor 110 via resistor 1294. A capacitor 1292 and a resistor 1293 coupled in parallel between the resistor 1294 and the base of the transistor 1291 are connected to a virtual ground (e.g., GND terminal) of the circuit board. A resistor 1295 may be coupled between the collector of transistor 1291 and the output of or gate unit 1261. When the standby power supply is automatically switched to the main power supply, the power supply monitoring circuit 111 detects that the power supply voltage (the power supply voltage of the main power supply) is higher than the predetermined threshold, and even if the lock circuit 126 is in the unlock state of the high level signal, that is, the switch circuit is in the on state, the standby power supply is powered by the main power supply, and the standby power supply does not need to be powered, so that the electric quantity of the standby power supply can be saved.

In order to more clearly understand the operation of the battery control device 100 according to the embodiment of the present disclosure, an example of the battery control device 100 is described below with reference to fig. 1 and 2. The battery control device 100 according to the embodiment of the present disclosure analyzes the operation process of the battery by the trip process and the switching device start-up process. The switching device includes a main power supply circuit and a standby power supply circuit (hereinafter referred to as a main circuit and a standby circuit), which are switchable to each other. When operating normally, the main loop is connected to the load and is powered by the main power supply. When the trip mechanism trips, in some cases (for example, the voltage of the standby power supply is too low), when the system voltage is reduced to the minimum operating voltage required by the microprocessor 110 cannot be maintained, the power supply monitoring circuit 111 of the battery control device 100 monitors the situation and rapidly outputs a low-level signal to the switch circuit 121, and the current limiting resistor 127 limits the current of the locking circuit and pulls down the high-level signal to be output, so that the switch circuit 121 is in an off state, and unstable conditions caused by the too low standby power supply voltage to the load are prevented. When the user looks at the cause of the fault by pressing an external input unit (e.g., a button) for a short time, the timing coordination of the first delay circuit 122 and the second delay circuit 124 enables the standby power supply to continue to power a load such as a microprocessor and/or an indicator light until the microprocessor is fully started. During this process, the battery control device 100 can ensure stable energy transmission of the backup circuit.

Specifically, referring to fig. 2, when the user presses an external input unit (e.g., a button) for a short time, the external input unit 130 outputs an on control signal to the switching transistor 1211 in the switching circuit 121, so that the switching circuit 121 is opened, a standby loop (i.e., a loop between a standby power source or a battery and a load) is started, and power is supplied to the microprocessor 110 or other controller. While the first transistor 1221 in the first delay circuit 122 is also turned on. Next, the on control signal output from the external input unit 130 is turned off (short press is ended), and at the same time, the first delay circuit 122 outputs the on control signal to the switching transistor 1211 in the switching circuit 121, so that the switching circuit 121 is continuously turned on. Before the first delay circuit 122 finishes outputting the on control signal, the second transistor 1241 of the second delay circuit 124 is turned on, and a lock signal for locking the on state of the switch circuit 121 is output to the switch circuit 121 through the lock circuit 126, so that the switch circuit 121 is kept on (before the control signal of the microprocessor is interposed).

Referring to fig. 2, when the trip mechanism is tripped and is powered by the backup power source or the battery, if the backup power source or the battery voltage is too low, the power source monitoring circuit 111 outputs an off signal to the switching circuit 121 when detecting that the system voltage is lower than the minimum operation voltage required for the normal operation of the microprocessor 110, and the locking circuit 126 limits the current via the current limiting resistor 127 and pulls the output high level signal low, an unlock signal locking the switching circuit 121 in the off state may be output to the switching circuit 121. Thus, after the tripping mechanism trips, when the system voltage is lower than the minimum working voltage required by the normal operation of the microprocessor 110, the switching circuit 121 can be rapidly turned off, so that the reliability of the circuit can be ensured and the battery power can be saved.

The foregoing description of implementations of the present disclosure has been provided for illustrative purposes, is not exhaustive, and is not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various implementations described. The terminology used herein was chosen in order to best explain the principles of each implementation, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand each implementation disclosed herein.

Claims (11)

1. A battery control device for a switching device, comprising:

a switching circuit (121) coupled at least between the battery (120) and the load and comprising a control input for receiving a control signal controlling the switching of the switching circuit (121), the control input being coupled to an external input unit (130) of the switching device;

a locking circuit (126) coupled to the control input and comprising a plurality of inputs for outputting to the switching circuit (121) a locking signal for locking an on state of the switching circuit (121) or an unlocking signal for locking an off state of the switching circuit (121) at least in dependence of a signal from any one of the plurality of inputs;

a first delay circuit (122) coupled to the control input and configured to input a turn-on control signal for turning on the switching circuit (121) to the control input for a first predetermined period of time in response to an input of the external input unit (130); and

a second delay circuit (124) coupled to one of the plurality of inputs of the lock circuit (126) and the control input for outputting the lock signal to the switch circuit (121) via the lock circuit (126) for a second predetermined period of time in response to the control input inputting a turn-on control signal for turning on the switch circuit (121).

2. The battery control device according to claim 1, characterized by further comprising:

a power supply monitoring circuit (111) is coupled to the locking circuit (126) and is configured to detect a supply voltage input to the load and to cause the locking circuit (126) to output the unlocking signal to the switching circuit (121) if the supply voltage is detected to be less than a predetermined threshold.

3. The battery control device according to claim 2, characterized by further comprising:

-a first or logic unit (123), a first common terminal of the first or logic unit (123) being coupled to the control input of the switching circuit (121), a first branch terminal of the first or logic unit (123) being coupled to the first delay circuit (122), and a second branch terminal of the first or logic unit (123) being coupled to the locking circuit (126).

4. The battery control device according to claim 3, characterized by further comprising:

-a second or logic unit (125), a second common terminal of the second or logic unit (125) being coupled to one of the plurality of inputs of the locking circuit (126), a third terminal of the second or logic unit (125) being coupled to the second delay circuit (124), and a fourth terminal of the second or logic unit (125) being coupled to a locking signal output of the microprocessor (110).

5. The battery control device according to claim 4, wherein the lock circuit (126) includes:

-an or-gate unit (1261), the output of the or-gate unit (1261) being coupled to the second terminal of the first or-gate unit (123), one of the plurality of inputs of the or-gate unit (1261) being coupled to the second common terminal of the second or-gate unit (125).

6. The battery control device according to claim 5, wherein the locking circuit (126) comprises a current limiting resistor (127) coupled between the output of the or gate unit (1261) and the first or logic unit (123) and adapted to cause the locking circuit (126) to output the unlocking signal to the switching circuit (121) if the supply voltage is less than a predetermined threshold.

7. The battery control device according to claim 5, characterized by further comprising:

-an unlocking circuit (129) coupled to any one of a plurality of inputs of the or gate unit (1261).

8. The battery control device according to claim 5, wherein the first delay circuit (122) includes:

-a first transistor (1221), an emitter of the first transistor (1221) being coupled between the load and the switching circuit (121), a collector of the first transistor (1221) being coupled at the first terminal of the first or logic unit (123) via a first resistor (1226).

9. The battery control device according to claim 8, wherein the second delay circuit (124) includes:

-a second transistor (1241), an emitter of the second transistor (1241) being coupled between the load and the switching circuit (121), a collector of the second transistor (1241) being coupled at a third split of the second or logic unit (125).

10. The battery control device according to claim 9, wherein the first delay circuit (122) or the second delay circuit (124) each includes:

a second resistor (1222) and a pair of parallel capacitors, the base of the first transistor (1221) or the second transistor (1241) being coupled to the pair of parallel capacitors via the second resistor (1222), and the pair of parallel capacitors being grounded;

-a third resistor (1225), one end of the third resistor (1225) being coupled to the emitter of the first transistor (1221) or the second transistor (1241), the other end being coupled between the second resistor (1222) and the pair of parallel capacitors.

11. A switching device, comprising:

the tripping mechanism is used for controlling the on-off of a main loop where the switching device is positioned;

a main power supply and a backup power supply coupled to the trip mechanism; and

the battery control device of any one of claims 1-10, configured to turn on the backup power source to power the trip mechanism.