CN220526561U - Display driving circuit and display device - Google Patents
Display driving circuit and display device Download PDFInfo
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- CN220526561U CN220526561U CN202223469664.1U CN202223469664U CN220526561U CN 220526561 U CN220526561 U CN 220526561U CN 202223469664 U CN202223469664 U CN 202223469664U CN 220526561 U CN220526561 U CN 220526561U
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Abstract
The application discloses display drive circuit includes: an abnormality detection circuit for generating a reset control signal according to the abnormality detection signal; a microprocessor for transmitting a low voltage differential signal and a reset data signal, and changing an external reset signal to an active state when the reset control signal is in an active state; the time schedule controller is used for receiving a reset data signal and generating a plurality of starting signals, synchronous signals and data signals according to the low-voltage differential signal; the source driver is used for providing a first gray-scale voltage for the display panel according to the data signal so as to drive the display panel to display normally; the time schedule controller also controls whether to send the data signal to the source driver according to the reset signal; when the reset signal is in an active state, a reset data signal is provided to the source driver. According to the display device provided by the embodiment of the utility model, when the occurrence of the abnormality is detected, the reset signal is changed into the active state, so that the display panel displays a black screen picture, and the system reset is realized.
Description
Technical Field
The present utility model relates to the field of display technologies, and in particular, to a display driving circuit and a display device.
Background
Based on safety, the vehicle-mounted display driving chips have an abnormality detection function, and the types of errors detected include voltage abnormality, input display signal abnormality (LVDS signal), source (Source) driving signal, gate driving signal (Gate) abnormality, and the like. The abnormality information is typically outputted to the instruction information notifying system through one Pin. If the error occurs, the system reads the register in the chip and judges the specific error type.
However, the indication information output by the driving chip can only indicate whether an abnormality occurs, and the specific abnormality type also needs to read the internal register of the driving chip; the display driving chip receives the abnormal signal to cause abnormal display.
Accordingly, there is a need to provide an improved solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In view of the above, an object of the present utility model is to provide a display driving circuit and a display device capable of actively resetting an external reset signal when an abnormal signal is detected, thereby improving a display effect.
According to an aspect of the present utility model, there is provided a display driving circuit including: the abnormality detection circuit is connected with the output end of the display driving circuit and comprises a comparator, a first resistor and a second resistor; the first resistor and the second resistor are connected in series between the power supply voltage and the ground terminal, and a node between the first resistor and the second resistor outputs a reference voltage; the non-inverting input end of the comparator receives the abnormality detection signal, the inverting input end receives the reference voltage, and the output end outputs the reset control signal;
the microprocessor is used for transmitting a low-voltage differential signal and a reset data signal, is connected with the abnormality detection circuit and changes an external reset signal in an invalid state into a reset signal in an valid state based on the reset control signal in the valid state;
the time sequence controller is connected with the microprocessor and receives a reset data signal and generates a plurality of clock signals, a starting signal, a synchronous signal and a data signal according to a low-voltage differential signal;
the source electrode driver is connected with the time sequence controller and the display panel, and provides a first gray scale voltage for the display panel according to a data signal generated by the time sequence controller so as to drive the display panel to display normally; when the time schedule controller receives a reset signal in an effective state, the time schedule controller stops providing a data signal to the source driver, and simultaneously provides a reset data signal to the source driver, and the source driver also provides a second gray-scale voltage to the display panel according to the reset data signal so as to drive the display panel to display a black picture.
Preferably, the display driving circuit further includes a gate driver connected to the display panel to supply a gate voltage to the display panel.
Preferably, the source driver includes a plurality of source driving circuits, the synchronization signal generated by the timing controller includes at least a field synchronization signal, and the timing controller receives the field synchronization signal to supply a reset data signal to the plurality of source driving circuits.
According to another aspect of the present utility model, there is provided a display device, including a main controller, the display driving circuit and a display panel, where the main controller is connected to a microprocessor of the display driving circuit through a low voltage differential signal interface, and the display driving circuit is disposed in a non-display area of the display panel.
According to the display driving circuit and the display device, when abnormality is detected, the reset signal is changed into the active state, so that the display panel displays a black screen picture, and system reset is realized.
Drawings
The above and other objects, features and advantages of the present utility model will become more apparent from the following description of embodiments of the present utility model with reference to the accompanying drawings.
Fig. 1 shows a schematic block diagram of a display device of an embodiment of the utility model.
Fig. 2 shows a schematic block diagram of an anomaly detection circuit of an embodiment of the present utility model.
Fig. 3 shows a timing diagram of various control signals in an embodiment of the utility model.
Detailed Description
The utility model will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Numerous specific details of the utility model, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the utility model. However, as will be understood by those skilled in the art, the present utility model may be practiced without these specific details.
Fig. 1 shows a schematic block diagram of a display device according to an embodiment of the present utility model, which includes a main controller 100, a display driving circuit 200, and a display panel 300, as shown in fig. 1. The main controller 100 is connected to the microprocessor of the display driving circuit 200 through a Low Voltage Differential Signaling (LVDS) interface, and the display driving circuit 200 is disposed in a non-display area of the display panel 300.
The display driving circuit 200 includes a microprocessor 210, an abnormality detection circuit 220, a timing controller 230, a gate driver 240, and a source driver 250.
The abnormality detection circuit 220 is connected to an output terminal of the display driving circuit 200, and is configured to obtain an abnormality detection signal and generate a reset control signal according to the abnormality detection signal.
In this embodiment, the display driving circuit 200 has an abnormality detection function for self-checking a signal output from the display driving circuit 200 to the display panel 300, and if a module self-checking discovery signal of the display driving circuit 200 is wrong, the abnormality detection signal DET is sent to the abnormality detection circuit 220, and the abnormality detection signal DET is at a high level.
Fig. 2 shows a schematic block diagram of an abnormality detection circuit of an embodiment of the present utility model, referring to fig. 2, the abnormality detection circuit 220 includes a comparator, a first resistor R1, and a second resistor R2. The first resistor R1 and the second resistor R2 are connected in series between the power supply voltage VDD and the ground terminal, and a node between the first resistor R1 and the second resistor R2 outputs a reference voltage Vref; the comparator has a non-inverting input terminal receiving the abnormality detection signal DET, an inverting input terminal receiving the reference voltage Vref, and an output terminal outputting a reset control signal. When the abnormality detection signal is smaller than a reference voltage, the reset control signal is in an invalid state; when the abnormality detection signal is greater than a reference voltage, the reset control signal is in an active state.
The microprocessor 210 is connected to the abnormality detection circuit 220 for transmitting a low voltage differential signal and a reset data signal, and changing an external reset signal from an inactive state to an active state when the reset control signal is in an active state.
In the present embodiment, the microprocessor 210 receives a low voltage differential signal (LVDS signal) including a data signal and a control signal (STV/Hsync/Vsync). The control signals include a start signal STV, a line synchronization signal Vsync, and a field synchronization signal Hsync.
When the RESET control signal is in an invalid state, the RESET signal RESET maintains the invalid state; when the RESET control signal is in an active state, the microprocessor 210 changes an external RESET signal RESET from an inactive state to an active state. When the RESET signal RESET is in a high level, the RESET signal RESET is in an invalid state; when the RESET signal RESET is in a low level, the RESET signal RESET is in an active state.
The timing controller 220 is connected to the microprocessor 210 for receiving the reset data signal RESDA and generating a plurality of clock signals SCL, start signals STV, synchronization signals and data signals SDA according to the low voltage differential signal.
In this embodiment, the start signal STV may be a start signal of one frame.
The timing controller 220 also controls whether the data signal SDA is supplied to the source driver 250 according to the RESET signal RESET.
In the present embodiment, when the RESET signal RESET is in an active state, the timing controller 220 stops the supply of the data signal SDA to the source driver while the RESET data signal RESDA is supplied to the source driver.
The microprocessor 210 also restores an external reset signal to an inactive state according to the enable signal.
In each frame period, when the RESET signal RESET changes from the inactive state to the active state, the RESET signal RESET maintains the active state until the end of the current frame period, and when the next frame period starts, the RESET signal RESET returns to the inactive state, and the timing controller 220 continues to supply the data signal SDA to the source driver 250.
The source driver 250 is connected to the display panel 300, and is configured to provide a first gray voltage to the display panel 300 according to the data signal SDA to drive the display panel 300 to display normally.
The source driver 250 is further configured to provide a second gray voltage to the display panel 300 according to the reset data signal RESDA to drive the display panel 300 to display a black image.
In this embodiment, the source driver 250 includes a plurality of source driving circuits, the synchronization signal includes at least a field synchronization signal Hsync, and the timing controller 220 supplies the reset data signal RESDA to the plurality of source driving circuits according to the field synchronization signal Hsync. The plurality of source driving circuits simultaneously display a black picture according to the field synchronizing signal Hsync and the reset data signal RESDA.
The gate driver 240 is connected to the display panel 300 for supplying a gate voltage to the display panel 300.
Referring to fig. 3, after power-up, the supply voltage VDD is changed from an inactive level to an active level to generate the reference voltage Vref; when the abnormality detection signal DET is at an inactive level (e.g., low level), the RESET control signal is at an inactive state, and thus the RESET signal RESET remains at an inactive state (e.g., high level), at which time the timing controller 230 may transmit the data signal SDA to the source driver 250; when the abnormality detection signal DET is at an active level (e.g., a high level) and the amplitude is greater than the reference voltage, the RESET control signal is at an active state, and the microprocessor 210 changes the RESET signal RESET from an inactive state to an active state (e.g., a low level), the timing controller 230 stops transmitting the data signal SDA to the source driver 250 and continues transmitting the RESET data signal RESDA to the source driver 250 for resetting; when a next frame period arrives, that is, the start signal STV changes from the inactive level to the active level, the RESET signal RESET returns to the inactive state.
According to the display driving circuit and the display device, when abnormality is detected, the reset signal is changed into the active state, so that the display panel displays a black screen picture, and system reset is realized.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present utility model, as described above, are not intended to be exhaustive or to limit the utility model to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model and various modifications as are suited to the particular use contemplated.
Claims (4)
1. A display driving circuit, comprising:
the abnormality detection circuit is connected with the output end of the display driving circuit and comprises a comparator, a first resistor and a second resistor; the first resistor and the second resistor are connected in series between the power supply voltage and the ground terminal, and a node between the first resistor and the second resistor outputs a reference voltage; the non-inverting input end of the comparator receives the abnormality detection signal, the inverting input end receives the reference voltage, and the output end outputs the reset control signal;
the microprocessor is used for transmitting a low-voltage differential signal and a reset data signal, is connected with the abnormality detection circuit and changes an external reset signal in an invalid state into a reset signal in an valid state based on the reset control signal in the valid state;
the time sequence controller is connected with the microprocessor and receives a reset data signal and generates a plurality of clock signals, a starting signal, a synchronous signal and a data signal according to a low-voltage differential signal;
the source electrode driver is connected with the time sequence controller and the display panel, and provides a first gray scale voltage for the display panel according to a data signal generated by the time sequence controller so as to drive the display panel to display normally; when the time schedule controller receives a reset signal in an effective state, the time schedule controller stops providing a data signal to the source driver, and simultaneously provides a reset data signal to the source driver, and the source driver also provides a second gray-scale voltage to the display panel according to the reset data signal so as to drive the display panel to display a black picture.
2. The display driver circuit of claim 1, further comprising a gate driver coupled to the display panel to provide a gate voltage to the display panel.
3. The display driver circuit of claim 1, wherein the source driver includes a plurality of source driver circuits, the synchronization signal includes at least a field synchronization signal, and the timing controller receives the field synchronization signal to provide a reset data signal to the plurality of source driver circuits.
4. A display device comprising a main controller, a display driving circuit according to any one of claims 1 to 3, and a display panel, wherein the main controller is connected to a microprocessor of the display driving circuit through a low voltage differential signal interface, and the display driving circuit is disposed in a non-display area of the display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223469664.1U CN220526561U (en) | 2022-12-22 | 2022-12-22 | Display driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223469664.1U CN220526561U (en) | 2022-12-22 | 2022-12-22 | Display driving circuit and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220526561U true CN220526561U (en) | 2024-02-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202223469664.1U Active CN220526561U (en) | 2022-12-22 | 2022-12-22 | Display driving circuit and display device |
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| Country | Link |
|---|---|
| CN (1) | CN220526561U (en) |
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- 2022-12-22 CN CN202223469664.1U patent/CN220526561U/en active Active
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