CN220509081U - Arc fault detection circuit - Google Patents

Abstract

The present disclosure proposes an arc fault detection circuit comprising: the signal acquisition circuit is used for acquiring current on the power supply line and outputting a first signal; a window gating circuit for outputting a window gating signal corresponding to the first signal; and the signal processing circuit is electrically connected with the signal acquisition circuit and the window gating circuit and is used for generating an arc fault signal based on the window gating signal and the first signal. According to the arc fault detection circuit, the window gating circuit is added into the arc fault detection circuit, and whether the fault arc characteristics exist or not is judged only in a period when the harmful arc is certain to appear, so that the accuracy of judging the harmful arc is greatly improved, and the probability of misoperation of the arc fault protection device is reduced.

Description

Arc fault detection circuit

Technical Field

The present disclosure relates to the field of electrical safety protection, and more particularly, to a more accurate arc fault detection circuit.

Background

The electric circuit and equipment in the house have the problems that the insulation layer of the electric wire is aged, the insulation effect is reduced, or the insulation layer is damaged due to long-time overload operation or poor electric connection and the like, and fault arc can occur. The arc spark may ignite the line causing a fire to occur.

With the increasing awareness of people about safety, more households choose to install arc fault protection devices in houses. However, most arc fault protection devices produced in the current market have the problem that harmful arcs are inaccurately judged, so that misoperation of the devices often occurs, and great trouble is brought to users for electricity.

Disclosure of Invention

In view of the above, the present disclosure provides an arc fault detection circuit capable of accurately detecting an arc fault signal in a power supply line and implementing corresponding protection.

Based on this, according to one embodiment of the present disclosure, there is provided an arc fault detection circuit including: the signal acquisition circuit is used for acquiring current on the power supply line and outputting a first signal; the window gating circuit is used for outputting a window gating signal corresponding to the first signal, the window gating signal comprises a first level signal and a second level signal, the first level signal is used for shielding a signal corresponding to a preset time period in the first signal, and the second level signal is used for retaining a signal not corresponding to the preset time period in the first signal; and the signal processing circuit is electrically connected with the signal acquisition circuit and the window gating circuit and is used for generating an arc fault signal based on the window gating signal and the first signal.

According to the method, the window gating circuit is added into the arc fault detection circuit, whether the fault arc characteristics exist or not is judged only in the period when the harmful arc which is easy to cause fire is certain to appear, and judgment is not carried out in other periods, so that the accuracy of judging the harmful arc is greatly improved, the probability of misoperation of the arc fault protection device is greatly reduced, and the electricity consumption trouble of a user is solved while the arc fault protection is realized.

In one example of this embodiment, the signal processing circuit includes: and the characteristic extraction sub-circuit is used for carrying out arc characteristic extraction on the first signal to generate an arc characteristic signal.

In one example of this embodiment, the signal processing circuit includes: the signal amplifying sub-circuit is used for amplifying the first signal to acquire a second signal; and the characteristic extraction sub-circuit is electrically connected with the signal amplification sub-circuit and is used for carrying out arc characteristic extraction on the second signal so as to generate an arc characteristic signal.

In one example of this embodiment, the signal processing circuit includes: and the pulse driving sub-circuit is electrically connected with the characteristic extraction sub-circuit and is used for generating an arc pulse signal based on the arc characteristic signal.

In one example of this embodiment, the signal processing circuit includes: and the pulse counting sub-circuit is electrically connected with the driving pulse sub-circuit and is used for recording the pulse number in the arc pulse signal and generating the arc fault signal based on the pulse number of the arc pulse signal in a preset time period.

In one example of this embodiment, the window gating circuit includes: a first voltage dividing sub-circuit for dividing a voltage from the power supply line and outputting a first voltage signal; a second voltage dividing sub-circuit for dividing a voltage from the power supply line and outputting a second voltage signal; and the input end of the gating sub-circuit is connected with the output end of the first voltage dividing sub-circuit, the output end of the gating sub-circuit is connected with the output end of the second voltage dividing sub-circuit, and the gating sub-circuit is turned on when the input voltage of the input end of the gating sub-circuit is within a preset range, and is turned off otherwise, so that the window gating signal is output.

In an example of this embodiment, the gate sub-circuit includes a first voltage regulator, a first transistor, a second transistor, a first protection resistor and a second protection resistor, where a first end of the first voltage regulator is an input end of the gate sub-circuit, a second end of the first voltage regulator is connected to the first end of the first transistor, a second end of the first transistor is grounded, a third end of the first transistor is connected to the first end of the second transistor through the first protection resistor, a first end of the second transistor is connected to the first end of the second protection resistor, a second end of the second protection resistor is connected to the second end of the second transistor and a power supply voltage, and a third end of the second transistor is an output end of the gate sub-circuit.

In an example of this embodiment, the gate circuit includes a three-terminal adjustable voltage regulator, a second transistor, a first protection resistor and a second protection resistor, where a first end of the three-terminal adjustable voltage regulator is an input end of the gate circuit, a second end of the three-terminal adjustable voltage regulator is grounded, a third end of the three-terminal adjustable voltage regulator is connected with a first end of the second transistor through the first protection resistor, a first end of the second transistor is connected with a first end of the second protection resistor, a second end of the second protection resistor is connected with a second end of the second transistor and a power supply voltage, and a third end of the second transistor is an output end of the gate circuit.

In an embodiment of this implementation manner, the gating sub-circuit includes a first comparator, a first voltage dividing resistor, a second voltage dividing resistor, and a diode, where a positive phase end of the first comparator is an input end of the gating sub-circuit, an inverting end of the first comparator is connected with the first voltage dividing resistor and the second voltage dividing resistor, another end of the first voltage dividing resistor is connected with a power supply voltage, another end of the second voltage dividing resistor is grounded, an output end of the first comparator is connected with an anode of the diode, and a negative electrode of the diode is an output end of the gating sub-circuit.

In one example of this embodiment, the arc fault detection circuit includes: an arc fault driving circuit electrically connected with the signal processing circuit and used for generating a switch control signal based on the arc fault signal; and the switching circuit is electrically connected with the arc fault driving circuit and is used for opening or closing an input/output switch of the power supply line according to the switch control signal.

In one example of this embodiment, the arc fault detection circuit includes: and the output end of the analog arc test circuit is connected to the signal acquisition circuit or the signal processing circuit and is used for generating an analog arc signal, so that the switching circuit turns off the input/output switch of the power supply line according to the analog arc signal.

In one example of this embodiment, the arc fault detection circuit includes: and the power supply circuit comprises a rectifier and a second voltage stabilizer and is used for supplying power to the window gating circuit and the signal processing circuit after rectifying conversion and voltage stabilization treatment on the voltage of the power supply line.

In one example of this embodiment, the signal processing circuit includes: and the filtering sub-circuit is electrically connected with the signal acquisition circuit and is used for outputting the first signal after filtering.

In one example of this embodiment, the signal processing circuit includes a filtering sub-circuit, a feature extraction sub-circuit, and a driving pulse sub-circuit, and the window gate circuit is electrically connected to at least one of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and the driving pulse sub-circuit, for shielding the signal of the preset period in the output signals of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and/or the driving pulse sub-circuit.

Drawings

The disclosure will be better understood and other objects, details, features and advantages of the disclosure will become more apparent from the following description of specific embodiments thereof, which is set forth in the following drawings. In the drawings:

fig. 1 shows a system architecture diagram of an arc fault detection circuit in an embodiment of the present disclosure.

Fig. 2 shows a detailed circuit diagram of an arc fault detection circuit in an embodiment of the present disclosure.

Fig. 3 shows a detailed circuit diagram of an arc fault detection circuit in another embodiment of the present disclosure.

Fig. 4 shows a circuit diagram of a window gating circuit in an embodiment of the present disclosure.

Fig. 5 shows a circuit diagram of a window gating circuit in another embodiment of the present disclosure.

Fig. 6 shows a circuit diagram of a window gating circuit in yet another embodiment of the present disclosure.

Fig. 7 shows signal waveforms corresponding to resistive loads in an embodiment of the present disclosure.

Fig. 8 shows waveforms of signals corresponding to the induction cooker load in an embodiment of the present disclosure.

Fig. 9 shows waveforms of signals corresponding to induction cooker loads in another embodiment of the present disclosure.

Detailed Description

The present disclosure is described in further detail below with reference to the following detailed description and the accompanying drawings. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, some operations associated with the present application have not been shown or described in the specification to avoid obscuring the core portions of the present application, and may not be necessary for a person skilled in the art to describe in detail the relevant operations based on the description herein and the general knowledge of one skilled in the art.

The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated.

As shown in fig. 1, an embodiment of the present disclosure proposes a system architecture diagram of an arc fault detection circuit, including: a signal acquisition circuit 11, a window gating circuit 13 and a signal processing circuit 15. The signal acquisition circuit 11 is configured to acquire a current on a power supply line (e.g., L line, N line shown in fig. 1) and output a first signal. The window gating circuit 13 is configured to output a window gating signal corresponding to the first signal, where the window gating signal is configured to mask a current signal over a preset period of time for each cycle of the current, and to preserve a current characteristic signal of a period in which the arc is located. The window gating signal has a portion of the time period being at a higher level and the remainder being at a lower level during each cycle of the current signal on the supply line. A signal processing circuit 15 is electrically connected to the signal acquisition circuit 11 and the window gating circuit 13 for generating an arc fault signal based on the window gating signal and the first signal.

In some examples, signal processing circuit 15 includes a filtering sub-circuit 150, a signal amplification sub-circuit 151, a feature extraction sub-circuit 153, a driving pulse sub-circuit 155, and a pulse counting sub-circuit 157. The filtering sub-circuit 150 is electrically connected to the signal acquisition circuit 11, and is configured to output the first signal after filtering (i.e. output a current characteristic signal of a frequency band where an arc is located); the signal amplifying sub-circuit 151 is configured to amplify the first signal after the filtering process to obtain a second signal; the feature extraction sub-circuit 153 is electrically connected to the signal amplification sub-circuit 151, and is configured to perform arc feature extraction on the second signal to generate an arc feature signal; the pulse driving sub-circuit 155 is electrically connected to the characteristic extraction sub-circuit 153, and is configured to generate an arc pulse signal based on the arc characteristic signal (i.e., normalize the arc characteristic signal to an arc pulse signal having a certain duty cycle); the pulse counting sub-circuit 157 is electrically connected to the driving pulse sub-circuit 155 for recording the number of pulses in the arc pulse signal and generating the arc fault signal based on the number of pulses of the arc pulse signal for a preset period of time. The accuracy of arc fault detection can be improved by amplifying the first signal by the signal amplifying sub-circuit 151. In other examples, the signal processing circuit 15 may not include a signal amplifying sub-circuit, which is advantageous in simplifying the circuit and reducing the cost.

In some examples, the arc fault detection circuit further includes an arc fault drive circuit 17 and a switching circuit 19. Wherein an arc fault driving circuit 17 is electrically connected to the signal processing circuit 15 for generating a switch control signal based on the arc fault signal; a switching circuit 19 is electrically connected to the arc fault driving circuit 17 for opening or closing an input/output switch of the power supply line according to the switching control signal.

In some examples, the arc fault detection circuit further comprises an analog arc test circuit 21, the output of which is connected to the signal acquisition circuit 11 or the signal processing circuit 15, for generating an analog arc signal, so that the switching circuit 19 opens the input/output switch of the power supply line according to the analog arc signal. The simulated arc test circuit 21 detects whether the arc fault protection function of the product is normal by generating a simulated fault arc.

In some examples, the arc fault detection circuit further comprises a power supply circuit 23 for supplying power to the window gate circuit 13 and the signal processing circuit 15 after rectifying and stabilizing the voltage of the power supply line. The power supply circuit 23 is electrically connected to the power supply line, rectifies and converts alternating current from the power supply line by a rectifier, and processes the alternating current by a voltage regulator, thereby supplying stable direct current to a signal processing circuit, a window gate circuit, and the like.

In some examples, a window gating circuit is electrically connected to at least one of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and the drive pulse sub-circuit for masking the predetermined period of signals in the output signals of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and/or the drive pulse sub-circuit. That is, the window gating circuit may process the signal including the arc characteristic at any one or more stages of the signal processing process, mask the current signal over a predetermined period of time for each cycle of the current, and preserve the current characteristic waveform of the period in which the arc is located, thereby improving the accuracy of fault arc detection. As shown in fig. 2, an embodiment of the present disclosure proposes a detailed circuit diagram of an arc fault detection circuit. Referring to fig. 2, the arc fault detection circuit may be specifically described as follows.

In some examples, the signal acquisition circuit 11 includes a current transformer CT1, the current transformer CT1 acquiring current on the power supply line and outputting a first signal, i.e., a current signal of the power supply line.

In some examples, the filtering subcircuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R24, a capacitor C2, a capacitor C3, a capacitor C4, and a zener diode ZD1. The resistor R1 is connected with the secondary of the CT1 in parallel, a secondary current signal output by the CT1 is converted into a secondary voltage waveform, then the secondary voltage waveform of a frequency band where an electric arc is located is reserved after filtering is carried out through R2, R3, R4, C2, C3 and C4, and the voltage-stabilizing tube ZD1 limits the output voltage waveform. Wherein, the first end of R1 is connected with the first end of R2, and the second end of R1 is connected with the negative pole of regulator tube ZD1, and the positive pole of regulator tube is connected with the second end of R2 and the first end of C2, and the second end of C2 is connected with the first end of R3 and the first end of C3 is connected, and the second end of C3 is connected with the first end of R4 and the first end of C4, and the second end of C4 passes through R24 ground connection, and the second end of R3 and R4 is connected with the negative pole of ZD1 and ground connection. The second end of C4 is the output end of the filter sub-circuit.

In some examples, window gating circuit 13 includes a first voltage divider circuit, a second voltage divider circuit, and a gating sub-circuit, where the first voltage divider circuit is resistors R17 and R27 connected in series, the second voltage divider circuit is resistors R10 and R22 connected in series, where a connection point of R17 and R27 is an output terminal of the first voltage divider circuit, and outputs a first voltage signal; the connection point of R10 and R22 is the output end of the second voltage division subcircuit, and outputs a second voltage signal.

In some examples, the gating sub-circuit includes a voltage regulator ZD3, a first transistor Q3, a second transistor Q1, a first protection resistor R16, and a second protection resistor R13. The first end of the voltage stabilizing transistor ZD3 is an input end of the gating sub-circuit, the second end of the voltage stabilizing transistor ZD3 is connected with the first end of the first transistor Q3, the second end of the first transistor Q3 is grounded, the third end of the first transistor Q3 is connected with the first end of the second transistor Q1 through the first protection resistor R16, the first end of the second transistor Q1 is connected with the first end of the second protection resistor R13, the second end of the second protection resistor R13 is connected with the second end of the second transistor Q1 and the power supply voltage VCC, and the third end of the second transistor Q1 is an output end of the gating sub-circuit.

In some examples, the first transistor Q3 is an NPN bipolar transistor (with a base at a first end, an emitter at a second end, and a collector at a third end), and the second transistor Q1 is a PNP bipolar transistor (with a base at a first end, an emitter at a second end, and a collector at a third end). In other examples, the first transistor Q3 and the second transistor Q1 may be field effect transistors.

In some examples, the window gating circuit 13 further includes filter capacitors C8 and C10, where C8 is connected in parallel with the voltage dividing resistor R27, and C10 is connected in parallel with the voltage dividing resistor R22, and the gating effect of the window gating signal can be improved through the filtering process. Preferably, the capacitor C8 is a phase shift capacitor, and the gating accuracy of the window gating circuit is improved by adjusting the phase of the voltage input to the window gating circuit 13 by the rectifier DB 1.

As shown in fig. 3, an embodiment of the present disclosure proposes a detailed circuit diagram of another arc fault detection circuit. The switching circuit 19 in fig. 3 is provided at a power supply terminal (an input terminal of a power supply line), and the switching circuit 19 in fig. 2 is provided at a load terminal (an output terminal of the power supply line). Fig. 2 and 3 illustrate that the location where the arc fault detection circuit performs the protection action may be flexibly adjusted as desired, but is not limited thereto. The connection manner between the window gating circuit 13 and the signal processing circuit 15 in fig. 3 is also different from fig. 2, and fig. 3 and 2 exemplarily illustrate that the window gating circuit can mask signals of various stages in the signal processing process for signals of a preset period, and the connection manner between the window gating circuit 13 and the signal processing circuit and the signal acquisition circuit can be flexibly adjusted according to the needs, but are not limited to the manners shown in fig. 2 and 3.

Referring to fig. 3, in some examples, the third terminal of the second transistor Q1, i.e., the output terminal of the gating sub-circuit, is connected in parallel with the secondary of CT1 in the signal acquisition circuit 11 through the fourth transistor Q4, i.e., the first terminal of the fourth transistor Q4 (e.g., the base of the bipolar transistor) is connected to the third terminal of Q1, the second terminal of the Q4 (e.g., the emitter of the bipolar transistor) is grounded, and the third terminal of the Q4 (e.g., the collector of the bipolar transistor) is connected to the output terminal of CT 1.

Fig. 4, 5 and 6 are circuit diagrams of different embodiments of the window gate circuit 13, respectively. It should be noted that, in fig. 4-6, the window gating circuit 13 gates the signal from the signal amplifying sub-circuit 151 and outputs the signal to the driving pulse sub-circuit, but the window gating circuit 13 in this disclosure is not limited to gate the output of the signal amplifying sub-circuit 151, and may gate the outputs of the signal collecting circuit, the filtering sub-circuit, the feature extracting sub-circuit and the driving pulse sub-circuit.

As shown in fig. 4, the window gate signal output from the window gate circuit 13 is input to the inverting terminal (-) of the comparator IC1A of the feature extraction sub-circuit 153, the second signal output from the signal amplification sub-circuit 151 is input to the non-inverting terminal (+) of the comparator IC1A, and the first voltage dividing sub-circuits R17 and R27 receive the voltage output after the ac voltage of the power supply line is rectified by the rectifier DB 1. The working principle of the circuit can be explained as follows:

when the inverting terminal of the IC1A is at a higher level, the second signal output by the signal amplifying sub-circuit is forbidden to be output to the next stage; when the inverting terminal of the IC1A is at a lower level, the second signal (stronger signal) of the signal amplifying sub-circuit is allowed to be transmitted to the next stage. Specifically, the alternating current of the power supply line is rectified by DB1 and then divided by R17 and R27, the voltage at the upper end of R27 linearly changes along with the voltage of the power supply line, when the voltage at the upper end of R27 exceeds a set value, the current triggers Q3 to be turned on and then triggers Q1 to be turned on, at this time, the voltage at the inverting end of the comparator IC1A rises to the working voltage of IC1, and the voltage signal from the signal amplifying sub-circuit 151 cannot pass through IC1A; when the voltage at the upper end of R27 does not exceed the set value, Q3 is cut off, Q1 is cut off, the voltage at the inverting end of IC1A is lower voltage after the voltage of the power supply of IC1 is divided by R10 and R22, and at the moment, if a stronger signal exists in the voltage signal from the signal amplifying sub-circuit to exceed the set value, the output end of IC1A is at a high level.

In some examples, the set point is adjusted by adjusting the model parameters of ZD3 and/or R17 and R27. And the window gating signal output by the window gating circuit is extracted to a third signal in a corresponding time period in the second signal by adjusting the set value. If an arc fault occurs in the supply line, the arc fault signal must appear in the third signal. Therefore, the arc characteristic extraction of the third signal greatly improves the accuracy of the harmful arc judgment.

As shown in fig. 5, in some examples, the gating sub-circuit includes a three-terminal adjustable voltage regulator U1, a second transistor Q1, a first protection resistor R16, and a second protection resistor R13. The first end of the three-terminal adjustable voltage stabilizer U1 is an input end of a gating sub-circuit, the second end of the three-terminal adjustable voltage stabilizer U1 is grounded, the third end of the three-terminal adjustable voltage stabilizer U1 is connected with the first end of the second transistor Q1 through a first protection resistor R16, the first end of the second transistor Q1 is connected with the first end of a second protection resistor R13, the second end of the second protection resistor R13 is connected with the second end of the second transistor Q1 and a power supply voltage VCC, and the third end of the second transistor Q1 is an output end of the gating sub-circuit. In some examples, the second transistor Q1 is a PNP bipolar transistor (with a base at a first end, an emitter at a second end, and a collector at a third end). In other examples, the second transistor Q1 may be a field effect transistor. The working principle of the circuit diagram shown in fig. 5 is similar to that of fig. 4, so that the description is omitted, and the difference between fig. 5 and fig. 4 is that ZD3 and Q3 in fig. 4 are replaced by a three-terminal adjustable voltage regulator U1, so that the patch element is reduced, and the product volume is reduced.

As shown in fig. 6, in some examples, the gating sub-circuit includes a first comparator IC1B, a first voltage dividing resistor R13, a second voltage dividing resistor R16, and a diode D5, where a non-inverting terminal of the first comparator IC1B is an input terminal of the gating sub-circuit, an inverting terminal of the first comparator IC1B is connected to the first voltage dividing resistor R13 and the second voltage dividing resistor R16, another terminal of the first voltage dividing resistor R13 is connected to a power supply voltage VCC, another terminal of the second voltage dividing resistor R16 is grounded, an output terminal of the first comparator IC1B is connected to an anode of the diode D5, and a negative terminal of the diode D5 is an output terminal of the gating sub-circuit. The principle of operation of the circuit diagram of fig. 6 can be expressed as follows: setting the reference voltage of the inverting terminal of the comparator IC1B by dividing the voltage of R13 and R16, when the voltage of the upper terminal of R27 exceeds the reference voltage of the inverting terminal of the comparator IC1B, the IC1B outputs a high level, the voltage of the inverting terminal of the comparator IC1A rises to the working voltage, and at the moment, the voltage signal from the signal amplifying sub-circuit 151 cannot pass through the IC1A; when the upper voltage of R27 is lower than the set value, IC1B outputs a low level, the inverting terminal voltage of IC1A is a lower voltage obtained by dividing the power supply voltage by R10 and R22, and if the voltage signal from the signal amplifying sub-circuit 151 has a stronger signal exceeding the set value, the output terminal of IC1A is at a high level.

In some examples, the arc fault drive circuit 17 includes a solenoid SOL and a thyristor Q2. The output terminal of the signal processing circuit 15 is connected to the control terminal of the thyristor Q2 through the resistor R14, so that the arc fault signal generated by the signal processing circuit controls the arc fault driving circuit 17, i.e., controls whether the thyristor Q2 is turned on or not. When the thyristor Q2 is turned on, the input/output switch circuit 19 will be disconnected, i.e. the solenoid SOL flows a larger current, thereby generating a magnetic force, and the iron core inside will move to disconnect the switch circuit 19.

In some examples, the power supply circuit 23 includes a rectifier DB1, a resistor R11, a regulator ZD4, and a filter capacitor C7. The first end (1) and the third end (3) of the rectifier DB1 are respectively and electrically connected with an L (HOT) line and an N (WHITE) line of a power supply line, the second end of the rectifier DB1 is connected with the input end of a window gating circuit and the first end of a resistor R11, the second end of the resistor R11 is connected with the negative electrode of a voltage stabilizing tube ZD4, and the voltage stabilizing tube ZD4 and a capacitor C7 are connected in parallel.

In some examples, the simulated arc TEST circuit 21 includes a TEST button (TEST) and a protection resistor R6. When the user presses the test button, an arc analog signal is generated and output to the signal acquisition circuit 11 or the signal processing circuit 15, and whether the arc fault protection function can be normally implemented is detected.

Fig. 7 and 8 are output waveform diagrams of respective circuit modules to which the resistive load and the induction cooker load of the present disclosure shown in fig. 2 are applied, respectively, more intuitively showing the technical effects of the present disclosure.

Fig. 7 shows a window gate signal A1, a load current signal A2, an arc characteristic signal A3 and an arc pulse signal A4 corresponding to a resistive load, and as can be seen from fig. 7, at the zero crossing point of the load current signal A2, an arc characteristic ("flat shoulder") appears at a lower level part of the corresponding window gate signal A1, a corresponding characteristic waveform appears in the arc characteristic signal A3, and a corresponding arc pulse appears in the arc pulse signal A4. Therefore, the arc fault detection circuit disclosed by the utility model extracts the arc characteristics in the A3 through the A1, so that whether the arc fault occurs or not can be judged through the formed arc pulse, the judgment range is reduced, and the judgment precision is improved.

Fig. 8 shows a window gating signal B1, a load current signal B2, an arc characteristic signal B3 and an arc pulse signal B4 corresponding to the load of the induction cooker, and as can be seen from fig. 8, a significant high-frequency signal appears at the peak portion of the load current signal B2, overlaps with the arc frequency band, and a significant characteristic signal appears on the arc characteristic signal B3 correspondingly, but since the characteristic signal corresponds to the high-level portion of the window gating signal B1, is completely shielded, and therefore does not appear on the arc pulse signal B4, thereby avoiding causing malfunction.

Fig. 9 is a waveform diagram of the output of each circuit module of the induction cooker load to which the present disclosure shown in fig. 2 is applied, and there are a window gate signal C1, a load current signal C2, an arc characteristic signal C3, and an arc pulse signal C4, and as can be seen from fig. 9, a significant high-frequency signal appears at the peak portion of the load current signal C2, overlapping with the arc frequency band, but since the characteristic signal corresponds to the high-level portion of the window gate signal C1, it is completely shielded, and thus does not appear at the arc characteristic signal C3 and the arc pulse signal C4, thereby avoiding causing malfunction.

Reference is made to various exemplary embodiments herein. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope herein. While the principles herein have been shown in various embodiments, many modifications of structure, arrangement, proportions, elements, materials, and components, which are particularly adapted to specific environments and operative requirements, may be used without departing from the principles and scope of the present disclosure. The above modifications and other changes or modifications are intended to be included within the scope of this document. The foregoing detailed description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes may be made without departing from the scope of the present disclosure. Accordingly, the present disclosure is to be considered as illustrative and not restrictive in character, and all such modifications are intended to be included within the scope thereof. Also, advantages, other advantages, and solutions to problems have been described above with regard to various embodiments. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, system, article, or apparatus. Furthermore, the term "couple" and any other variants thereof are used herein to refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.

Those having ordinary skill in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the present disclosure. Accordingly, the scope of the disclosure should be determined solely by the claims.

Claims (14)

1. An arc fault detection circuit, comprising:

the signal acquisition circuit is used for acquiring current on the power supply line and outputting a first signal;

the window gating circuit is used for outputting a window gating signal corresponding to the first signal, the window gating signal comprises a first level signal and a second level signal, the first level signal is used for shielding a signal corresponding to a preset time period in the first signal, and the second level signal is used for retaining a signal not corresponding to the preset time period in the first signal;

and the signal processing circuit is electrically connected with the signal acquisition circuit and the window gating circuit and is used for generating an arc fault signal based on the window gating signal and the first signal.

2. The arc fault detection circuit of claim 1, wherein the signal processing circuit comprises:

and the characteristic extraction sub-circuit is used for carrying out arc characteristic extraction on the first signal to generate an arc characteristic signal.

3. The arc fault detection circuit of claim 1, wherein the signal processing circuit comprises:

the signal amplifying sub-circuit is used for amplifying the first signal to acquire a second signal;

and the characteristic extraction sub-circuit is electrically connected with the signal amplification sub-circuit and is used for carrying out arc characteristic extraction on the second signal so as to generate an arc characteristic signal.

4. An arc fault detection circuit according to claim 2 or 3, wherein the signal processing circuit comprises:

and the pulse driving sub-circuit is electrically connected with the characteristic extraction sub-circuit and is used for generating an arc pulse signal based on the arc characteristic signal.

5. The arc fault detection circuit of claim 4, wherein the signal processing circuit comprises:

and the pulse counting sub-circuit is electrically connected with the driving pulse sub-circuit and is used for recording the pulse number in the arc pulse signal and generating the arc fault signal based on the pulse number of the arc pulse signal in a preset time period.

6. The arc fault detection circuit of claim 1, wherein the window gating circuit comprises:

a first voltage dividing sub-circuit for dividing a voltage from the power supply line and outputting a first voltage signal;

a second voltage dividing sub-circuit for dividing a voltage from the power supply line and outputting a second voltage signal;

and the input end of the gating sub-circuit is connected with the output end of the first voltage dividing sub-circuit, the output end of the gating sub-circuit is connected with the output end of the second voltage dividing sub-circuit, and the gating sub-circuit is turned on when the input voltage of the input end of the gating sub-circuit is within a preset range, and is turned off otherwise, so that the window gating signal is output.

7. The arc fault detection circuit of claim 6, wherein the gating sub-circuit comprises a first voltage regulator, a first transistor, a second transistor, a first protection resistor, and a second protection resistor, wherein a first end of the first voltage regulator is an input end of the gating sub-circuit, a second end of the first voltage regulator is connected to the first end of the first transistor, a second end of the first transistor is grounded, a third end of the first transistor is connected to the first end of the second transistor through the first protection resistor, a first end of the second transistor is connected to the first end of the second protection resistor, a second end of the second protection resistor is connected to the second end of the second transistor and a power supply voltage, and a third end of the second transistor is an output end of the gating sub-circuit.

8. The arc fault detection circuit of claim 6, wherein the gating circuit comprises a three-terminal adjustable voltage regulator, a second transistor, a first protection resistor and a second protection resistor, wherein a first terminal of the three-terminal adjustable voltage regulator is an input terminal of the gating circuit, a second terminal of the three-terminal adjustable voltage regulator is grounded, a third terminal of the three-terminal adjustable voltage regulator is connected with the first terminal of the second transistor through the first protection resistor, a first terminal of the second transistor is connected with the first terminal of the second protection resistor, a second terminal of the second protection resistor is connected with a second terminal of the second transistor and a power supply voltage, and a third terminal of the second transistor is an output terminal of the gating circuit.

9. The arc fault detection circuit of claim 6, wherein the gating sub-circuit comprises a first comparator, a first voltage dividing resistor, a second voltage dividing resistor and a diode, wherein a positive phase end of the first comparator is an input end of the gating sub-circuit, an inverting end of the first comparator is connected with the first voltage dividing resistor and the second voltage dividing resistor, the other end of the first voltage dividing resistor is connected with a power supply voltage, the other end of the second voltage dividing resistor is grounded, an output end of the first comparator is connected with an anode of the diode, and a negative electrode of the diode is an output end of the gating sub-circuit.

10. The arc fault detection circuit of claim 1, comprising:

an arc fault driving circuit electrically connected with the signal processing circuit and used for generating a switch control signal based on the arc fault signal;

and the switching circuit is electrically connected with the arc fault driving circuit and is used for opening or closing an input/output switch of the power supply line according to the switch control signal.

11. The arc fault detection circuit of claim 10, comprising:

and the output end of the analog arc test circuit is connected to the signal acquisition circuit or the signal processing circuit and is used for generating an analog arc signal, so that the switching circuit turns off the input/output switch of the power supply line according to the analog arc signal.

12. The arc fault detection circuit of claim 1, comprising:

and the power supply circuit comprises a rectifier and a second voltage stabilizer and is used for supplying power to the window gating circuit and the signal processing circuit after rectifying conversion and voltage stabilization treatment on the voltage of the power supply line.

13. The arc fault detection circuit of claim 1, wherein the signal processing circuit comprises:

and the filtering sub-circuit is electrically connected with the signal acquisition circuit and is used for outputting the first signal after filtering.

14. The arc fault detection circuit of claim 1, wherein the signal processing circuit comprises a filter sub-circuit, a feature extraction sub-circuit, and a drive pulse sub-circuit, the window gating circuit being electrically connected to at least one of the signal acquisition circuit, the filter sub-circuit, the feature extraction sub-circuit, and the drive pulse sub-circuit for masking the signal of the preset period in the output signal of the signal acquisition circuit, the filter sub-circuit, the feature extraction sub-circuit, and/or the drive pulse sub-circuit.