CN220457391U - Level signal integration and conversion circuit - Google Patents

Abstract

The application provides a level signal integration conversion circuit, including: a plurality of level signal input terminals, a plurality of first transistors, a second transistor, a first power supply terminal, a second power supply terminal, a ground terminal, and a level signal output terminal; the number of the first transistors is greater than or equal to the number of the level signal input terminals; the control electrode of the first transistor is electrically connected with the corresponding level signal input end, the first electrode of the first transistor is electrically connected with the first power supply end, and the second electrode of the first transistor is electrically connected with the control electrode of the second transistor; wherein the control electrode of the second transistor is extremely high in level conduction; the first electrode of the second transistor is electrically connected with the level signal output end, and the second electrode of the second transistor is electrically connected with the grounding end; the level signal output end is electrically connected with the second power supply end. The output level signal of the level signal integration conversion circuit can be made to match with the input level signal required by the subsequent circuit.

Description

Level signal integration and conversion circuit

Technical Field

The application belongs to the technical field of integrated circuits, and particularly relates to a level signal integration and conversion circuit.

Background

In a circuit of a battery management system (Battery Management System, BMS), a secondary overvoltage protection chip of a battery cell is generally used for secondary overvoltage protection of 5 cells connected in series, and a mode of cascading a plurality of secondary overvoltage chips is generally adopted when the secondary overvoltage protection chip is used for secondary overvoltage protection of more than 5 cells connected in series. When the voltage of the battery core of any battery core is larger than the overvoltage threshold value, the secondary overvoltage protection chip corresponding to the battery core outputs a level signal which is used for informing a later-stage circuit such as a main loop of the BMS circuit, and the front-stage circuit has the problem of overvoltage of the voltage of the battery core.

However, when one secondary overvoltage protection chip corresponds to one output level signal, a plurality of secondary overvoltage chips are cascaded to correspond to a plurality of output level signals, and when a later circuit only needs one input level signal, the output level signal of the former circuit is not matched with the input level signal needed by the later circuit.

Disclosure of Invention

The application provides a level signal integration conversion circuit to solve the problem that output level signals of a front-stage circuit and input level signals required by a rear-stage circuit are not matched in the prior art. The level signal integration and conversion circuit comprises: a plurality of level signal input terminals, a plurality of first transistors, a second transistor, a first power supply terminal, a second power supply terminal, a ground terminal, and a level signal output terminal; the number of the first transistors is greater than or equal to the number of the level signal input terminals;

the control electrode of the first transistor is electrically connected with the corresponding level signal input end, the first electrode of the first transistor is electrically connected with the first power supply end, and the second electrode of the first transistor is electrically connected with the control electrode of the second transistor; wherein the control electrode of the second transistor is extremely high in level conduction;

the first pole of the second transistor is electrically connected with the level signal output end, and the second pole of the second transistor is electrically connected with the grounding end;

the level signal output end is electrically connected with the second power supply end.

Optionally, the circuit further comprises: a voltage stabilizing component; one end of the voltage stabilizing component is electrically connected with the control electrode of the second transistor, and the other end of the voltage stabilizing component is electrically connected with the second electrode of the second transistor; the stable voltage of the voltage stabilizing component is smaller than the preset withstand voltage value of the second transistor.

Optionally, the voltage stabilizing component is a voltage stabilizing diode; the cathode of the zener diode is electrically connected with the control electrode of the second transistor, and the anode of the zener diode is electrically connected with the second electrode of the second transistor.

Optionally, the circuit further comprises: a capacitor assembly; one end of the capacitor assembly is electrically connected with the control electrode of the second transistor, and the other end of the capacitor assembly is electrically connected with the second electrode of the second transistor.

Optionally, the circuit further comprises: a first resistor assembly; one end of the first resistor component is electrically connected with the control electrode of the second transistor, and the other end of the first resistor component is electrically connected with the second electrode of the second transistor.

Optionally, the circuit further comprises: a plurality of second resistor elements, the number of the second resistor elements being equal to the number of the first transistors;

one end of the second resistor component is electrically connected with the control electrode of the corresponding first transistor, and the other end of the second resistor component is electrically connected with the first electrode of the corresponding first transistor.

Optionally, the circuit further comprises: a plurality of first unidirectional conductive components, the number of the first unidirectional conductive components being equal to the number of the first transistors; the first unidirectional conduction component is arranged between the level signal input end and the corresponding first transistor;

one end of the first unidirectional conduction component is electrically connected with the level signal input end, and the other end of the first unidirectional conduction component is electrically connected with the corresponding control electrode of the first transistor.

Optionally, the circuit further comprises: a plurality of second unidirectional conductive components, the number of which is equal to the number of the first transistors; the second unidirectional conduction component is arranged between the second transistor and the corresponding first transistor;

one end of the second unidirectional conduction component is electrically connected with the second electrode of the first transistor, and the other end of the second unidirectional conduction component is electrically connected with the control electrode of the second transistor.

Optionally, the second transistor is an N-channel MOS transistor.

Optionally, the plurality of first transistors are all N-channel MOS transistors, or the plurality of first transistors are all P-channel MOS transistors.

In this embodiment of the present utility model, since the control electrode of the first transistor is electrically connected to the corresponding level signal input end, the conduction or the disconnection of the first transistor may be controlled by the level signal input end, when any one of the first transistors is turned on, the first electrode and the second electrode of the first transistor are respectively connected between the first power supply end and the second transistor, and since the control electrode of the second transistor is extremely high in level conduction, the high level output by the first power supply end may control the control electrode of the second transistor to be conducted, the level signal output end respectively connected to the first electrode and the second electrode of the second transistor is conducted with the ground end, the level signal output end outputs a low level signal corresponding to the ground end, and when all of the plurality of first transistors are not conducted, the first power supply end and the second transistor are not conducted, and the level signal output by the level signal output end outputs a high level signal corresponding to the second power supply end, so that the level signal output by the level signal output end can meet the requirement of integrating a plurality of output level signals of the front stage circuit into a level signal required to be converted, and the level signal output by the level signal output circuit is more matched with the input signal.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief description will be given below of the drawings that are needed in the embodiments or the prior art descriptions, and it is obvious that the drawings in the following description are some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a circuit diagram of a level signal integrating and converting circuit according to an embodiment of the present application;

FIG. 2 is a second circuit diagram of a level signal integrated switching circuit according to an embodiment of the present disclosure;

FIG. 3 is a third circuit diagram of the level signal integrating and converting circuit according to the embodiment of the present application;

fig. 4 is a circuit diagram of a level signal integrated conversion circuit according to an embodiment of the present application.

Reference numerals:

a 10-level signal integration and conversion circuit; 101-level signal input; 102-a first transistor; 1021-the control electrode of the first transistor; 1022-a first pole of a first transistor; 1023-a second pole of the first transistor; 103-a second transistor; 1031-a control electrode of the second transistor; 1032-a first pole of a second transistor; 1033-a second pole of the second transistor; 104-a first power supply terminal; 105-a second power supply terminal; 106-a ground terminal; 107-level signal output terminal.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Fig. 1 is a circuit configuration diagram of a level signal integration and conversion circuit provided in an embodiment of the present application, and the level signal integration and conversion circuit 10 includes: a plurality of level signal input terminals 101, a plurality of first transistors 102, a plurality of second transistors 103, a first power supply terminal 104, a second power supply terminal 105, a ground terminal 106, and a level signal output terminal 107; the number of first transistors 102 is greater than or equal to the number of level signal input terminals 101;

the control electrode 1021 of the first transistor 102 is electrically connected to the corresponding level signal input terminal 101, the first electrode 1022 of the first transistor 102 is electrically connected to the first power supply terminal 104, and the second electrode 1023 of the first transistor 102 is electrically connected to the control electrode 1031 of the second transistor 103; wherein the control electrode 1031 of the second transistor 103 is turned on at a high level;

a first pole 1032 of the second transistor 103 is electrically connected to the level signal output terminal 107, and a second pole 1033 of the second transistor 103 is electrically connected to the ground terminal 106;

the level signal output terminal 107 is electrically connected to the second power supply terminal 105.

In this embodiment, the first transistor 102 may be a metal-oxide-semiconductor (Metal Oxide Semiconductor, MOS) field effect transistor, specifically, an N-channel metal-oxide-semiconductor field effect transistor, i.e., an NMOS transistor, or a P-channel metal-oxide-semiconductor field effect transistor, i.e., a PMOS transistor. Alternatively, the first transistor 102 may be a transistor, specifically, an NPN transistor or a PNP transistor. The MOS tube is a switch and comprises a grid electrode, a source electrode and a drain electrode, wherein the grid electrode is a control electrode 1021 and is used for controlling whether the source electrode and the drain electrode can be conducted or not, namely whether current can pass through the source electrode and the drain electrode, the NMOS tube is effective at a high level of the grid electrode, the high level is generally 5-10V, the PMOS tube is effective at a low level of the grid electrode, and the low level is generally-10-5V. The triode can also be used as a switch, the triode comprises a base electrode, a collector electrode and an emitter electrode, the triode is conducted when the base electrode of the NPN triode is at a high level, and the triode is conducted when the base electrode of the PNP triode is at a low level.

In this embodiment of the present application, the number of the first transistors 102 is greater than or equal to the number of the level signal input ends 101, where the first transistors 102 are connected to the level signal input ends 101 in a one-to-one correspondence manner, and more first transistors 102 may be empty, specifically, when the first transistors 102 are NMOS transistors, the gates may be grounded, and when the first transistors 102 are PMOS transistors, the gates may be connected to a power supply, so that the redundant first transistors 102 are turned off for later use when level signal expansion is performed. The control electrode 1021 of the first transistor 102 may be a gate of a MOS transistor, the first electrode 1022 of the first transistor 102 may be a source or a drain of a MOS transistor, and correspondingly, the second electrode 1023 of the first transistor 102 may be a drain or a source of a MOS transistor, specifically, when the first transistor 102 is an NMOS transistor, the first electrode 1022 of the first transistor 102 may be a drain of an NMOS transistor, the second electrode 1023 of the first transistor 102 may be a source of an NMOS transistor, or when the first transistor 102 is a PMOS transistor, the first electrode 1022 of the first transistor 102 may be a source of a PMOS transistor, and the second electrode 1023 of the first transistor 102 may be a drain of a PMOS transistor. Alternatively, the control electrode 1021 of the first transistor 102 may be a base electrode of a triode, the first electrode of the first transistor 102 may be a collector electrode or an emitter electrode of a triode, and accordingly, the second electrode 1023 of the first transistor 102 may be an emitter electrode or a collector electrode of a triode, specifically, when the first transistor 102 is an NPN type triode, the first electrode 1022 of the first transistor 102 may be a collector electrode of an NPN type triode, the second electrode 1023 of the first transistor 102 may be an emitter electrode of an NPN type triode, or, when the first transistor 102 is a PNP type triode, the first electrode 1022 of the first transistor 102 may be an emitter electrode of a PNP type triode, and the second electrode 1023 of the first transistor 102 may be a collector electrode of a PNP type triode. This is by way of example only, and the embodiments of the present application are not limited thereto.

In this embodiment, the second transistor 103 may be an NMOS transistor, the control electrode 1031 of the second transistor 103 may be a gate of the NMOS transistor, and the control electrode of the second transistor 103 is turned on at a very high level, that is, the NMOS transistor is turned on at a high level, and the high level is typically 5-10V, which is only illustrated herein, and the embodiment of the present application does not limit the present application. The first pole 1032 of the second transistor 103 may be a drain of an NMOS transistor and the second pole 1033 of the second transistor 103 may be a source of an NMOS transistor. Alternatively, the second transistor 103 may be an NPN transistor, the control electrode 1031 of the second transistor 103 may be a base electrode of the NPN transistor, the first electrode 1032 of the second transistor 103 may be a collector electrode of the NPN transistor, and the second electrode 1023 of the second transistor 103 may be a collector emitter electrode of the NPN transistor. This is by way of example only, and the embodiments of the present application are not limited thereto.

In this embodiment, when the first transistor 102 is an NMOS transistor, in the case that the low level signal is input to each of the level signal input terminals 101, the control electrode 1021 of the first transistor 102 correspondingly connected to the level signal input terminal 101, that is, the gate electrode of the NMOS transistor does not reach the conducting condition, the first transistor 102 is turned off, that is, the first electrode 1022 of the first transistor 102 is not conducted with the second electrode 1023, and further, the first power supply terminal 104 is not conducted with the control electrode 1031 of the second transistor 103, and since the control electrode 1031 of the second transistor 103 is conducted at a high level, the second transistor 103 is turned off, and the level signal output terminal 107 can output the high level signal corresponding to the second power supply terminal 105, thereby integrating and converting the plurality of low level signals into one high level signal output. The high level signal corresponding to the second power supply terminal 105 may be determined according to the requirement of the input signal of the subsequent stage circuit, which is not limited in the embodiment of the present application. Alternatively, when the first transistor 102 is an NPN-type transistor, the base of the NPN-type transistor is turned on when the base of the NPN-type transistor is at a high level, and when a low-level signal is input to each of the level signal input terminals 101, the NPN-type transistor is turned off, and thus the second transistor 103 is turned off, the level signal output terminal 107 may output a high-level signal corresponding to the second power supply terminal 105, so that a plurality of low-level signals are integrated and converted into one high-level signal to be output. This is by way of example only, and the embodiments of the present application are not limited thereto.

In this embodiment, when the first transistor 102 is an NMOS transistor, in the case where a high level signal is input to any one of the level signal input terminals 101, the control electrode 1021 of the first transistor 102 connected to the level signal input terminal 101, that is, the gate of the NMOS transistor, reaches a conducting condition, the first transistor 102 is turned on, that is, the first electrode 1022 of the first transistor 102 is conducted with the second electrode 1023, the first power supply terminal 104 is further conducted with the control electrode 1031 of the second transistor 103, at this time, a high level signal corresponding to the first power supply terminal 104 is given to the control electrode 1031 of the second transistor 103, and since the control electrode 1031 of the second transistor 103 is conducted at a high level, the second transistor 103 is turned on, that is, the first electrode 1032 of the second transistor 103 is conducted with the second electrode 1023 of the first transistor 102, and then the level signal output terminal 107 is conducted with the ground terminal 106, and the level signal output terminal 107 is pulled to the ground, thereby outputting a low level signal. Thereby integrating the plurality of level signals into one low level signal output. Alternatively, when the first transistor 102 is an NPN-type transistor, if a high-level signal is input to any one of the level signal input terminals 101, the corresponding NPN-type transistor is turned on, and the second transistor 103 is turned on, so that the level signal output terminal 107 is turned on with the ground terminal 106, and the level signal output terminal 107 is pulled to the ground, and a low-level signal can be output. Thereby integrating the plurality of level signals into one low level signal output. This is by way of example only, and the embodiments of the present application are not limited thereto.

In this embodiment, when the first transistor 102 is a PMOS transistor, in the case that each of the level signal input terminals 101 inputs a high level signal, the control electrode 1021 of the first transistor 102 connected to the level signal input terminal 101, that is, the gate electrode of the PMOS transistor does not reach the conducting condition, the first transistor 102 is turned off, that is, the first electrode 1022 of the first transistor 102 is not conducted with the second electrode 1023, and further, the first power supply terminal 104 is not conducted with the control electrode 1031 of the second transistor 103, and since the control electrode 1031 of the second transistor 103 is conducted at a high level, the second transistor 103 is turned off, and the level signal output terminal 107 can output the high level signal corresponding to the second power supply terminal 105, thereby integrating and converting the plurality of high level signals into one high level signal for output. The high level signal corresponding to the second power supply terminal 105 may be determined according to the requirement of the input signal of the subsequent stage circuit, which is not limited in the embodiment of the present application. Alternatively, when the first transistor 102 is a PNP transistor, the PNP transistor is turned on when the base of the PNP transistor is at a low level, and when each of the level signal input terminals 101 inputs a high level signal, the PNP transistor is turned off, and thus the second transistor 103 is turned off, and the level signal output terminal 107 can output a high level signal corresponding to the second power supply terminal 105, so as to integrate and convert a plurality of high level signals into one high level signal for output.

In this embodiment, when the first transistor 102 is a PMOS transistor, in a case where a low level signal is input to any level signal input terminal 101, the control electrode 1021 of the first transistor 102 connected to the level signal input terminal 101, that is, the gate of the PMOS transistor, reaches a conducting condition, the first transistor 102 is turned on, that is, the first electrode 1022 of the first transistor 102 is conducted with the second electrode 1023, the first power supply terminal 104 is conducted with the control electrode 1031 of the second transistor 103, at this time, a high level signal corresponding to the first power supply terminal 104 is given to the control electrode 1031 of the second transistor 103, and since the control electrode 1031 of the second transistor 103 is conducted at a high level, the second transistor 103 is turned on, that is, the first electrode 1022 of the second transistor 103 is conducted with the second electrode 1023, and then the level signal output terminal 107 is conducted with the ground terminal 106, and the level signal output terminal 107 is pulled to the ground, so that a low level signal can be output. Thereby integrating the plurality of level signals into one low level signal output. Alternatively, when the first transistor 102 is a PNP transistor, if a low level signal is input to any one of the level signal input terminals 101, the PNP transistor is turned on, and the second transistor 103 is turned on, so that the level signal output terminal 107 is turned on with the ground terminal 106, and the level signal output terminal 107 is pulled to the ground, and a low level signal can be output. Thereby integrating the plurality of level signals into one low level signal output. This is by way of example only, and the embodiments of the present application are not limited thereto.

In this embodiment of the present application, since the control electrode 1021 of the first transistor 102 is electrically connected to the corresponding level signal input terminal 101, the conduction or the disconnection of the first transistor 102 can be controlled by the level signal input terminal 101, when any one of the first transistors 102 is conducted, the first electrode 1022 and the second electrode 1023 of the first transistor 102 are respectively connected between the first power supply terminal 104 and the second transistor 103, and because the control electrode 1031 of the second transistor 103 is conducted at a high level, the high level output by the first power supply terminal 104 can control the control electrode 1031 of the second transistor 103 to be conducted, the level signal output terminal 107 respectively connected with the first electrode 1022 and the second electrode 1023 of the second transistor 102 is conducted with the ground terminal, and the level signal output terminal 107 outputs a low level signal corresponding to the ground terminal 106, and when none of the first transistors 102 are conducted, the first power supply terminal 104 and the second transistor 103 are not conducted, and no high level is given to the control electrode 1031 of the second transistor 103, so that the level signal output by the second power supply terminal 103 is more suitable for the level signal output circuit after the level signal output by the first level signal output terminal and the second level signal output terminal is more suitable for the level signal output circuit.

Optionally, the circuit further comprises: a voltage stabilizing component; one end of the voltage stabilizing component is electrically connected with the control electrode 1031 of the second transistor 103, and the other end of the voltage stabilizing component is electrically connected with the second electrode 1033 of the second transistor 103; the stabilizing voltage of the stabilizing component is smaller than the preset withstand voltage value of the second transistor 103.

In this embodiment, the preset voltage withstand value of the second transistor 103 refers to a threshold voltage of breakdown of the second transistor 103, for example, a maximum voltage withstand of a gate and a source of the MOS transistor, and a high voltage greater than the maximum voltage withstand would breakdown the gate and the source of the MOS transistor, resulting in damage of the MOS transistor. The turn-on voltage of the MOS transistor is generally 1.5-4 volts (V), which can be determined according to the actual parameters of the MOS transistor, and the gate usually needs to be turned on three times, such as 6V, to fully turn on the MOS transistor. The maximum withstand voltage of the grid electrode and the source electrode of the MOS tube is 20V generally, and the MOS tube can be broken down more than 20 VMOS. Alternatively, the preset withstand voltage of the second transistor 103 may be a breakdown voltage corresponding to a triode. This is by way of example only, and the embodiments of the present application are not limited thereto.

In this embodiment of the present application, the stable voltage of the voltage stabilizing component refers to a voltage value generated at two ends when the voltage stabilizing component passes through the rated current. It should be noted that, when the voltage stabilizing component, such as a voltage stabilizing diode, works in the reverse breakdown region, the current variation range is large, and the voltage variation range is small, the voltage value at this time is the stable voltage of the voltage stabilizing component. One end of the voltage stabilizing component is electrically connected with the control electrode 1031 of the second transistor 103, and the other end of the voltage stabilizing component is electrically connected with the second electrode 1033 of the second transistor 103, when the voltage between the control electrode 1031 of the second transistor 103 and the second electrode 1033 is too large, the voltage stabilizing component breaks down firstly because the stable voltage of the voltage stabilizing component is smaller than the preset withstand voltage value of the second transistor 103, so that the second transistor 103 is protected. The voltage value of the stable voltage may be determined according to the voltage value of the preset withstand voltage value of the second transistor 103, so that the stable voltage is smaller than the preset withstand voltage value. For example, if the preset withstand voltage of the second transistor 103 is 20V, the stabilizing voltage of the stabilizing component may be a voltage value smaller than 20V, for example, 15V. This is by way of example only, and the embodiments of the present application are not limited thereto.

Optionally, the voltage stabilizing component is a voltage stabilizing diode; the cathode of the zener diode is electrically connected to the control electrode 1031 of the second transistor 103, and the anode of the zener diode is electrically connected to the second electrode 1033 of the second transistor 103.

It should be noted that, the basic structure of the zener diode is the same as that of a common diode, and there is a PN junction, so that the PN junction of the zener diode is not damaged when it is in a reverse breakdown state due to different manufacturing processes, and the PN junction of the common diode is damaged, when the zener diode is used for stabilizing the voltage, the breakdown characteristic of the zener diode is utilized, and the current can be changed in a wide range while the voltage is kept unchanged.

For example, the preset withstand voltage of the second transistor 103 may be 20V, the regulated voltage of the zener diode may be 15V, and the zener diode is broken down before exceeding 15V, thereby protecting the second transistor 103. In this way, the lifetime of the second transistor 103 can be increased, thereby increasing the lifetime of the level signal integration conversion circuit.

Optionally, the circuit further comprises: a capacitor assembly; one end of the capacitor element is electrically connected to the control electrode 1031 of the second transistor 103, and the other end of the capacitor element is electrically connected to the second electrode 103 of the second transistor 103.

In this embodiment of the present application, the capacitor component may be a filter capacitor, which is used to protect the second transistor 103 from being broken down by static electricity, so as to improve the service life of the second transistor 103. In some embodiments, a filter capacitor may be connected in parallel to each first transistor 102, so as to protect the first transistor 102 from static breakdown, and improve the service life of the first transistor 102. Thus, the service life of the level signal integration and conversion circuit can be prolonged.

Optionally, the circuit further comprises: a first resistor assembly; one end of the first resistor element is electrically connected to the control electrode 1031 of the second transistor 103, and the other end of the first resistor element is electrically connected to the second electrode 1033 of the second transistor 103.

In an embodiment of the present application, the first resistor component may be at least one resistor. The resistor is used for limiting the current of the branch circuit to prevent the components from being burnt out due to overlarge current. The first resistor element is connected in parallel with the second transistor 103 and may also function to provide a bias voltage, when a high level signal is given to the control electrode 1031 of the second transistor 103, the first resistor element may provide a bias voltage between the control electrode 1031 and the second electrode 1033 of the second transistor 103, so that the second transistor 103 is turned on, and when no high level signal is given to the control electrode 1031 of the second transistor 103, the first resistor element may pull the voltage between the control electrode 1031 and the second electrode 1033 of the second transistor 103 to an equipotential, so that the second transistor 103 is turned off.

Optionally, the circuit further comprises: a plurality of second resistor elements, the number of which is equal to the number of the first transistors 102;

one end of the second resistive element is electrically connected to the control electrode 1031 of the corresponding first transistor 102, and the other end of the second resistive element is electrically connected to the first electrode 1022 of the corresponding first transistor 102.

In this embodiment, the number of the second resistor elements is equal to the number of the first transistors 102, and the second resistor elements are connected to the first transistors 102 in a one-to-one correspondence. The second resistor assembly can comprise at least one resistor, and the resistor is used for limiting the current of the branch circuit so as to prevent the components from being burnt out due to excessive current. In this way, the lifetime of the first transistor 102 may be improved.

Optionally, the circuit further comprises: a plurality of first unidirectional conductive components, the number of first unidirectional conductive components being equal to the number of first transistors 102; the first unidirectional conduction component is arranged between the level signal input end 101 and the corresponding first transistor 102;

one end of the first unidirectional conductive component is electrically connected to the level signal input terminal 101, and the other end of the first unidirectional conductive component is electrically connected to the control electrode 1021 of the corresponding first transistor 102.

In this embodiment, the number of the first unidirectional conductive components is equal to the number of the first transistors 102, and the first unidirectional conductive components are connected in a one-to-one correspondence with the first transistors 102. The first unidirectional conductive component may be connected in series between the level signal input terminal 101 and the corresponding first transistor 102. The first unidirectional conductive component may be a positive conductive component, including a positive terminal and a negative terminal, where the positive terminal of the first unidirectional conductive component is electrically connected to the level signal input terminal 101, and the negative terminal is electrically connected to the control electrode 1021 of the first transistor 102, and the conductive direction of the first unidirectional conductive component is a direction from the level signal input terminal 101 to the corresponding first transistor 102, i.e., a current may flow from the level signal input terminal 101 to the control electrode 1021 of the corresponding first transistor 102, and may intercept a reverse current and a reverse high voltage.

The first unidirectional conductive component may be a diode. When the first transistor 102 is an NMOS transistor, a cathode of the diode is connected to a gate of the NMOS transistor, and an anode of the diode is connected to the level signal input terminal 101, that is, a current is unidirectional in a direction from the level signal input terminal 101 to the first transistor 102, so that a reverse current and a reverse high voltage can be cut off, when the level signal input terminal 101 inputs a high level signal, the current and the voltage can cause the first transistor 102 to be turned on in the past, and when the level signal input terminal 101 inputs a low level signal, the current and the voltage cannot cause the first transistor 102 to be turned off.

In this embodiment, when the first transistor 102 is a PMOS transistor, the anode of the diode is connected to the gate of the PMOS transistor, and the cathode of the diode is connected to the level signal input terminal 101, that is, the current is unidirectional conducted in the direction from the first transistor 102 to the level signal input terminal 101, so that the reverse current and the reverse high voltage can be cut off, when the level signal input terminal 101 inputs a low level signal, the current and the voltage can cause the first transistor 102 to be turned on in the past, and when the level signal input terminal 101 inputs a high level signal, the current and the voltage cannot cause the first transistor 102 to be turned off. In this way, the level signal input through the level signal input terminal 101 can conveniently control the on or off of the corresponding first transistor 102, thereby improving the practicability of the level signal integration conversion circuit.

Optionally, the circuit further comprises: a plurality of second unidirectional conductive components, the number of second unidirectional conductive components being equal to the number of first transistors 102; the second unidirectional-conduction component is disposed between the second transistor 103 and the corresponding first transistor 102;

one end of the second unidirectional conductive component is electrically connected to the second pole 1023 of the first transistor 102, and the other end of the second unidirectional conductive component is electrically connected to the control pole 1021 of the second transistor 103.

In this embodiment, the number of the second unidirectional conductive components is equal to the number of the first transistors 102, and the second unidirectional conductive components are connected in a one-to-one correspondence with the first transistors 102. Wherein the second unidirectional-conduction component may be connected in series between the second transistor 103 and the corresponding first transistor 102. The second unidirectional conductive component may be a positive conductive component including a positive terminal electrically connected to the second electrode 1023 of the first transistor 102 and a negative terminal electrically connected to the control electrode 1021 of the second transistor 103, and the second unidirectional conductive component may be a positive conductive component having a conductive direction from the first transistor 102 to the second transistor 103, i.e., a current may flow from the second electrode 1023 of the first transistor 102 to the control electrode 1021 of the second transistor 103, and may block a reverse current and a reverse high voltage.

The second unidirectional conductive component may be a diode. The anode of the diode is electrically connected to the second pole 1023 of the first transistor 102, the cathode of the diode is electrically connected to the control pole 1021 of the second transistor 103, i.e. the current and voltage are turned on unidirectionally from the direction of the first transistor 102 to the second transistor 103, the reverse current and reverse high voltage can be cut off, when the first transistor 102 is turned on, the current and voltage can pass such that the high level signal of the first power supply terminal 104 can be given to the second transistor 103, and when the first transistor 102 is turned off, the current and voltage cannot pass such that the second transistor 103 is pulled down by the ground terminal, so that the second transistor 103 is turned off. In this way, the second transistor 103 can be conveniently controlled to be turned on or off by the first power supply terminal 104, thereby improving the practicability of the level signal integration conversion circuit.

Optionally, the second transistor 103 is an N-channel MOS transistor.

In the embodiment of the application, the N-channel MOS tube is an NMOS tube, the NMOS tube is effective in high level of the grid, and the high level is generally 5-10V. When each first transistor 102 is turned off, the gate of the NMOS transistor is pulled down by the ground terminal, and the NMOS transistor is turned off, so that the level signal output terminal 107 outputs a high level signal corresponding to the second power supply terminal 105. When any of the first transistors 102 is turned on, the gate of the NMOS transistor is pulled up by the first power supply terminal 104, and the NMOS transistor is turned on, so that the level signal output terminal is turned on with the ground terminal, and a low level signal is output.

Optionally, the plurality of first transistors 102 are all N-channel MOS transistors, or the plurality of first transistors 102 are all P-channel MOS transistors.

In this embodiment, when the plurality of first transistors 102 are all NMOS transistors, under the condition that the low level signals are input to the level signal input terminals 101, the plurality of NMOS transistors are turned off, the gate of the second transistor 103 is pulled down by the ground terminal, and the second transistor 103 is turned off, so that the level signal output terminal 107 outputs the high level signals corresponding to the second power supply terminal 105, thereby implementing the integrated conversion of the plurality of low level signals into one high level signal output. In the case that any level signal input end 101 inputs a high level signal, the NMOS transistor corresponding to the level signal input end 101 is turned on, the gate of the second transistor 103 is pulled up by the first power supply end 103, and the second transistor 103 is turned on, so that the level signal output end is conducted with the ground end, and a low level signal is output, thereby realizing the integrated conversion of a plurality of level signals into one low level signal output.

In this embodiment of the present application, when the plurality of first transistors 102 are PMOS transistors, the plurality of PMOS transistors are turned off under the condition that the high-level signal is input to each level signal input terminal 101, the gate of the second transistor 103 is pulled down by the ground terminal, and the second transistor 103 is turned off, so that the level signal output terminal 107 outputs the high-level signal corresponding to the second power supply terminal 105, thereby implementing the integrated conversion of the plurality of high-level signals into one high-level signal output. In the case that any level signal input end 101 inputs a low level signal, the PMOS transistor corresponding to the level signal input end 101 is turned on, the gate of the second transistor 103 is pulled up by the first power supply end 103, and the second transistor 103 is turned on, so that the level signal output end is conducted with the ground end, and a low level signal is output, thereby realizing the integrated conversion of a plurality of level signals into one low level signal output. Therefore, a user can conveniently select an N-channel MOS tube or a P-channel MOS tube according to the level signal output by the front-stage circuit, and corresponding level integration conversion logic is realized.

In some embodiments, a current limiting resistor may be connected in series between the first unidirectional current conducting component and the first transistor 102, and a current limiting resistor may be connected in series between the first transistor 102 and the second transistor 103, so that the magnitude of the current in the branch circuit may be limited, so as to prevent the components from being burnt out due to excessive current, and thus the service life of the circuit is prolonged.

Fig. 2 is a second circuit structure diagram of the level signal integration and conversion circuit provided in the embodiment of the present application, as shown in fig. 2, the level signal input end of the level signal integration and conversion circuit is electrically connected with the output end CO of the secondary overvoltage protection chip, and is used for performing integration and conversion on level signals output by a plurality of secondary overvoltage chips, so as to obtain level signals required by a later stage circuit. The U1 and the U2 are two-level overvoltage chips, a VC2 terminal of the U1 chip is electrically connected with a 7 th power-saving core in the 5 th-10 th series-connected power-saving core and used for receiving the voltage of the 7 th power-saving core, and a VC2 terminal of the U2 chip is electrically connected with a 2 nd power-saving core in the 1 st-5 th series-connected power-saving core and used for receiving the voltage of the 2 nd power-saving core. Diodes D3 and D4 are first unidirectional conductive components, diodes D1 and D2 are second unidirectional conductive components, and R1-R6 and R13 are resistors. NMOS transistors Q1 and Q2 are first transistors, NMOS transistor Q3 is a second transistor, the grid electrode of Q1 is electrically connected with R3, the drain electrode of Q1 is electrically connected with the VC2 terminal of the U1 chip, the source electrode of Q1 is electrically connected with a resistor R2, the source electrode of Q1 is also electrically connected with one end of a resistor R1, the other end of the resistor R1 is also electrically connected with a resistor R3, and the other end of the resistor R3 is also electrically connected with the cathode of a diode D4. The VC2 terminal of the U1 chip is used as a first power supply end corresponding to the NMOS tube Q1, and the voltage of the 2 nd battery cell is a high-level signal corresponding to the first power supply end. C3 is a filter capacitor, namely a capacitor component, Z1 is a voltage stabilizing tube, namely a voltage stabilizing component, C3, Z1 and R6 are connected in parallel, one end of the voltage stabilizing tube is electrically connected with the cathode of a diode D2, the other end of the voltage stabilizing tube is electrically connected with a grounding end GND, and a power supply VCC is a second power supply end. The connection relation of Q2 is similar to Q1, except that the source of Q2 is electrically connected with the anode of diode D1, because the voltage of the 7 th battery is larger than that of the 2 nd battery, therefore, a resistor is arranged between Q1 and D2 to limit the current and voltage of the branch circuit), the burning of components due to overlarge current is prevented, and Q2 and D1 can be arranged differently. The gate of Q3 is electrically connected to the cathode of the diode D2, the source of Q3 is electrically connected to the ground GND, and the drain of Q3 is electrically connected to the level signal output terminal OUT. For the level signal integration and conversion circuit shown in fig. 2, when the input signal of the CO terminal of each secondary overvoltage protection chip is a low level signal, Q1 and Q2 are turned off, Q3 is turned off, and the level signal output terminal OUT outputs a high level signal, so as to realize integration and conversion of a plurality of low level signals into one high level signal for output. Under the condition that the input signal of the CO terminal of any two-stage overvoltage protection chip is a high-level signal, Q1 or Q2 is turned on, Q3 is turned on, the level signal output end OUT is pulled down, a low-level signal is output, and the integration and conversion of a plurality of level signals into one low-level signal output are realized.

Fig. 3 is a third circuit structure diagram of the level signal integrating and converting circuit provided in the embodiment of the present application, as shown in fig. 3, the difference between fig. 3 and fig. 2 is that the first transistor is a PMOS transistor, that is, Q7 and Q16 are PMOS transistors, and the directions of the first unidirectional conduction components, that is, the diodes D23 and D24 are opposite, where the anode of D24 is electrically connected to the gate of Q7, and the cathode of D24 is electrically connected to the CO terminal of the U5 chip. For the level signal integration and conversion circuit shown in fig. 3, when the input signal of the CO terminal of each secondary overvoltage protection chip is a high level signal, Q7 and Q16 are turned off, Q17 is turned off, and the level signal output terminal OUT outputs a high level signal, so as to realize integration and conversion of a plurality of high level signals into one high level signal for output. Under the condition that the input signal of the CO terminal of any two-stage overvoltage protection chip is a low-level signal, Q7 or Q16 is turned on, then Q17 is turned on, the level signal output end OUT is pulled down, a low-level signal is output, and the integration and conversion of a plurality of level signals into one low-level signal output are realized.

Fig. 4 is a circuit diagram of a level signal integrated switching circuit according to an embodiment of the present application, as shown in fig. 4, the difference between fig. 4 and fig. 2 is that the number of first transistors increases correspondingly, i.e. Q24 in fig. 4, and the number of diodes and current limiting resistors increases correspondingly when the input signal increases to 3.

It should be noted that, the level signal integration and conversion circuit provided in the embodiment of the present application may be applied to a cascade circuit of a secondary overvoltage chip of a battery cell, a chip cascade circuit with different reference voltages, and a circuit in which a plurality of input signals need level integration and conversion.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

The foregoing description of the preferred embodiment of the present utility model is not intended to limit the utility model to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the utility model.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A level signal integration and conversion circuit, comprising: a plurality of level signal input terminals, a plurality of first transistors, a second transistor, a first power supply terminal, a second power supply terminal, a ground terminal, and a level signal output terminal; the number of the first transistors is greater than or equal to the number of the level signal input terminals;

the control electrode of the first transistor is electrically connected with the corresponding level signal input end, the first electrode of the first transistor is electrically connected with the first power supply end, and the second electrode of the first transistor is electrically connected with the control electrode of the second transistor; wherein the control electrode of the second transistor is extremely high in level conduction;

the first pole of the second transistor is electrically connected with the level signal output end, and the second pole of the second transistor is electrically connected with the grounding end;

the level signal output end is electrically connected with the second power supply end.

2. The circuit of claim 1, wherein the circuit further comprises: a voltage stabilizing component; one end of the voltage stabilizing component is electrically connected with the control electrode of the second transistor, and the other end of the voltage stabilizing component is electrically connected with the second electrode of the second transistor; the stable voltage of the voltage stabilizing component is smaller than the preset withstand voltage value of the second transistor.

3. The circuit of claim 2, wherein the voltage stabilizing component is a voltage stabilizing diode; the cathode of the zener diode is electrically connected with the control electrode of the second transistor, and the anode of the zener diode is electrically connected with the second electrode of the second transistor.

4. The circuit of claim 1, wherein the circuit further comprises: a capacitor assembly; one end of the capacitor assembly is electrically connected with the control electrode of the second transistor, and the other end of the capacitor assembly is electrically connected with the second electrode of the second transistor.

5. The circuit of claim 1, wherein the circuit further comprises: a first resistor assembly; one end of the first resistor component is electrically connected with the control electrode of the second transistor, and the other end of the first resistor component is electrically connected with the second electrode of the second transistor.

6. The circuit of claim 1, wherein the circuit further comprises: a plurality of second resistor elements, the number of the second resistor elements being equal to the number of the first transistors;

one end of the second resistor component is electrically connected with the control electrode of the corresponding first transistor, and the other end of the second resistor component is electrically connected with the first electrode of the corresponding first transistor.

7. The circuit of claim 1, wherein the circuit further comprises: a plurality of first unidirectional conductive components, the number of the first unidirectional conductive components being equal to the number of the first transistors; the first unidirectional conduction component is arranged between the level signal input end and the corresponding first transistor;

one end of the first unidirectional conduction component is electrically connected with the level signal input end, and the other end of the first unidirectional conduction component is electrically connected with the corresponding control electrode of the first transistor.

8. The circuit of claim 1, wherein the circuit further comprises: a plurality of second unidirectional conductive components, the number of which is equal to the number of the first transistors; the second unidirectional conduction component is arranged between the second transistor and the corresponding first transistor;

one end of the second unidirectional conduction component is electrically connected with the second electrode of the first transistor, and the other end of the second unidirectional conduction component is electrically connected with the control electrode of the second transistor.

9. The circuit of any of claims 1-8, wherein the second transistor is an N-channel MOS transistor.

10. The circuit of any of claims 1-8, wherein the plurality of first transistors are all N-channel MOS transistors or the plurality of first transistors are all P-channel MOS transistors.