CN220306704U - Packaging structure - Google Patents

Abstract

The application discloses packaging structure, this packaging structure includes: a substrate; a photonic integrated circuit disposed on the substrate and including a first active surface facing the substrate; the electronic integrated circuit is arranged to overlap the photonic integrated circuit in a vertical direction and includes a second active surface facing the substrate. The technical scheme can at least shorten the electrical paths among the photonic integrated circuit, the electronic integrated circuit and the substrate.

Description

Packaging structure

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a packaging structure.

Background

Nowadays, network information demands are improved year by year, cloud services, internet of things, 5G applications and the like are required to be higher and higher in signal data transmission speed. Traditionally, electrical signals are transmitted by cables, and at higher and higher speeds and high frequencies, the Signal Integrity (Signal Integrity) is easily affected by high impedance generated by elements such as capacitors, inductors, etc., so that the transmission distance is limited and power loss is caused. In recent years, optical communication has been gradually transferred from conventional cable transmission to optical communication, and optical fibers have been used between devices to replace copper wires. Silicon photons (Silicon-Photonics) have the advantages of high-speed transmission, low power consumption and the like, so that the application prospect of the Silicon photons (Silicon-Photonics) has great potential, and the Silicon photons (Silicon-Photonics) can be applied to the related fields of optical communication, such as servers, laser radars (Lidar) and the like. However, with the ever-increasing high-speed high-frequency demands, there is also a start of a need to shorten the copper wire transmission distance between elements inside the device to avoid the signal transmission problem at high speed. Also unlike conventional packages, optical packages must consider the coupling light region of the PIC (Photonic Integrated Circuit ) surface that is coupled to the optical fiber, which may be referred to as the optical keep-in region (optical keep out zone, KOZ). For example, the coupling region must not be contaminated by the process flow, and the package design must also take into account the coupling mode that combines the optical path of the waveguide with the fiber base.

Referring to fig. 1A, an optical communication module (or optical engine) 10 is shown to integrate an EIC (Electrical Integrated Circuit, electronic integrated circuit) 22 and a PIC 26 on a substrate 30. In fig. 1A, the light coupling region (not shown) of the surface of PIC 26 is susceptible to contamination by processes such as an underfill (not shown) that encapsulates copper pillars 53 and solder 51 or a reflow (reflow) process that bonds EIC 22. The FAU (Fiber array unit) 40 also requires a suitable support member for the package support.

With continued reference to fig. 1A, the conventional optical communication module 10 uses a Chip-on-Chip (Chip-on-Chip) method, that is, the EIC 22 is connected to the PIC 26 by Flip Chip bonding (Flip Chip Bond), and the active surface 28 of the EIC 22 and the active surface 29 of the PIC 26 are disposed towards each other, so as to greatly shorten the distance between the EIC 22 and the PIC 26. High-speed signals transmitted from the outside may reach EIC 22 through C4 solder balls 32, substrate 30, wire bond 39, a re-wiring layer (not shown) on PIC 26, UBM (under bump metal, under Bump Metallization) 55, solder 51, copper pillars 53, and PIC 26 is driven by EIC 22. However, the connection through wire bond 39 will lengthen the signal path, e.g., wire bond 39 is about 2000 μm long, and there is a significant inductance effect that tends to result in high impedance, affecting signal integrity, and a 100 megabit per second drive may be satisfactory, but can cause significant problems in applications greater than 400 megabits per second.

In addition, the optical signal is transmitted to PIC 26 through FAU 40, then the optical signal is converted into an electrical signal, the electrical signal enters EIC 22, the electrical signal is processed by EIC 22 operation, and the electrical signal is converted into an optical signal through LD (laser Diode) 60 and then transmitted back to PIC 26. Wherein the optical signal prior to entering EIC 22 needs to pass through an optical waveguide greater than about 3000 μm. The electrical signal path P1 is to pass through the copper pillar 53, the solder 51, and the UBM 55, and since the electrical signal is transmitted back and forth, the length of the electrical signal path P1 is about 45 μm+45 μm=90 μm in total.

Referring to another prior art technique shown in fig. 1B, EIC 22 and PIC 26 are disposed side-by-side on substrate 30 with active face 28 of EIC 22 and active face 29 of PIC 26 disposed toward substrate 30. Although the electrical paths between EIC 22 and substrate 30, and between PIC 26 and substrate 30, may be significantly shortened. However, the electrical signal of PIC 26 needs to be routed to the edge of PIC 26 adjacent EIC 22; and, the electrical path P2 between PIC 26 and EIC 22 passes through copper pillar 71, solder 73, UBM 75 under PIC 26 and UBM 76, solder 74, copper pillar 72 under EIC 22, and returns to PIC 26 after processing the electrical signal by EIC 22, which increases the length of electrical path P2 between EIC 22 and PIC 26.

If the electrical paths between EIC 22, PIC 26 and substrate 30 can be shortened, device performance can be improved and heat buildup reduced.

Disclosure of Invention

In view of the above, the present application provides a packaging structure capable of at least shortening an electrical path between a photonic integrated circuit, an electronic integrated circuit and a substrate.

The technical scheme of the application is realized as follows:

according to one aspect of the present application, there is provided a package structure including: a substrate; a photonic integrated circuit disposed on the substrate and including a first active surface facing the substrate; the electronic integrated circuit is arranged to overlap the photonic integrated circuit in a vertical direction and includes a second active surface facing the substrate.

In some embodiments, the electronic integrated circuit is embedded in the photonic integrated circuit.

In some embodiments, the package structure further includes a redistribution layer connecting the first active surface and the second active surface.

In some embodiments, the photonic integrated circuit further comprises a first side connected to the first active surface, wherein the package structure further comprises an optical fiber array unit disposed on the first side of the photonic integrated circuit, and a waveguide disposed on the first active surface and optically connected to the optical fiber array unit.

In some embodiments, the package structure further includes a light emitting element optically connected to the optical fiber array unit.

In some embodiments, the light emitting element is embedded in a photonic integrated circuit.

In some embodiments, the photonic integrated circuit further comprises a first inactive face opposite the first active face, wherein the package structure further comprises an optical fiber array unit disposed at the first inactive face of the photonic integrated circuit, and a first optical through-silicon via extending through the photonic integrated circuit and optically connecting the optical fiber array unit.

In some embodiments, the package structure further includes a light emitting element optically connected to the fiber array unit, and a second optical through-silicon via penetrating the photonic integrated circuit and optically connected to the light emitting element.

In some embodiments, the light emitting element is disposed at a first passive face of the photonic integrated circuit.

In some embodiments, the light emitting element is disposed on the substrate.

In the above-described package structure, the first active surface of the photonic integrated circuit and the second active surface of the electronic integrated circuit are both disposed toward the substrate, so that the electrical signal paths between the photonic integrated circuit and the substrate and between the electronic integrated circuit and the substrate can be shortened. In addition, by overlapping the electronic integrated circuit and the photonic integrated circuit along the Z direction, the first active surface of the photonic integrated circuit and the second active surface of the electronic integrated circuit may be laterally adjacent, so that an electrical signal path between the electronic integrated circuit and the photonic integrated circuit may be transferred across the electronic integrated circuit and the photonic integrated circuit without passing through the intervals between the photonic integrated circuit and the substrate and between the electronic integrated circuit and the substrate, and the electrical signal path between the electronic integrated circuit and the photonic integrated circuit may be shortened, improving the element performance and reducing the heat accumulation.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1A and 1B are side views of a prior art integrated electronic and photonic integrated circuits on a substrate in different ways, respectively.

Fig. 2A and 2B are side and top views, respectively, of a package structure according to one embodiment of the present application.

Fig. 3A and 3B are side and top views, respectively, of a package structure according to another embodiment of the present application.

Fig. 4A and 4B are side and top views, respectively, of a package structure according to another embodiment of the present application.

Fig. 5A-5F are side views of the package structure of fig. 2A at various stages of formation.

Fig. 6 is a side view schematic diagram of a package structure according to another embodiment of the present application.

Fig. 7A and 7B are side and top views, respectively, of a package structure according to another embodiment of the present application.

Fig. 8A and 8B are side and top views, respectively, of a package structure according to another embodiment of the present application.

Fig. 9A and 9B are side and top views, respectively, of a package structure according to another embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of the protection of the present application.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the utility model. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. It should be understood that the same reference numerals may be used to identify the same components in the following description.

Fig. 2A is a side view schematic diagram of a package structure 100 according to an embodiment of the present application. Referring to fig. 2A, the package structure 100 includes a substrate 110, and a PIC (Photonic Integrated Circuit ) 120 disposed on the substrate 110. The PIC 120 includes a first active face 123, the first active face 123 facing the substrate 110. The package structure 100 further includes an EIC (Electrical Integrated Circuit, electronic integrated circuit) 140. The EIC 140 includes a second active face 143, the second active face 143 facing the substrate 110.EIC 140 is disposed overlapping PIC 120 in the Z-direction (i.e., vertical direction), with a portion of PIC 120 being located above EIC 140.

In the package structure 100, by providing the first active surface 123 of the PIC 120 and the second active surface 143 of the EIC 140 toward the substrate 110, the electrical signal paths between the PIC 120 and the substrate 110 and between the EIC 140 and the substrate 110 can be shortened. In addition, by overlapping EIC 140 and PIC 120 in the Z-direction such that first active face 123 of PIC 120 and second active face 143 of EIC 140 may be laterally adjacent, electrical signal path P3 between EIC 140 and PIC 120 may be transferred laterally across first active face 123 of PIC 120 and second active face 143 of EIC 140 without requiring electrical connections (e.g., copper pillars 71, solder 73, UBM 75, and copper pillars 72, solder 74, UBM 76, shown in fig. 1B) between PIC 120 and substrate 110 and between EIC 140 and substrate 110. Since the electrical signal path between PIC 120 and substrate 110, the electrical signal path between EIC 140 and substrate 110, and electrical signal path P3 between EIC 140 and PIC 120 are shortened, device performance can be improved and heat accumulation can be reduced.

With continued reference to fig. 2A, EIC 140 is embedded within PIC 120.PIC 120 may have a first cavity 160 recessed from first active face 123 to accommodate EIC 140. The first cavity 160 has a surface 162 recessed relative to the first active surface 123, and a sidewall 164 connecting the surface 162 and the first active surface 123. In this embodiment, a space 502 is provided between the sidewall 164 of the first cavity 160 and the side of the EIC 140, and the surface 162 of the first cavity 160 contacts a second passive surface 145 of the EIC 140 opposite to the second active surface 143.

In some embodiments, the first active surface 123 and the second active surface 143 may be substantially coplanar along the lateral direction, i.e., the first active surface 123 and the second active surface 143 are substantially at the same horizontal position. Package structure 100 may further include a redistribution layer 180, and redistribution layer 180 may connect first active face 123 of PIC 120 with second active face 143 of EIC 140. The redistribution layer 180 may cover the second active face 143 of the EIC 140, and may extend laterally beyond the second active face 143 of the EIC 140 onto the first active face 123 of the PIC 120. The redistribution layer 180 may be connected to the substrate 110 by solder 185. By orienting both the first active face 123 of the PIC 120 and the second active face 143 of the EIC 140 towards the substrate 110 and providing the redistribution layer 180, electrical signals between the PIC 120 and the EIC 140 may be transmitted via the redistribution layer 180. By embedding EIC 140 in PIC 120 and electrically connecting EIC 140 to PIC 120 with redistribution layer 180, the electrical signals of PIC 120 need not be routed to the edge of PIC 120 (as described with respect to fig. 1B), but rather EIC 140 can be accessed from the middle region of PIC 120 via redistribution layer 180, and substrate 110 can be directly electrically connected to EIC 140 and PIC 120 via solder 185 and redistribution layer 180 for power. In some embodiments, transmitters for transmitting electrical signals and receivers for receiving electrical signals may be designed in the surrounding area of EIC 140, while intermediate areas of EIC 140 may be designed with other circuitry, for example, circuitry in the intermediate areas may be connected to substrate 110 via redistribution layer 180 and solder 185 to obtain power from substrate 110.

More specifically, the electrical signal path P3 between the PIC 120 and the EIC 140 extends vertically downward from the first active surface 123 in the middle region of the PIC 120 into the redistribution layer 180, then extends laterally through the redistribution layer 180 to below the EIC 140, and then extends vertically upward to the second active surface 143 of the EIC 140 to enter the EIC 140. Such an electrical signal path P3 has a shorter length. By replacing the conventional electrical connection between EIC 140 and PIC 120 with copper pillars and solder with redistribution layer 180, the length of electrical signal path P3 can be significantly reduced compared to the conventional electrical signal path (e.g., electrical signal path P1 in fig. 1A) that has to pass through copper pillars, solder, UBM (e.g., solder 51, copper pillars 53, and UBM 55 between EIC 140 and PIC 120 in fig. 1A). For example, the electrical signal path P3 length traveling back and forth may be shortened from 90 μm (as described with respect to FIG. 1A) to less than 20 μm, by approximately a 4-fold reduction in electrical signal path length. And in addition to being able to shorten the electrical signal path P3, the package structure 100 can also be reduced in volume.

PIC 120 also includes a first side 121 that connects to first active surface 123. The package structure 100 further includes a FAU 170 (Fiber array unit) disposed on the first side 121 of the PIC 120. A waveguide 191 optically connected to the FAU 170 is provided at the first active face 123 of the PIC 120. The package structure 100 further includes a light emitting element 175 optically connected to the FAU 170. In some embodiments, the light emitting element 175 is a Laser Diode (LD).

In some embodiments, light emitting element 175 is embedded within PIC 120. The PIC 120 may have a second cavity 165 recessed from the first active surface 123 to accommodate the light emitting element 175. The second cavity 165 has a surface 166 recessed relative to the first active face 123, and a sidewall 168 connecting the surface 166 and the first active face 123. In this embodiment, the sidewall 168 of the second cavity 165 has a space 504 between the light emitting element 175 and the surface 166 of the second cavity 165 is in contact with the light emitting element 175.

In the package structure 100, the optical signal is transmitted to the PIC 120 through the FAU 170, then the optical signal is converted into an electrical signal, the electrical signal enters the EIC 140 through the electrical signal path P3, the optical signal before entering the EIC 140 is subjected to the operation processing of the EIC 140 by the optical waveguide 191, and then the optical signal output by the EIC 140 is used to control the light emitting element 175 to emit the optical signal corresponding to the electrical signal, and such optical signal is transmitted back to the PIC 120 and the FAU 170. Waveguide 191 for transmission from FAU 170 to EIC 140 may cross over light emitting element 175 below light emitting element 175 without the need for routing wires away from light emitting element 175 resulting in an elongated optical signal path.

PIC 120 also includes a first passive face 125 opposite first active face 123. The package structure 100 further includes a support 190 disposed on the first passive side 125 of the PIC 120. Support 190 includes a second side 192 adjacent to first side 121 of PIC 120. In some embodiments, second side 192 is substantially coplanar with first side 121 along the Z-direction. The FAU 170 is disposed on the first side 121 of the PIC 120 and the second side 192 of the support 190. In some embodiments, the support 190 may be formed of a dummy wafer (dummy wafer) or a dummy die (dummy die).

In some embodiments, the thickness of the FAU 170 in the Z-direction is greater than the thickness of the PIC 120. The upper surface of the FAU 170 may be higher than the first passive face 125 of the PIC 120 in the Z-direction. The upper surface of the FAU 170 may be lower than the upper surface of the support 190. In some embodiments, the thickness of the PIC 120 may be in the range of 200 μm to 300 μm. By providing the support 190 on the first passive face 125 of the PIC 120, the FAU 170 may be supported for improved structural strength. In some embodiments, a lower surface of the FAU 170 may be non-coplanar with the first active face 123 of the PIC 120, e.g., as shown in fig. 1A, the lower surface of the FAU 170 may be lower than the first active face 123. In other embodiments, the lower surface of the FAU 170 may also be higher than the first active surface 123.

Fig. 2B is a schematic top view of the package structure 100 according to an embodiment of the present application. As shown in fig. 2B, PIC 120 is disposed on substrate 110, EIC 140, light emitting element 175 are embedded in PIC 120, FAU 170 is disposed at first side 121 of PIC 120, and light emitting element 175 is located between FAU 170 and EIC 140. The PIC 120 is provided with a support 190.

Fig. 3A and 3B are side and top views, respectively, of a package structure 200 according to another embodiment of the present application. The package structure 200 shown in fig. 3A and 3B is identical in many respects to the package structure 100 described above with reference to fig. 2A and 2B, except that in the package structure 200 shown in fig. 3A and 3B, the EIC 140 is located between the FAU 170 and the light emitting element 175. Similar to the description above with reference to fig. 2A and 2B, referring to fig. 3A, by directing both the first active face 123 of the PIC 120 and the second active face 143 of the EIC 140 toward the substrate 110, electrical signals may be transmitted between the PIC 120 and the EIC 140 via the redistribution layer 180, which may reduce the length of electrical signal paths, for example, by a factor of about 4 (less than 20 μm), and may also reduce the volume of the package structure 200. Since the EIC 140 is embedded in the PIC 120, a transmitter for transmitting an electrical signal and a receiver for receiving an electrical signal may be designed in a peripheral region of the EIC 140, and other circuits may be designed in a middle region of the EIC 140, and the circuits in the middle region may be directly connected to the substrate 110 to obtain power from the substrate 110.

As shown in the top views of fig. 2B and 3B, EIC 140 and light emitting element 175 are disposed side-by-side in a direction perpendicular to first side 121 of PIC 120. In other embodiments, the EIC 140 and light emitting element 175 embedded within the PIC 120 may also be configured in other suitable top-down layouts. Fig. 4A and 4B are side and top views, respectively, of a package structure 300 according to another embodiment of the present application. Referring to fig. 4A and 4B, EIC 140 and light emitting element 175 may be disposed side-by-side in a direction parallel to first side 121 of PIC 120. The planar layout design of EIC 140 and light emitting element 175 embedded in PIC 120 is not limited in this application.

Fig. 5A-5F are side views of the package structure 100 shown in fig. 2A at various stages of formation. Referring first to fig. 5A, EIC 140 is provided. Referring to fig. 5B, a plurality of conductive pillars 149, e.g., copper pillars, are formed on the second active surface 143 of the EIC 140. In some embodiments, the plurality of conductive posts 149 may be formed by an electroplating process.

As shown with reference to fig. 5C, a PIC 120 is provided. Then, a polishing process (polishing) may be performed on the PIC 120 to thin the thickness of the PIC 120. By reducing the thickness of the PIC 120, the heat dissipation efficiency may be improved.

Subsequently, as shown with reference to fig. 5D, the first active face 123 of the PIC 120 is placed facing upward, and two separate first and second cavities 160 and 165 recessed to the first active face 123 are formed in the PIC 120. In some embodiments, the first and second cavities 160 and 165 may be formed through a dry etching process. The first cavity 160 includes a surface 162 recessed with respect to the first active surface 123, and a sidewall 164 connecting the surface 162 and the first active surface 123. The second cavity 165 includes a surface 166 recessed relative to the first active surface 123, and a sidewall 168 connecting the surface 166 and the first active surface 123. The dimensions of the first and second cavities 160, 165 may be different, for example, at least one of the length, width, or depth of the first and second cavities 160, 165 may be different, depending on the dimensions of the EIC 140 and light emitting element 175 to be received by the first and second cavities 160, 165.

Referring to fig. 5E, EIC 140 and light emitting element 175 are attached into first cavity 160 and second cavity 165, respectively. In some embodiments, after the EIC 140 is attached, the EIC 140 is in contact with the surface 162 of the first cavity 160, with a space 502 between the EIC 140 and the sidewall 164 of the first cavity 160. In some embodiments, after attaching the light emitting element 175, the light emitting element 175 is in contact with the surface 166 of the second cavity 165, with the space 504 between the light emitting element 175 and the sidewall 168 of the second cavity 165.

In some embodiments, after the EIC 140 is attached into the first cavity 160, a polishing process may be performed to remove a portion of the conductive pillars 149 (see fig. 5B) so that the conductive pillars 149 have an appropriate height to electrically connect with subsequently formed re-wiring layers 180. Subsequently, a re-routing layer 180 is formed over EIC 140 and a portion of PIC 120 adjacent to EIC 140. The redistribution layer 180 may span the gap 502. In addition, a waveguide 191 is formed on a region of the PIC 120 where the rewiring layer 180 is not provided, and the waveguide 191 may span the light emitting element 175.

Referring to fig. 5F, the redistribution layer 180 is bonded to the substrate 110 through solder 185 to bond the structure formed in fig. 5E to the substrate 110. The FAU 170 may then be assembled to the first side 121 of the PIC 120 adjacent to the light emitting element 175 and a support 190 formed on the first passive side 125 of the PIC 120 to support the FAU 170. Finally, the package structure 100 is obtained.

Fig. 6 is a side view schematic diagram of a package structure 400 according to another embodiment of the present application. The package structure 400 shown in fig. 6 is identical in many respects to the package structure 100 described above with reference to fig. 2A and 2B, and only the differences of the package structure 400 shown in fig. 6 are described below. In the embodiment shown in fig. 6, the space 502 extends further between the second passive face 145 of the EIC 140 and the surface 162 of the first cavity 160 from between the sidewall 164 of the first cavity 160 and the EIC 140, and the space 502 is filled with a gel 610. Since the EIC 140 is placed in the preformed first cavity 160 (see fig. 5D), there may be a problem in that the thickness of the EIC 140 does not match the depth of the corresponding first cavity 160. Thus, by filling the gel 610 between the second passive face 145 of the EIC 140 and the surface 162 of the first cavity 160, a mismatch in the thickness of the EIC 140 and the depth of the corresponding first cavity 160 can be compensated for.

Similarly, the space 504 extends further between the light emitting element 175 and the surface 166 of the second cavity 165 from between the side wall 168 of the second cavity 165 and the light emitting element 175, and the space 504 is filled with a gel 610. By filling the gel 610 between the light emitting element 175 and the surface 166 of the second cavity 165, a mismatch of the thickness of the light emitting element 175 and the depth of the corresponding second cavity 165 can be compensated.

In addition, the space between the side of the EIC 140 and the sidewall 164 of the first cavity 160 is also filled with the gel 610. In some embodiments, the gel 610 is a heat-dissipating gel. If the space 502 between the side of the EIC 140 and the sidewall 164 of the first cavity 160 is not provided with the gel 610, heat may be accumulated at the side of the EIC 140. By filling the glue 610 between the side surface of the EIC 140 and the sidewall 164 of the first cavity 160, the heat dissipation performance of the EIC 140 can be improved. Similarly, the space between the side surface of the light emitting element 175 and the side wall 168 of the second cavity 165 is filled with the glue 610, so as to enhance the heat dissipation efficiency of the light emitting element 175. In some other embodiments, the glue 610 may be filled between the second passive face 145 and the surface 162 of the EIC 140, and the glue 610 may not be filled between the side of the EIC 140 and the sidewall 164. In some other embodiments, the glue 610 may be filled between the light emitting element 175 and the surface 166, and the glue 610 may not be filled between the side of the light emitting element 175 and the sidewall 168.

Fig. 7A is a side view schematic diagram of a package structure 500 according to another embodiment of the present application. Referring to fig. 7A, the FAU 170 is disposed on the first passive side 125 of the PIC 120. The light emitting element 175 is also disposed on the first passive face 125 of the PIC 120. In this embodiment, where the FAU 170 is disposed at the first passive face 125 of the PIC 120, the support 190 described above may be omitted. Fig. 7B is a schematic top view of a package structure 500 according to another embodiment of the present application. As shown in the top view of fig. 7B, light emitting element 175 is located between EIC 140 and FAU 170.

Referring again to fig. 7A, the package structure 500 includes a first optical TSV 522 (through-silicon via, through Silicon Via) 522 and a second optical TSV 524 that extend through the PIC 120. The first optical TSV 522 may be disposed under the FAU 170 and optically connect the FAU 170. Waveguide 191 is disposed at first active face 123 of PIC 120. In some embodiments, waveguide 191 may optically connect FAU 170 through first optical TSV 522. The second optical TSV 524 may be disposed under the light emitting element 175 and optically connected to the light emitting element 175. The first and second optical TSVs 522 and 524 may be disposed at the same side of the EIC 140. In some implementationsIn an embodiment, the material of waveguide 191 may be a high refractive index material, such as a Polymer (Polymer). In some embodiments, the material of the first and second optical TSVs 522, 524 may be a high refractive index material, such as a polymer, tiO ₂ 。

By providing the first and second optical TSVs 522 and 524 in the PIC 120, an optical signal may be transmitted from the FAU 170 located at the first passive side 125 of the PIC 120 to the first active side 123 of the PIC 120 through the first optical TSV 522, then the optical signal may pass through the waveguide 191, after which the optical signal is converted into an electrical signal, which enters the EIC 140 via the redistribution layer 180 (e.g., through the electrical signal path P3 similar to that described with reference to fig. 2A), after the EIC 140 arithmetic processing, the output electrical signal controls the light emitting element 175 to generate a corresponding optical signal, and the optical signal emitted by the light emitting element 175 located at the first passive side 125 is transmitted to the first active side 123 of the PIC 120 through the second optical TSV 524.

Fig. 8A is a side view schematic diagram of a package structure 600 according to another embodiment of the present application. Fig. 8B is a schematic top view of a package structure 600 according to another embodiment of the present application. Referring to fig. 8A and 8B, the FAU 170 is disposed on the first passive side 125 of the PIC 120. The light emitting element 175 is disposed on the surface 113 of the substrate 110 to which the redistribution layer 180 is bonded.

Referring to fig. 8A, package structure 600 includes a first optical TSV 522 that extends through PIC 120. The first optical TSV 522 is disposed below the FAU 170 and optically connects the FAU 170. Waveguide 191 is disposed at first active face 123 of PIC 120. A waveguide 196 is provided at the surface 113 of the substrate 110 that optically connects the light emitting element 175, the waveguide 196 extending below the first active face 123 of the PIC 120 and being connected to the first active face 123 of the PIC 120 through a vertically extending waveguide 198. In some embodiments, the materials of waveguide 191, waveguide 196, waveguide 198 may be high refractive index materials, such as polymers, tiO ₂ 。

In this embodiment, an optical signal may be transmitted from the FAU 170 located on the first passive surface 125 of the PIC 120 to the first active surface 123 of the PIC 120 through the first optical TSV 522, then the optical signal may pass through the optical waveguide 191, then the optical signal may be converted into an electrical signal, and the electrical signal enters the EIC 140 through the redistribution layer 180 (for example, through the electrical signal path P3 similar to that described with reference to fig. 2A), and after the EIC 140 performs an arithmetic processing, the output electrical signal controls the light emitting element 175 to generate a corresponding optical signal, and the optical signal emitted by the light emitting element 175 located on the substrate 110 is transmitted to the first active surface 123 of the PIC 120 through the waveguide 196 on the substrate 110 and the waveguide 198 between the PIC 120 and the substrate 110.

Fig. 9A is a side view schematic diagram of a package structure 700 according to another embodiment of the present application. Referring to fig. 9A, the FAU 170 and the light emitting element 175 are disposed on the first passive side 125 of the PIC 120. FAU 170 and light emitting element 175 may be located over opposite sides of EIC 140. Fig. 9B is a schematic top view of a package structure 700 according to another embodiment of the present application. As shown in the top view of FIG. 9B, EIC 140 is positioned between light emitting element 175 and FAU 170.

Referring again to fig. 9A, the package structure 700 includes a first optical TSV 522 and a second optical TSV 524 that extend through the PIC 120. The first optical TSV 522 is disposed below the FAU 170 and optically connects the FAU 170. The second optical TSV 524 may be disposed under the light emitting element 175 and optically connected to the light emitting element 175. The first and second optical TSVs 522 and 524 may be disposed at opposite sides of the EIC 140. A waveguide 191 optically connected to the FAU 170 and a waveguide 199 optically connected to the light emitting element 175 may be provided at the first active face 123 of the PIC 120.

In this embodiment, by providing the first optical TSV 522 and the second optical TSV 524 in the PIC 120, an optical signal may be transmitted from the FAU 170 located on the first passive side 125 of the PIC 120 to the first active side 123 of the PIC 120 through the first optical TSV 522, then the optical signal may pass through the waveguide 191, after which the optical signal is converted into an electrical signal by the redistribution layer 180 into the EIC 140 (e.g., through the electrical signal path P3 similar to that described with reference to fig. 2A), the electrical signal output by the EIC 140 controls the light emitting element 175 to generate a corresponding optical signal, and the optical signal emitted by the light emitting element 175 located on the passive side is transmitted to the waveguide 199 of the first active side 123 of the PIC 120 through the second optical TSV 524 to be transmitted back to the PIC 120.

In addition, in the package structures 500, 600, 700 shown in fig. 7A, 8A, and 9A, in some embodiments, the glue 610 may be filled between the second passive surface 145 of the EIC 140 and the surface 162 of the first cavity 160 (as described with reference to fig. 6), and/or the glue 610 may be filled between the side of the EIC 140 and the sidewall 164 of the first cavity 160 (as described with reference to fig. 6).

As used herein, the terms "substantial", "about" are used to indicate and explain minor variations. For example, when used in connection with a numerical value, the above terms may refer to a range of variation of less than or equal to the corresponding numerical value ± 10%. The terms "substantially coplanar", "substantially flush" may refer to two surfaces lying within ±50 μm along the same plane (such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane).

The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover any and all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.

Claims (10)

1. A package structure, comprising:

a substrate;

a photonic integrated circuit disposed on the substrate and including a first active face facing the substrate;

an electronic integrated circuit is arranged to overlap the photonic integrated circuit in a vertical direction and includes a second active surface facing the substrate.

2. The package structure of claim 1, wherein the electronic integrated circuit is embedded within the photonic integrated circuit.

3. The package structure of claim 1, further comprising a redistribution layer connecting the first active face and the second active face.

4. The package structure of claim 1, wherein the photonic integrated circuit further comprises a first side connected to the first active surface, wherein the package structure further comprises an optical fiber array unit disposed on the first side of the photonic integrated circuit, and a waveguide disposed on the first active surface and optically connected to the optical fiber array unit.

5. The package structure of claim 4, further comprising a light emitting element optically connected to the fiber array unit.

6. The package structure of claim 5, wherein the light emitting element is embedded in the photonic integrated circuit.

7. The package structure of claim 1, wherein the photonic integrated circuit further comprises a first inactive face opposite the first active face, wherein the package structure further comprises an optical fiber array unit disposed at the first inactive face of the photonic integrated circuit, and a first optical through-silicon via extending through the photonic integrated circuit and optically connecting the optical fiber array unit.

8. The package structure of claim 7, further comprising a light emitting element optically connected to the fiber array unit, and a second optical through-silicon via extending through the photonic integrated circuit and optically connected to the light emitting element.

9. The package structure of claim 8, wherein the light emitting element is disposed on the first passive side of the photonic integrated circuit.

10. The package structure according to claim 8, wherein the light emitting element is provided over the substrate.