CN220208979U - Gate line electrode of heterojunction solar cell - Google Patents
Gate line electrode of heterojunction solar cell Download PDFInfo
- Publication number
- CN220208979U CN220208979U CN202321658175.2U CN202321658175U CN220208979U CN 220208979 U CN220208979 U CN 220208979U CN 202321658175 U CN202321658175 U CN 202321658175U CN 220208979 U CN220208979 U CN 220208979U
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- CN
- China
- Prior art keywords
- layer
- conductive film
- solar cell
- line electrode
- silicon wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 230000004913 activation Effects 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 15
- 230000008569 process Effects 0.000 abstract description 13
- 238000007747 plating Methods 0.000 abstract description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 238000001039 wet etching Methods 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 4
- 238000005240 physical vapour deposition Methods 0.000 abstract description 3
- 229910052763 palladium Inorganic materials 0.000 abstract description 2
- 230000009467 reduction Effects 0.000 abstract description 2
- 230000003213 activating effect Effects 0.000 description 5
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- MUJIDPITZJWBSW-UHFFFAOYSA-N palladium(2+) Chemical compound [Pd+2] MUJIDPITZJWBSW-UHFFFAOYSA-N 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- AFVFQIVMOAPDHO-UHFFFAOYSA-N Methanesulfonic acid Chemical compound CS(O)(=O)=O AFVFQIVMOAPDHO-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- LNOPIUAQISRISI-UHFFFAOYSA-N n'-hydroxy-2-propan-2-ylsulfonylethanimidamide Chemical compound CC(C)S(=O)(=O)CC(N)=NO LNOPIUAQISRISI-UHFFFAOYSA-N 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The utility model discloses a gate line electrode of a heterojunction solar cell, which comprises a silicon wafer, wherein a conductive film layer and a circuit pattern are sequentially formed on the surface of the silicon wafer, and the circuit pattern comprises an activation layer, a metal nickel layer and a conductive material layer which are sequentially formed on the conductive film layer. According to the method, the metal palladium is used for forming the activation layer on the conductive film layer, and patterning is carried out on the activation layer through a dry film or wet film process, so that the seed layer selectively grows on the grid line position of the grid line electrode on the silicon wafer through a chemical plating process, the PVD sputtering seed layer process and the wet etching seed layer process are not required to be additionally introduced, equipment investment is reduced, and meanwhile, the reduction of battery efficiency caused by damage to the conductive film layer due to the full-area sputtering seed layer and the wet etching seed layer is avoided.
Description
Technical Field
The present application relates to printed circuits; a housing or structural component of an electrical device; the technical field of manufacturing of electric element assemblies, in particular to a grid line electrode of a heterojunction solar cell.
Background
At present, the grid electrode process mainly comprises the steps of depositing a conductive seed layer on the ITO surface of a battery, patterning by using a dry film or wet film mode, electroplating copper and tin in a patterned area, and finally stripping a mask material and etching the seed layer. The problem with this solution is that it requires additional PVD sputtering chambers and wet etching equipment, not only increasing equipment investment costs, but also the full area sputtering and wet etching have some damage to the ITO surface, resulting in a loss of cell efficiency.
Disclosure of Invention
The present utility model aims to solve at least one of the technical problems existing in the prior art. Therefore, the utility model provides a gate line electrode of a heterojunction solar cell, which adopts the following technical scheme:
the gate line electrode of the heterojunction solar cell comprises a silicon wafer, wherein a conductive film layer and a circuit pattern are sequentially formed on the surface of the silicon wafer, and the circuit pattern comprises an activation layer, a metal nickel layer and a conductive material layer which are sequentially formed on the conductive film layer.
The technical scheme adopted by the embodiment of the utility model for solving the technical problems is as follows: the conductive film layer is one of ITO, IWO, AZO.
The technical scheme adopted by the embodiment of the utility model for solving the technical problems is as follows: the thickness of the conductive film layer is 50-150nm.
The technical scheme adopted by the embodiment of the utility model for solving the technical problems is as follows: the thickness of the metallic nickel layer is 100-200nm.
The technical scheme adopted by the embodiment of the utility model for solving the technical problems is as follows: the material of the conductive material layer is metallic copper or metallic tin, and the thickness of the conductive material layer is 5-15um.
The technical scheme adopted by the embodiment of the utility model for solving the technical problems is as follows: the light incident surface and the back surface of the silicon wafer are respectively provided with the conductive film layers, and each conductive film layer is respectively provided with the circuit pattern.
The utility model has the beneficial effects that:
according to the method, the metal palladium is used for forming the activation layer on the conductive film layer, and patterning is carried out on the activation layer through a dry film or wet film process, so that the seed layer selectively grows on the grid line position of the grid line electrode on the silicon wafer through a chemical plating process, the PVD sputtering seed layer process and the wet etching seed layer process are not required to be additionally introduced, equipment investment is reduced, and meanwhile, the reduction of battery efficiency caused by damage to the conductive film layer due to the full-area sputtering seed layer and the wet etching seed layer is avoided.
Drawings
The foregoing and/or additional aspects and advantages of the utility model will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a gate line electrode of a heterojunction solar cell according to an embodiment of the disclosure;
fig. 2 is a schematic diagram of a process flow for preparing a gate electrode of a heterojunction solar cell according to an embodiment of the application.
Detailed Description
Reference will now be made in detail to the present embodiments of the present utility model, examples of which are illustrated in the accompanying drawings, wherein the accompanying drawings are used to supplement the description of the written description so that one can intuitively and intuitively understand each technical feature and overall technical scheme of the present utility model, but not to limit the scope of the present utility model.
In the description of the present utility model, plural means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and the above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present utility model, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present utility model and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present utility model.
In the present utility model, unless clearly defined otherwise, the terms "disposed," "mounted," "connected," and the like are to be construed broadly and may be connected directly or indirectly through an intermediary; the connecting device can be fixedly connected, detachably connected and integrally formed; may be a mechanical connection; may be a communication between two elements or an interaction between two elements. The specific meaning of the words in the utility model can be reasonably determined by a person skilled in the art in combination with the specific content of the technical solution.
Referring to fig. 1-2, an embodiment of the present application is provided, which includes a silicon wafer 1, a conductive film layer 2 and a circuit pattern are sequentially formed on the surface of the silicon wafer 1, and the circuit pattern includes an activation layer 3, a metal nickel layer 4 and a conductive material layer 5 sequentially formed on the conductive film layer 2.
When the light incident surface of the silicon wafer 1 is an N surface, the backlight surface of the silicon wafer is a P surface; when the light incident surface of the silicon wafer 1 is the P surface, the back surface is the N surface.
In this embodiment, the light incident surface and the backlight surface of the silicon wafer 1 are respectively deposited with a transparent conductive film layer 2, the material of the conductive film layer 2 is one of ITO, IWO, AZO, and the thickness of the conductive film layer 2 is 50-150nm.
The silicon wafer 1 with the conductive film layer 2 deposited on the light incident surface and the backlight surface is activated by adopting an activating solution to form an activating layer, the activating solution is a metal palladium ion solution, the palladium ion concentration is 50-300ppm, the duration of the activating treatment of the light incident surface and the backlight surface of the silicon wafer 1 is 1-5min, and the activating layer 3 is formed on the conductive film layer 2 after the silicon wafer is cleaned by pure water and dried.
Patterning is carried out on the active layer 3 by adopting a dry film process or a wet film process, and a circuit pattern area and a non-circuit pattern area corresponding to the grid line electrode are formed on the active layer 3, so that a mask material layer is formed on the active layer 3 of the non-circuit pattern area;
carrying out chemical nickel plating on the activation layer 3 of the circuit pattern area, wherein the specific process is that a chemical nickel solution with pH of 7, phosphorus content of 1-4wt% and temperature of 50-80 ℃ is adopted to deposit metallic nickel on the surface of the activation layer 3 of the circuit pattern area, the treatment time of chemical nickel plating is 10-15min, and the metallic nickel layer 4 with thickness of 100-200nm is obtained;
then adopting an electroplating mode to carry out copper plating or tin plating on the surface of the metallic nickel layer 4 to form a conductive material layer 5, wherein the thickness of the conductive material layer 5 is 5-15 mu m, and a copper plating solution is a copper sulfate solution system; the tinning solution is one of sulfamic acid system, methylsulfonic acid system and sulfuric acid system;
and (3) performing film stripping treatment on the mask material layer in the non-circuit pattern area by adopting a film stripping solution, wherein the film stripping solution is one of sodium hydroxide or potassium hydroxide, the temperature of the film stripping solution is controlled to be 30-45 ℃, the film stripping time is controlled to be 0.5-2min, and the mask material layer in the non-circuit pattern area is removed to obtain the gate line electrode.
Of course, the present utility model is not limited to the above-described embodiments, and those skilled in the art can make equivalent modifications or substitutions without departing from the spirit of the present utility model, and these equivalent modifications and substitutions are included in the scope of the present utility model as defined in the appended claims.
Claims (6)
1. The heterojunction solar cell gate electrode is characterized by comprising a silicon wafer (1), wherein a conductive film layer (2) and a circuit pattern are sequentially formed on the surface of the silicon wafer (1), and the circuit pattern comprises an activation layer (3), a metal nickel layer (4) and a conductive material layer (5) which are sequentially formed on the conductive film layer (2).
2. The gate line electrode of a heterojunction solar cell as claimed in claim 1, wherein the conductive film layer (2) is one of ITO, IWO, AZO.
3. The gate line electrode of a heterojunction solar cell as claimed in claim 2, wherein the thickness of the conductive film layer (2) is 50-150nm.
4. The gate line electrode of a heterojunction solar cell according to claim 1, characterized in that the thickness of the metallic nickel layer (4) is 100-200nm.
5. The gate line electrode of a heterojunction solar cell according to claim 1, characterized in that the material of the conductive material layer (5) is metallic copper or metallic tin, and the thickness of the conductive material layer (5) is 5-15um.
6. The gate line electrode of the heterojunction solar cell according to claim 1, wherein the light incident surface and the light back surface of the silicon wafer (1) are both provided with the conductive film layers (2), and the circuit patterns are respectively formed on each conductive film layer (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321658175.2U CN220208979U (en) | 2023-06-27 | 2023-06-27 | Gate line electrode of heterojunction solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321658175.2U CN220208979U (en) | 2023-06-27 | 2023-06-27 | Gate line electrode of heterojunction solar cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220208979U true CN220208979U (en) | 2023-12-19 |
Family
ID=89149063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321658175.2U Active CN220208979U (en) | 2023-06-27 | 2023-06-27 | Gate line electrode of heterojunction solar cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220208979U (en) |
-
2023
- 2023-06-27 CN CN202321658175.2U patent/CN220208979U/en active Active
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