CN220122954U - MES system integrated output interface assembly - Google Patents
MES system integrated output interface assembly Download PDFInfo
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- CN220122954U CN220122954U CN202320400482.4U CN202320400482U CN220122954U CN 220122954 U CN220122954 U CN 220122954U CN 202320400482 U CN202320400482 U CN 202320400482U CN 220122954 U CN220122954 U CN 220122954U
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Abstract
An MES system integrated output interface component relates to the technical field of Manufacturing Execution Systems (MES), comprising: the LVDS transmitting interface circuit is in communication connection with the memory; the LVDS receiving interface circuit comprises a first LVDS receiving interface circuit and a second LVDS receiving interface circuit; the first LVDS receiving interface circuit is in communication connection with the memory, and the second LVDS receiving interface circuit is in communication connection with the image equipment; the Ethernet interface circuit is in communication connection with the upper computer and/or the PCM equipment; the interface circuit is synchronized 422. The MES system integrated output interface component is reasonable in design, and data transmission is carried out through the LVDS transmitting interface circuit, the LVDS receiving interface circuit, the Ethernet interface circuit, the synchronous 422 interface circuit and all equipment of the MES system, so that different types of received data can be received, and compatibility is improved.
Description
Technical Field
The utility model relates to the technical field of interfaces, in particular to an MES system integrated output interface component.
Background
With the advent of the intelligent manufacturing age, the integration of informatization technology and automation technology has been deepened continuously, and for the manufacturing industry, it is necessary to transmit data by using informatization means, optimize production management, and increase the automation level to increase the production efficiency. Under such circumstances, the MES system becomes a main production information management system for many large and medium-sized manufacturing enterprises. The MES system is capable of enabling the production process to be more precise, efficient and transparent, greatly reducing the high dependence of Chinese manufacturing on the number and the capability of people and converting the production process into a more intelligent direction.
With the advancement of modern electronic communication technology, a common low-speed transmission interface, for example: the RS-232 interface, the RS-422 interface standard, the hundred megaEthernet and the like can not meet the requirements of modern electronic communication. At present, in various data recording devices of an MES system, interface types are different and various, and incompatibility of interface data causes great limitation to data rapid transmission of the MES system.
For example, patent application No. PCTDE2022100405 discloses a module with an integrated WLAN ethernet data interface, patent application No. PCTCN2020106384 discloses a method and apparatus for adjusting physical interfaces in a flexible ethernet group, and so on.
Therefore, an object of the present utility model is to provide another MES system integrated output interface module, which performs data transmission with each device of the MES system through an LVDS transmitting interface circuit, an LVDS receiving interface circuit, an ethernet interface circuit, a synchronous 422 interface circuit, so that different types of data can be received, and compatibility is improved.
Disclosure of Invention
The utility model aims to: in order to overcome the defects, the utility model aims to provide an MES system integrated output interface component which is reasonable in design, performs data transmission through an LVDS transmitting interface circuit, an LVDS receiving interface circuit, an Ethernet interface circuit, a synchronous 422 interface circuit and various devices of the MES system, can receive different types of data, performs mixed framing through a controller, and re-frames the data into a memory, thereby improving compatibility and having wide application prospect.
The technical scheme is as follows: an MES system integrated output interface assembly, comprising:
the LVDS transmitting interface circuit is in communication connection with the memory;
the LVDS receiving interface circuit comprises a first LVDS receiving interface circuit and a second LVDS receiving interface circuit; the first LVDS receiving interface circuit is in communication connection with the memory, and the second LVDS receiving interface circuit is in communication connection with the image equipment;
the Ethernet interface circuit is in communication connection with the upper computer and/or the PCM equipment;
a synchronization 422 interface circuit, said synchronization 422 interface circuit being communicatively coupled to the PCM device.
The MES system integrated output interface component is reasonable in design, performs data transmission through the LVDS transmitting interface circuit, the LVDS receiving interface circuit, the Ethernet interface circuit, the synchronous 422 interface circuit and various devices of the MES system, can receive different types of data, and is used for interacting with data of a memory, the LVDS transmitting interface circuit and the LVDS receiving interface circuit are used for completing data interaction, the LVDS receiving interface circuit is used for completing image data reception, the LVDS receiving interface circuit is used for completing data communication with an upper computer, the Ethernet interface is used for completing data communication with a PCM data, and the Ethernet interface circuit and the synchronous 422 interface circuit are used for completing data communication with a PCM data.
Further, the MES system integrated output interface assembly further includes:
the controller is respectively connected with the LVDS transmitting interface circuit, the LVDS receiving interface circuit, the Ethernet interface circuit, the synchronous 422 interface circuit interface and the memory.
And the data of different types received by each interface circuit are mixed and framed through the controller, and the re-framed data are put into the memory, so that the compatibility is improved. In addition, online updating of the controller is responsible for the ethernet interface.
When PCM1, PCM2, LVDS image data of MES system are received by LVDS transmitting interface circuit, LVDS receiving interface circuit, ethernet interface circuit, synchronous 422 interface circuit and written into controller, after the controller packages the above data, it is transferred to memory by LVDS transmitting interface circuit, the controller simultaneously receives the state information fed back by memory, after framing again, it is sent out by Ethernet interface, in addition, the receiving end of Ethernet interface is inquired about whether there is upper computer related instruction or not, and transferred to memory.
Further, the MES system integrated output interface assembly further includes:
the internal bus is connected with the voltage converter, the voltage converter is respectively connected with the LVDS transmitting interface circuit, the LVDS receiving interface circuit, the Ethernet interface circuit, the synchronous 422 interface circuit and the controller for supplying power, and the internal bus is connected with the memory for supplying power.
The +5V power supply is obtained from the internal bus, then the +5V power supply is converted by the voltage converter, and then 3.3V, 2.5V, 1.8V, 1.0V voltage and the like are output, and then the power supply is supplied to the LVDS transmitting interface circuit, the LVDS receiving interface circuit, the Ethernet interface circuit, the synchronous 422 interface circuit and the controller. And the internal bus directly powers the memory.
Further, the MES system integrates the output interface component, and the ethernet interface circuit 3 is a gigabit ethernet interface or a tera ethernet interface.
The Ethernet interface circuit uses UDP/IP protocol for data communication.
Furthermore, the MES system integrates an output interface component, and the controller is an FPGA+PHY controller.
The FPGA is selected as the main controller, the structure is simple, the external part is matched with the PHY chip for assistance, the influence caused by the instruction execution period can be avoided, and the data transmission speed can be increased.
Further, the MES system integrated output interface assembly described above, the LVDS transmission interface circuit includes:
parallel-serial conversion module I;
the controller, the parallel-serial conversion module I, the LVDS output driving module and the memory are connected in sequence;
the clock module is connected with the parallel-serial conversion module;
and the bias module is respectively connected with the parallel-serial conversion module I and the LVDS output driving module.
The parallel-serial conversion module converts a parallel input signal with a lower speed into a serial signal with a higher speed, the clock module synchronizes data, the LVDS output driving module converts a serial high-speed CMOS level signal into a differential low-voltage low-swing LVDS signal and provides driving capability for the transmission of the signal on a transmission line, the bias module provides required bias voltage or current for the whole parallel-serial conversion module and the LVDS output driving module, and the data transmission rate of the LVDS transmitting interface circuit can reach 1.25Gbps.
Further, in the foregoing MES system integrated output interface assembly, the LVDS receiving interface circuit one includes:
an adaptive equalization module I;
and the memory, the adaptive equalization module I, the parallel-serial conversion module II and the controller are connected in sequence.
The LVDS receiving interface circuit I and the memory are used for data transmission, data are read from the memory, the memory is an internal device, the transmission distance is short, the adaptive equalization module and the parallel-serial conversion module II are adopted, and the adaptive equalization module is used for automatically supplementing signals to the original state, so that signal attenuation can be reduced.
Further, the MES system integrated output interface assembly, the LVDS receiving interface circuit two includes:
an adaptive equalization module II;
an electrical isolation module;
and the image equipment, the adaptive equalization module II, the electrical isolation module, the parallel-serial conversion module III and the controller are connected in sequence.
The self-adaptive equalization module II automatically supplements the signal to the original state, and the electrical isolation module is matched, so that the safety, accuracy and anti-interference performance of the signal are greatly improved, and then the differential signal is changed into a parallel transmission signal through the L parallel-serial conversion module III and enters the controller for signal processing.
The beneficial effects of the utility model are as follows:
(1) The MES system integrated output interface component has reasonable design, the data interaction with the memory is completed by adopting an LVDS transmitting interface circuit and an LVDS receiving interface circuit I, the image data is received by adopting an LVDS receiving interface circuit II, the data communication with an upper computer is completed by an Ethernet interface, the PCM data is completed by adopting an Ethernet interface circuit and a synchronous 422 interface circuit, and the data of different types can be received;
(2) According to the MES integrated output interface component, different types of data received by the interface circuits are subjected to mixed framing through the controller, and the frames are rearranged and put into the memory, so that the compatibility is improved.
Drawings
FIG. 1 is a functional block diagram of an MES system integrated output interface assembly according to the present utility model;
FIG. 2 is a schematic block diagram of an LVDS transmission interface circuit of an MES system integrated output interface assembly according to the present utility model;
FIG. 3 is a schematic block diagram of an LVDS receiving interface circuit of an MES system integrated output interface assembly according to the present utility model;
FIG. 4 is a schematic block diagram of a LVDS receiving interface circuit of an MES system integrated output interface assembly according to the present utility model;
in the figure: the device comprises an LVDS transmitting interface circuit 1, a parallel-serial conversion module 11, an LVDS output driving module 12, a clock module 13, a bias module 14, an LVDS receiving interface circuit 2, an LVDS receiving interface circuit 21, an adaptive equalization module 211, a parallel-serial conversion module 212, an LVDS receiving interface circuit 22, an adaptive equalization module 221, an electrical isolation module 222, a parallel-serial conversion module 223, an Ethernet interface circuit 3, a synchronous 422 interface circuit 4, a controller 5, a voltage converter 6, a memory 7, an image device 8, an upper computer 9 and a PCM device 10.
Detailed Description
The utility model will be further elucidated with reference to figures 1, 2, 3, 4 and specific examples.
Example 1
As shown in fig. 1, the MES system integrated output interface assembly of the present utility model includes an LVDS transmitting interface circuit 1, an LVDS receiving interface circuit 2, an ethernet interface circuit 3, a synchronous 422 interface circuit 4, a controller 5, and a voltage converter 6.
Specifically: the data interaction with the memory 7 is completed by adopting a first LVDS transmitting interface circuit 1 and a first LVDS receiving interface circuit 21 of a LVDS receiving interface circuit 2, the image data receiving of the image equipment 8 is completed by a second LVDS receiving interface circuit 22 of the LVDS receiving interface circuit 2, the data communication with the upper computer 9 is completed by the Ethernet interface 3, the PCM data of the PCM equipment 10 is divided into 2 paths, one path is transmitted by the Ethernet interface 3, the effective data is obtained according to the IP packet of the PCM data, the effective data is written into the controller 5 for buffering, the other path is transmitted by a synchronous 422 interface circuit 4, the synchronous 422 interface circuit 4 receives the PCM data, and the transmitting end interface realizes the clock and the PCM data transmission through the receiving end chip and the configuration circuit thereof.
Furthermore, the data of different types received by each interface circuit are mixed and framed through the controller 5, and the re-framed data are put into the memory 7, so that the compatibility is improved.
Specifically: each interface circuit receives different types of data PCM, LVDS image data and the like of the MES system, writes the data PCM, LVDS image data and the like into the controller 5, the controller 5 packages the data, transmits the data to the memory 7 through the LVDS sending interface circuit 1, the controller 5 simultaneously receives state information fed back by the memory 7, sends out the data after framing again through the ethernet interface 3, and additionally inquires whether a receiving end of the ethernet interface 3 has an upper computer 9 related instruction or not and forwards the data to the memory 7.
Furthermore, the FPGA is selected as the main controller 5, so that the structure is simple, the effect caused by the instruction execution period can be avoided by the assistance of the external PHY chip, and the data transmission speed can be increased.
Example 2
The structural basis based on embodiment 1 above is shown in fig. 1 and 3.
The MES system integrated output interface component further comprises power supply, wherein +5V power supply is obtained from an internal bus 101, then 3.3V, 2.5V, 1.8V, 1.0V voltage and the like are output after being converted by a voltage converter 6, and then the power supply is carried out for an LVDS transmitting interface circuit 1, an LVDS receiving interface circuit 2, an Ethernet interface circuit 3, a synchronous 422 interface circuit 4 and a controller 5. And the internal bus 101 directly supplies power to the memory 7.
Example 3
The structural basis based on embodiment 1 or embodiment 2 is shown in fig. 1, 2 and 3.
The utility model relates to an MES system integrated output interface component, which comprises a parallel-serial conversion module I11, an LVDS output driving module 12, a clock module 13 and a bias module 14, wherein the parallel-serial conversion module I11 converts a parallel input signal with lower speed into a serial signal with higher speed, the clock module 13 synchronizes data, the LVDS output driving module 12 converts a serial high-speed CMOS level signal into a differential low-voltage low-swing LVDS signal, driving capability is provided for transmission of the signal on a transmission line, the bias module 14 provides required bias voltage or current for the whole parallel-serial conversion module 11 and the LVDS output driving module 12, and the data transmission rate of the LVDS transmission interface circuit 1 can reach 1.25Gbps.
The first LVDS receiving interface circuit 21 includes a first adaptive equalization module 211, a second parallel-to-serial conversion module 212, the second LVDS receiving interface circuit 22 includes a second adaptive equalization module 221, an electrical isolation module 222, and a third parallel-to-serial conversion module 223, the first LVDS receiving interface circuit 21 and the memory 7 are in data transmission, the data is read from the memory 7, the data is an internal device, the transmission distance is short, the first adaptive equalization module 211 and the second parallel-to-serial conversion module 212 are adopted, the second LVDS receiving interface circuit 22 and the image device 8 are in image data transmission, the transmission distance is generally long, the data is necessarily influenced by the second LVDS receiving interface circuit 22 through a transmission cable and a connector, and therefore the second adaptive equalization module 221 supplements the signal to the original state automatically, and the second LVDS receiving interface circuit is matched with the electrical isolation module 222, so that the signal safety, the accuracy and the anti-interference performance are greatly improved.
The foregoing is merely a preferred embodiment of the utility model, and it should be noted that modifications could be made by those skilled in the art without departing from the principles of the utility model, which modifications would also be considered to be within the scope of the utility model.
Claims (8)
1. An MES system integrated output interface assembly, comprising:
an LVDS transmission interface circuit (1), wherein the LVDS transmission interface circuit (1) is in communication connection with a memory (7);
the LVDS receiving interface circuit (2) comprises a first LVDS receiving interface circuit (21) and a second LVDS receiving interface circuit (22); the LVDS receiving interface circuit I (21) is in communication connection with the memory (7), and the LVDS receiving interface circuit II (22) is in communication connection with the image equipment (8);
an Ethernet interface circuit (3), wherein the Ethernet interface circuit (3) is in communication connection with an upper computer (9) and/or a PCM device (10);
a synchronization 422 interface circuit (4), said synchronization 422 interface circuit (4) being in communication with the PCM device (10).
2. The MES system integrated output interface assembly of claim 1, further comprising:
the controller (5) is respectively connected with the LVDS transmitting interface circuit (1), the LVDS receiving interface circuit (2), the Ethernet interface circuit (3), the synchronous 422 interface circuit interface (4) and the memory (7).
3. The MES system integrated output interface assembly of claim 2, further comprising:
the voltage converter (6), internal bus (101) with voltage converter (6) is connected, voltage converter (6) respectively with LVDS send interface circuit (1), LVDS receive interface circuit (2), ethernet interface circuit (3), synchronous 422 interface circuit (4), controller (5) are connected the power supply, internal bus (101) is connected with memory (7) and is supplied power.
4. The MES system integrated output interface assembly according to claim 1, wherein the ethernet interface circuit (3) is a gigabit ethernet interface or a tera ethernet interface.
5. The MES system integrated output interface assembly according to claim 2, wherein the controller (5) is an fpga+phy controller.
6. The MES system integrated output interface assembly according to claim 2, wherein the LVDS transmission interface circuit (1) comprises:
parallel-serial conversion module I (11);
the LVDS output driving module (12), the controller (5), the parallel-serial conversion module I (11), the LVDS output driving module (12) and the memory (7) are connected in sequence;
the clock module (13), the said clock module (13) is connected with parallel-serial conversion module and (11);
the bias module (14), the bias module (14) is connected with the parallel-serial conversion module I (11) and the LVDS output driving module (12) respectively.
7. The MES system integrated output interface assembly according to claim 2, wherein the LVDS receive interface circuit one (21) comprises:
an adaptive equalization module one (211);
and the second parallel-serial conversion module (212), the first memory (7), the first adaptive equalization module (211), the second parallel-serial conversion module (212) and the controller (5) are sequentially connected.
8. The MES system integrated output interface assembly of claim 2, wherein the LVDS receive interface circuit two (22) comprises:
an adaptive equalization module II (221);
an electrical isolation module (222);
and the image equipment (8), the adaptive equalization module II (221), the electrical isolation module (222), the parallel-serial conversion module III (223) and the controller (5) are sequentially connected.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320400482.4U CN220122954U (en) | 2023-03-07 | 2023-03-07 | MES system integrated output interface assembly |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320400482.4U CN220122954U (en) | 2023-03-07 | 2023-03-07 | MES system integrated output interface assembly |
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| CN220122954U true CN220122954U (en) | 2023-12-01 |
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| CN202320400482.4U Active CN220122954U (en) | 2023-03-07 | 2023-03-07 | MES system integrated output interface assembly |
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