CN220087303U - Master communication equipment, slave communication equipment and communication system - Google Patents

Master communication equipment, slave communication equipment and communication system Download PDF

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Publication number
CN220087303U
CN220087303U CN202320761626.9U CN202320761626U CN220087303U CN 220087303 U CN220087303 U CN 220087303U CN 202320761626 U CN202320761626 U CN 202320761626U CN 220087303 U CN220087303 U CN 220087303U
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spi
slave
data
communication device
master
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陈国华
许琼隆
王广
刘文莉
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Hytera Communications Corp Ltd
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Hytera Communications Corp Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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Abstract

The utility model discloses a master communication device, a slave communication device and a communication system, wherein the master communication device is connected with at least two slave communication devices through a CAN bus, and the master communication device comprises: each of the main SPI-CAN transceiver chips is connected with one of the at least two slave communication devices through a CAN bus, the control switch is respectively connected with each of the main SPI-CAN transceiver chips, the main CPU is respectively connected with the control switch and each of the main SPI-CAN transceiver chips through SPI interfaces, wherein the control switch is used for controlling the main CPU to send/receive data, when the main CPU sends data, the main CPU sends broadcast data to each of the slave communication devices, and when the main CPU receives data, the main CPU receives broadcast data sent from any one of the at least two slave communication devices to other of the at least two slave communication devices. According to the scheme, long-distance transmission and high-speed transmission are realized, meanwhile, the CAN bus broadcasting receiving and transmitting function is reserved, and the effectiveness of data is guaranteed.

Description

Master communication equipment, slave communication equipment and communication system
Technical Field
The present utility model relates to the field of communications electronics, and in particular, to a master communication device, a slave communication device, and a communication system.
Background
The CAN bus is widely applied to automobile buses and industrial field buses, only two wires are needed to realize data transmission, the bus technology mode CAN connect a plurality of devices, the highest speed reaches 1Mbps, and the transmission distance CAN reach 10km. The longer the transmission distance, the lower the data rate. The CAN bus is usually 500kbps, and as the functions are gradually increased, the more information interaction is carried out among the devices, so that the bus load is continuously increased; only about 40-50% of the bandwidth in the CAN message is used for actual data transmission; the response mechanism is limited by the physical characteristics of the field wiring, such as ACK generation delay in the CAN controller; transceiver propagation delay; wire delays, etc. In order to solve the limitations of the CAN bus, it is indispensable to upgrade it, so that CAN FD is known as CAN with Flexible Data rate. The highest transmission rate of CAN FD CAN reach 5Mbps, and likewise, the data transmission rate decreases as the transmission distance becomes longer.
Disclosure of Invention
The utility model provides at least a master communication device, a slave communication device and a communication system.
The first aspect of the present utility model provides a master communication device connected to at least two slave communication devices via a CAN bus, the master communication device comprising: each of the at least two master SPI-CAN transceiver chips is connected with one slave communication device of the at least two slave communication devices through a CAN bus; the control switch is respectively connected with each main SPI-CAN transceiver chip; the main CPU is respectively connected with the control switch and each main SPI-CAN transceiver chip through SPI interfaces; wherein the control switch is used for controlling the main CPU to send/receive data, and when the main CPU sends data, the main CPU sends broadcast data to each slave communication device; when the main CPU receives data, the main CPU receives broadcast data transmitted from any one of the at least two slave communication devices to other slave communication devices in the at least two slave communication devices.
In some embodiments, the communication device further includes a switch group, and the control switch includes a switch group for controlling the main CPU to transmit/receive data.
In some embodiments, the SPI interface comprises a chip select pin, a clock pin, a first data pin, and a second data pin, wherein the first data pin and the second data pin each represent a different data transmission mode; the chip selection pins of the main CPU are connected with the chip selection pins of each main SPI-CAN transceiver chip, the clock pins of the main CPU are connected with the clock pins of each main SPI-CAN transceiver chip, and the first data pins and the second data pins of the main CPU are connected with the first data pins and the second data pins of each main SPI-CAN transceiver chip through the switch group.
In some embodiments, the at least two master SPI-CAN transceiver chips comprise a first master SPI-CAN transceiver chip and a second master SPI-CAN transceiver chip, and the at least two slave communications devices comprise a first slave communications device and a second slave communications device; the first slave communication equipment is connected with the first master SPI-CAN transceiver chip through a CAN bus, and the second slave communication equipment is connected with the second master SPI-CAN transceiver chip through a CAN bus; the chip selection pins of the main CPU are respectively connected with the chip selection pins of the first and second SPI-CAN transceiver chips, and the clock pins of the main CPU are respectively connected with the clock pins of the first and second SPI-CAN transceiver chips; the first data pin and the second data pin of the main CPU are connected with the first data pin and the second data pin of the first SPI-CAN transceiver chip and the second SPI-CAN transceiver chip through the switch group.
In some embodiments, the switch set includes a first switch, a second switch, and a third switch, wherein: the first end of the first switch is connected with a first data pin of the first main SPI-CAN transceiver chip, the second end of the first switch is connected with a first data pin of the main CPU, and the third end of the first switch is connected with a second data pin of the second main SPI-CAN transceiver chip; the first end of the second switch is connected with a second data pin of the main CPU, the second end of the second switch is connected with a second data pin of the first main SPI-CAN transceiver chip, and the third end of the second switch is connected with a second data pin of the second main SPI-CAN transceiver chip; the first end of the third switch is connected with a first data pin of the second SPI-CAN transceiver chip, the second end of the third switch is connected with a first data pin of the main CPU, and the third end of the third switch is connected with a second data pin of the main CPU; when the first end of the first switch is communicated with the second end, and the first end of the third switch is communicated with the second end, the main CPU sends broadcast data to the first slave communication equipment and the second slave communication equipment; when the first end of the second switch is communicated with the second end and the first end of the third switch is communicated with the third end, the first slave communication device sends broadcast data to the main CPU and the second slave communication device; when the first end of the second switch is communicated with the third end, and the first end of the first switch is communicated with the third end, the second slave communication device transmits broadcast data to the main CPU and the first slave communication device.
In some embodiments, when the main CPU receives data, the main CPU is further configured to receive an arbitration signal sent by any one of the at least two slave communication devices, where the arbitration signal is used to indicate that the any one slave communication device applies to send data
In some embodiments, each of the at least two master SPI-CAN transceiver chips includes a controller for implementing a conversion control from an SPI protocol to a CAN transfer protocol or a CAN FD transfer protocol supported by the CAN bus, and for data transceiver control.
In some embodiments, the CAN bus supports a CAN transfer protocol or CAN FD transfer protocol.
A second aspect of the present utility model provides a slave communication device connected to a master communication device as described in any of the first aspects above via a CAN bus, the slave communication device comprising: the slave SPI-CAN transceiver chip is connected with any one of at least two master SPI-CAN transceiver chips in the master communication equipment through a CAN bus; the slave CPU is connected with the slave SPI-CAN transceiver chip through an SPI interface and is used for controlling the slave SPI-CAN transceiver chip to communicate with the master communication equipment through the SPI interface; when the slave CPU controls the slave SPI-CAN transceiver chip to receive data, the slave SPI-CAN transceiver chip receives broadcast data sent by the master CPU, and when the slave CPU controls the slave SPI-CAN transceiver chip to send data, the slave SPI-CAN transceiver chip sends broadcast data to the master communication equipment and other slave communication equipment.
In some embodiments, the SPI interface comprises a chip select pin, a clock pin, a first data pin, and a second data pin, wherein the first data pin and the second data pin each represent a different data transmission mode; the chip selection pin of the slave CPU is connected with the chip selection pin of the slave SPI-CAN transceiver chip, the clock pin of the slave CPU is connected with the clock pin of the slave SPI-CAN transceiver chip, the first data pin of the slave CPU is connected with the first data pin of the slave SPI-CAN transceiver chip, and the second data pin of the slave CPU is connected with the second data pin of the slave SPI-CAN transceiver chip.
A third aspect of the present utility model provides a communication system comprising a master communication device as in the first aspect and at least two slave communication devices as in the second aspect.
According to the scheme, the communication device is connected with at least two slave communication devices through the CAN bus, and the master communication device comprises: each main SPI-CAN transceiver chip is connected with one slave communication device of at least two slave communication devices through a CAN bus, a control switch is respectively connected with each main SPI-CAN transceiver chip, a main CPU is respectively connected with the control switch and each main SPI-CAN transceiver chip through SPI interfaces, wherein the control switch is used for controlling the main CPU to send/receive data, when the main CPU sends data, the main CPU sends broadcast data to each slave communication device, when the main CPU receives data, the main CPU receives broadcast data sent from any slave communication device of at least two slave communication devices to other slave communication devices of at least two slave communication devices, thereby realizing long-distance transmission and high-speed transmission, simultaneously retaining the CAN bus broadcast transceiver function, and guaranteeing the effectiveness of the data.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the utility model as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the utility model and together with the description, serve to explain the principles of the utility model.
FIG. 1 is a schematic diagram of an embodiment of a primary communication device of the present utility model;
FIG. 2 is a schematic diagram of another embodiment of a primary communication device of the present utility model;
FIG. 3 is a schematic circuit diagram of a portion of a primary communication device according to an embodiment of the present utility model;
FIG. 4 is a schematic circuit diagram of a portion of a primary communication device according to an embodiment of the present utility model;
FIG. 5 is a schematic diagram of an embodiment of a slave communication device of the present utility model;
FIG. 6 is a schematic diagram of an embodiment of a communication system of the present utility model;
FIG. 7 is a flow chart of an embodiment of the communication method of the present utility model.
Detailed Description
The following describes embodiments of the present utility model in detail with reference to the drawings.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present utility model.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship. Further, "a plurality" herein means two or more than two. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Referring to fig. 1, fig. 1 is a schematic diagram of a main communication device 10 according to an embodiment of the present utility model. The master communication device 10 is connected to at least two slave communication devices 20 via CAN bus, and includes: at least two main SPI-CAN transceiver chips 101, main CPU102, control switch 104.
At least two master SPI-CAN transceiver chips 101, each connected to one of the at least two slave communication devices 20 via a CAN bus.
The master SPI-CAN transceiver chip 101 may be a transceiver chip that converts an SPI protocol into a CAN protocol, that is, implements conversion of an SPI interface into a CAN interface for receiving data sent from the communication device 20, and may also send data to the slave communication device 20.
The main CPU102 is respectively connected with the control switch 104 and each main SPI-CAN transceiver chip through the SPI interface 103, wherein the main CPU102 is configured with the SPI interface 103, and the SPI interface 103 CAN perform data transmission between the main CPU102 and at least two main SPI-CAN transceiver chips 101.
The control switch 104 is connected to each of the master SPI-CAN transceiver chips, where the control switch 104 may refer to a manner of switching a connection relationship between the master CPU102 and at least two master SPI-CAN transceiver chips 101 through the SPI interface 103 by using a switching device, a program instruction, or the like.
Wherein the control switch 104 is for controlling the main CPU102 to transmit/receive data, and when the main CPU102 transmits data, the main CPU102 transmits broadcast data to each of the slave communication devices; when the main CPU102 receives data, the main CPU102 receives broadcast data transmitted from any one of the at least two slave communication devices 20 to other slave communication devices of the at least two slave communication devices 20.
Taking the number of the slave communication devices as two as an example, the master CPU102 selects two master SPI-CAN transceiver chips correspondingly connected with the two slave communication devices through the SPI interface 103, and CAN realize that the master communication device sends broadcast data to the two slave communication devices or one of the slave communication devices sends broadcast data to the master communication device and the other slave communication device through controlling to switch the connection between the two master SPI-CAN transceiver chips.
In this embodiment, the master communication device 10 is connected to at least two slave communication devices 20 via CAN buses, and includes: and the control switch 104 is used for controlling the main CPU to send/receive data, when the main CPU sends data, the main CPU sends broadcast data to each slave communication device, and when the main CPU receives data, the main CPU receives broadcast data sent from any one of the at least two slave communication devices to other slave communication devices in the at least two slave communication devices. According to the scheme, long-distance transmission and high-speed transmission are realized, meanwhile, the CAN bus broadcasting receiving and transmitting function is reserved, and the effectiveness of data is guaranteed.
As described above, the control switch 104 is used to control the main CPU to transmit/receive data, referring to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of the main communication device of the present utility model, and in some embodiments, the control switch 104 includes a switch group for controlling the main CPU to transmit/receive data.
Switch bank 1041 may include a plurality of dual-control switches, switching diodes, or other devices having control circuit connection functions.
In some embodiments, referring to fig. 3, fig. 3 is a schematic circuit diagram of a portion of the primary communication device 10 of the present utility model. SPI interface 103 includes a chip select pin SPI_nCS, a clock pin SPI_CLK, a first data pin SPI_MOSI, and a second data pin SPI_MISO, where the first data pin SPI_MOSI and the second data pin SPI_MISO represent different data transmission modes, respectively.
The chip selection pin of the main CPU is connected with the chip selection pin of each main SPI-CAN transceiver chip, the clock pin of the main CPU is connected with the clock pin of each main SPI-CAN transceiver chip, and the first data pin and the second data pin of the main CPU are connected with the first data pin and the second data pin of each main SPI-CAN transceiver chip through the switch group.
The main CPU102 is connected to the chip select pins of each of the main SPI-CAN transceiver chips through the SPI interface 103, the chip select pins spi_ncs and clock pins spi_clk of the main CPU102 are directly connected to the chip select pins spi_ncs and clock pins spi_clk of at least two of the main SPI-CAN transceiver chips 101, and the first data pin spi_mosi and the second data pin spi_moso of the main CPU102 are connected to the first data pin spi_mosi and the second data pin spi_miso of at least two of the main SPI-CAN transceiver chips 101 through the switch group 1041.
Table 1 pin of SPI interface 103
Pin name Pin definition
SPI_nCS SPI chip selection
SPI_CLK SPI clock
SPI_MOSI SPI data master-slave in and out
SPI_MISO SPI data master-in and slave-out
In some embodiments, as shown in fig. 3, at least two master SPI-CAN transceiver chips 101 include a first master SPI-CAN transceiver chip 101a and a second master SPI-CAN transceiver chip 101b, and at least two slave communication devices 20 include a first slave communication device 20a and a second slave communication device 20b.
The first slave communication device 20a is connected to the first master SPI-CAN transceiver chip 101a via a CAN bus, and the second slave communication device 20b is connected to the second master SPI-CAN transceiver chip 101b via a CAN bus.
The chip selection pin SPI_nCS of the main CPU102 is respectively connected with the chip selection pins SPI_nCS of the first main SPI-CAN transceiver chip 101a and the second main SPI-CAN transceiver chip 101b, and the clock pin SPI_CLK of the main CPU is respectively connected with the clock pins SPI_CLK of the first main SPI-CAN transceiver chip 101a and the second main SPI-CAN transceiver chip 101 b.
The first data pin spi_mosi and the second data pin spi_miso of the main CPU102 are connected to the first data pin spi_mosi and the second data pin spi_miso of the first and second main SPI-CAN transceiver chips 101a and 101b through the switch group 1041.
As described above, the first data pin spi_mosi and the second data pin spi_miso of the main CPU are connected to the first data pin spi_mosi and the second data pin spi_miso of the first and second main SPI-CAN transceiver chips 101a and 101b through the switch assembly 1041, and fig. 4 is a schematic circuit diagram of a portion of the main communication device 10 according to the present utility model. The switch group 1041 includes a first switch S1, a second switch S2, and a third switch S3, wherein:
the first end a1 of the first switch S1 is connected to the first data pin spi_mosi of the first master SPI-CAN transceiver chip 101a, the second end a2 is connected to the first data pin spi_mosi of the master CPU102, and the third end a3 is connected to the second data pin spi_moso of the second master SPI-CAN transceiver chip 101 b.
The first terminal b1 of the second switch S2 is connected to the second data pin spi_moso of the main CPU102, the second terminal b2 is connected to the second data pin spi_moso of the first main SPI-CAN transceiver chip 101a, and the third terminal b3 is connected to the second data pin spi_moso of the second main SPI-CAN transceiver chip 101 b.
The first end c1 of the third switch S3 is connected to the first data pin spi_mosi of the second master SPI-CAN transceiver chip 101b, the second end c2 is connected to the first data pin spi_mosi of the master CPU102, and the third end c3 is connected to the second data pin spi_moso of the master CPU 102.
When the first terminal a1 of the first switch S1 is in control communication with the second terminal a2, and the first terminal c1 of the third switch S3 is in communication with the second terminal c2, the master CPU102 transmits broadcast data to the first slave communication device 20a and the second slave communication device 20b.
When the first terminal b1 of the second switch S2 is connected to the second terminal b2 and when the first terminal c1 of the third switch S3 is connected to the third terminal c3, the first slave communication device 20a transmits broadcast data to the master CPU102 and the second slave communication device 20b.
When the first terminal b1 of the second switch S2 is in communication with the third terminal b3 and the first terminal a1 of the first switch S1 is in control communication with the third terminal a3, the second slave communication device 20b transmits broadcast data to the master CPU102 and the first slave communication device 20 a.
In some embodiments, when the master CPU receives data, the master CPU is further configured to receive an arbitration signal sent by any one of the at least two slave communication devices 20, where the arbitration signal is used to indicate that any one of the slave communication devices 20 applies to send data.
The SPI interface 103 of the master CPU102 is separated from the transmission/reception data lines to which all the slave communication devices 20 are connected, so that data can be received while data is transmitted, and when any arbitration request signal transmitted from any slave communication device is received during data transmission, the master communication device 10 can switch the requested slave communication device 20 to the master communication device 10 according to circumstances, and the original master communication device 10 can switch to the slave communication device 20.
In some embodiments, each of the at least two master SPI-CAN transceiver chips 101 includes a controller (not shown) for implementing conversion from an SPI protocol to a CAN transmission protocol or a CAN FD transmission protocol supported by a CAN bus, and for data transceiving control.
As described above, the controller is configured to implement a conversion from the SPI protocol to a CAN transfer protocol or CAN FD transfer protocol supported by the CAN bus, which in some embodiments supports the CAN transfer protocol or CAN FD transfer protocol.
The CAN transmission protocol and the CAN FD transmission protocol are the same protocol and adopt the same bus topology structure.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of the slave communication device 20 according to the present utility model. The slave communication device includes a slave SPI-CAN transceiver chip 202 and a slave CPU201.
The slave SPI-CAN transceiver chip 202 may be a transceiver chip that converts an SPI protocol into a CAN protocol, that is, implements conversion of an SPI interface into a CAN interface, and is used for receiving data sent from the master communication device 10 and other connected slave communication devices 20, and may also be used for sending data to the master communication device 10 and other connected slave communication devices 20.
The slave CPU201 is connected to the slave SPI-CAN transceiver chip 202 through the SPI interface 203, and is configured to control the slave SPI-CAN transceiver chip 202 to communicate with the master communication device 10 through the SPI interface 203.
When the slave CPU controls the slave SPI-CAN transceiver chip to receive data, the slave SPI-CAN transceiver chip receives broadcast data sent by the master CPU, and when the slave CPU controls the slave SPI-CAN transceiver chip to send data, the slave SPI-CAN transceiver chip sends broadcast data to the master communication equipment and other slave communication equipment.
In some embodiments, the SPI interface comprises a chip select pin SPI_nCS, a clock pin SPI_CLK, a first data pin SPI_MOSI, and a second data pin SPI_MISO, wherein the first data pin SPI_MOSI and the second data pin SPI_MISO respectively represent different data transmission modes. The pin definition corresponding to the pin name of the SPI interface 203 of the slave CPU201 is shown in table 2, and the first data pin spi_mosi indicates that when SPI data is transmitted, the master communication device 10 transmits data to the slave communication device 20, that is, the slave communication device 20 transmits data. The second data pin spi_miso represents the transmission of SPI data from the communication device 20 to the master communication device, i.e. the master communication device 10 transmits in data.
The chip selection pin SPI_nCS of the slave CPU201 is connected with the chip selection pin SPI_nCS of the slave SPI-CAN transceiver chip 202, the clock pin SPI_CLK of the slave CPU201 is connected with the clock pin SPI_CLK of the slave SPI-CAN transceiver chip 202, the first data pin SPI_MOSI of the slave CPU201 is connected with the first data pin SPI_MOSI of the slave SPI-CAN transceiver chip 202, and the second data pin SPI_MISO of the slave CP201U is connected with the second data pin SPI_MISO of the slave SPI-CAN transceiver chip 202.
Table 2 pin of SPI interface 203
Pin name Pin definition
SPI_nCS SPI chip selection
SPI_CLK SPI clock
SPI_MOSI SPI data master-slave in and out
SPI_MISO SPI data master-in and slave-out
Referring to fig. 6, fig. 6 is a schematic diagram illustrating a communication system 60 according to an embodiment of the utility model. The master communication device 10 and the at least two slave communication devices 20 according to the above embodiments may be the master communication device 601 and the at least two slave communication devices 602, and the descriptions of the master communication device 10 and the at least two slave communication devices 20 according to the above embodiments are detailed in the description of the embodiments and are not described herein.
Referring to fig. 7, fig. 7 is a flow chart of an embodiment of the communication method of the present utility model. The method is applied to a master communication device 10, such as the master communication device 10 of the embodiment of fig. 1 described above, the master communication device 10 being connected to at least two slave communication devices 20 via a CAN bus.
Specifically, the method may include the steps of:
s71: at least two master SPI-CAN transceiver chips 101 are selected simultaneously through the SPI interface 103, and the master CPU102 is controlled to transmit data through the control switch 104, and the master CPU102 transmits broadcast data to each slave communication device.
S72: the main CPU102 is controlled to receive data by the control switch 104, and the main CPU102 receives broadcast data transmitted from any one of the at least two slave communication devices 20 to the other of the at least two slave communication devices.
In this embodiment, at least two master SPI-CAN transceiver chips 101 are selected simultaneously through the SPI interface 103, and the master CPU102 is controlled to transmit data through the control switch 104, and the master CPU102 transmits broadcast data to each slave communication device; the main CPU102 is controlled by the control switch 104 to receive data, and the main CPU102 receives broadcast data transmitted from any one of the at least two slave communication devices 20 to the other of the at least two slave communication devices, thereby receiving broadcast data from any one of the slave communication devices.
As described above, the main CPU102 receives broadcast data transmitted from any one of the at least two slave communication devices to other ones of the at least two slave communication devices, and in some embodiments, the method further includes: when the main CPU102 receives data, if the main CPU102 receives arbitration signals transmitted by other slave communication devices among the at least two slave communication devices 20, the main CPU102 transmits a control signal to the slave communication device that is transmitting broadcast data when determining that the other slave communication devices need to transmit data, so that the slave communication device that is transmitting broadcast data stops transmitting broadcast data, and receives broadcast data transmitted by the other slave communication devices.
Taking the circuit diagram of the embodiment of fig. 4 as an example, when the master CPU102 receives the data transmitted by the first slave communication device 20a and the second slave communication device 20b transmits the arbitration signal to the master CPU102, the master CPU102 determines that the second slave communication device 20b needs to transmit the data and transmits the control signal to the first slave communication device 20a, so that the first slave communication device 20a stops transmitting the broadcast data and receives the broadcast data transmitted by the second slave communication device 20b.
It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.
In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.
The foregoing description of various embodiments is intended to highlight differences between the various embodiments, which may be the same or similar to each other by reference, and is not repeated herein for the sake of brevity.
In the several embodiments provided in the present utility model, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical, or other forms.
In addition, each functional unit in the embodiments of the present utility model may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present utility model may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present utility model. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Claims (11)

1. A master communication device connected to at least two slave communication devices via a CAN bus, the master communication device comprising:
each of the at least two master SPI-CAN transceiver chips is connected with one slave communication device of the at least two slave communication devices through a CAN bus;
the control switch is respectively connected with each main SPI-CAN transceiver chip;
the main CPU is respectively connected with the control switch and each main SPI-CAN transceiver chip through SPI interfaces;
wherein the control switch is used for controlling the main CPU to send/receive data, and when the main CPU sends data, the main CPU sends broadcast data to each slave communication device; when the main CPU receives data, the main CPU receives broadcast data transmitted from any one of the at least two slave communication devices to other slave communication devices in the at least two slave communication devices.
2. The main communication device according to claim 1, wherein the control switch includes a switch group for controlling the main CPU to transmit/receive data.
3. The master communication device of claim 2, wherein the SPI interface comprises a chip select pin, a clock pin, a first data pin, and a second data pin, wherein the first data pin and the second data pin each represent a different data transmission mode;
the chip selection pins of the main CPU are connected with the chip selection pins of each main SPI-CAN transceiver chip, the clock pins of the main CPU are connected with the clock pins of each main SPI-CAN transceiver chip, and the first data pins and the second data pins of the main CPU are connected with the first data pins and the second data pins of each main SPI-CAN transceiver chip through the switch group.
4. A master communication device as claimed in claim 3, wherein the at least two master SPI-CAN transceiver chips comprise a first master SPI-CAN transceiver chip and a second master SPI-CAN transceiver chip, the at least two slave communication devices comprising a first slave communication device and a second slave communication device;
the first slave communication equipment is connected with the first master SPI-CAN transceiver chip through a CAN bus, and the second slave communication equipment is connected with the second master SPI-CAN transceiver chip through a CAN bus;
the chip selection pins of the main CPU are respectively connected with the chip selection pins of the first and second SPI-CAN transceiver chips, and the clock pins of the main CPU are respectively connected with the clock pins of the first and second SPI-CAN transceiver chips;
the first data pin and the second data pin of the main CPU are connected with the first data pin and the second data pin of the first SPI-CAN transceiver chip and the second SPI-CAN transceiver chip through the switch group.
5. The primary communication device of claim 4, wherein the switch set comprises a first switch, a second switch, and a third switch, wherein:
the first end of the first switch is connected with a first data pin of the first main SPI-CAN transceiver chip, the second end of the first switch is connected with a first data pin of the main CPU, and the third end of the first switch is connected with a second data pin of the second main SPI-CAN transceiver chip;
the first end of the second switch is connected with a second data pin of the main CPU, the second end of the second switch is connected with a second data pin of the first main SPI-CAN transceiver chip, and the third end of the second switch is connected with a second data pin of the second main SPI-CAN transceiver chip;
the first end of the third switch is connected with a first data pin of the second SPI-CAN transceiver chip, the second end of the third switch is connected with a first data pin of the main CPU, and the third end of the third switch is connected with a second data pin of the main CPU;
when the first end of the first switch is communicated with the second end, and the first end of the third switch is communicated with the second end, the main CPU sends broadcast data to the first slave communication equipment and the second slave communication equipment;
when the first end of the second switch is communicated with the second end and the first end of the third switch is communicated with the third end, the first slave communication device sends broadcast data to the main CPU and the second slave communication device;
when the first end of the second switch is communicated with the third end, and the first end of the first switch is communicated with the third end, the second slave communication device transmits broadcast data to the main CPU and the first slave communication device.
6. The master communication device according to claim 1, wherein when the master CPU receives data, the master CPU is further configured to receive an arbitration signal transmitted by any one of the at least two slave communication devices, wherein the arbitration signal is used to indicate that the any one slave communication device applies to transmit data.
7. The master communication device of any of claims 1-6, wherein each of the at least two master SPI-CAN transceiver chips comprises a controller for effecting a conversion from an SPI protocol to a transmission protocol supported by the CAN bus, and for data transceiver control.
8. The master communication device of claim 7, wherein the CAN bus supported transport protocol comprises CAN transport protocol, CAN FD transport protocol.
9. A slave communication device connected to a master communication device according to any of claims 1-8 via a CAN bus, the slave communication device comprising:
the slave SPI-CAN transceiver chip is connected with any one of at least two master SPI-CAN transceiver chips in the master communication equipment through a CAN bus;
the slave CPU is connected with the slave SPI-CAN transceiver chip through an SPI interface and is used for controlling the slave SPI-CAN transceiver chip to communicate with the master communication equipment through the SPI interface;
when the slave CPU controls the slave SPI-CAN transceiver chip to receive data, the slave SPI-CAN transceiver chip receives broadcast data sent by the master CPU, and when the slave CPU controls the slave SPI-CAN transceiver chip to send data, the slave SPI-CAN transceiver chip sends broadcast data to the master communication equipment and other slave communication equipment.
10. The slave communication device of claim 9, wherein the SPI interface comprises a chip select pin, a clock pin, a first data pin, and a second data pin, wherein the first data pin and the second data pin each represent a different data transmission mode;
the chip selection pin of the slave CPU is connected with the chip selection pin of the slave SPI-CAN transceiver chip, the clock pin of the slave CPU is connected with the clock pin of the slave SPI-CAN transceiver chip, the first data pin of the slave CPU is connected with the first data pin of the slave SPI-CAN transceiver chip, and the second data pin of the slave CPU is connected with the second data pin of the slave SPI-CAN transceiver chip.
11. A communication system comprising a master communication device according to any of claims 1-8 and at least two slave communication devices according to any of claims 9-10.
CN202320761626.9U 2023-04-03 2023-04-03 Master communication equipment, slave communication equipment and communication system Active CN220087303U (en)

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