CN219980789U - Operational amplifier circuit and operational amplifier chip - Google Patents

Abstract

The present utility model relates to the field of integrated circuits, and in particular, to an operational amplifier circuit and an operational amplifier chip. The operational amplifier circuit includes: a first-stage amplifying circuit having an input terminal, an output terminal, and a control terminal, the input terminal being configured to receive a pair of differential input signals and to output an amplified first-stage amplified signal from the output terminal thereof; the second-stage amplifying circuit is provided with an input end and an output end, the input end of the second-stage amplifying circuit is connected with the output end of the first-stage amplifying circuit, the second-stage amplifying circuit can amplify the received first-stage amplifying signal, and the acquired second-stage amplifying signal is fed back to the control end of the first-stage amplifying circuit through the output end of the second-stage amplifying circuit, so that the first-stage amplifying signal output by the first-stage amplifying circuit is increased until the second-stage amplifying signal is amplified to a preset gain. The utility model realizes the improvement of the gain of the operational amplifier circuit, and the bandwidth is not reduced because the output impedance of the operational amplifier circuit is not increased.

Description

Operational amplifier circuit and operational amplifier chip

Technical Field

The present utility model relates to the field of integrated circuits, and in particular, to an operational amplifier circuit and an operational amplifier chip.

Background

The operational amplifier circuit is an electronic integrated circuit with a multi-stage amplifying circuit, and the one-stage amplifying circuit is a differential amplifying circuit and has high input resistance; the second-stage amplifying circuit mainly performs voltage amplification, has high voltage amplification factor, and is generally composed of a common source amplifying circuit.

In order to increase the gain of an operational amplifier circuit, the prior art is generally implemented by increasing the output impedance of a transistor, but it results in a smaller bandwidth of the operational amplifier circuit.

Disclosure of Invention

In view of the above, it is necessary to provide an operational amplifier circuit and an operational amplifier chip that can secure a bandwidth while increasing a gain.

In a first aspect, an embodiment of the present utility model provides an operational amplifier circuit, including:

a first-stage amplifying circuit having an input terminal, an output terminal, and a control terminal, the input terminal being configured to receive a pair of differential input signals and to output an amplified first-stage amplified signal from the output terminal thereof; and

the second-stage amplifying circuit is provided with an input end and an output end, the input end of the second-stage amplifying circuit is connected with the output end of the first-stage amplifying circuit, the second-stage amplifying circuit can amplify the received first-stage amplifying signal, and the acquired second-stage amplifying signal is fed back to the control end of the first-stage amplifying circuit through the output end of the second-stage amplifying circuit, so that the first-stage amplifying signal output by the first-stage amplifying circuit is increased until the second-stage amplifying signal is amplified to a preset gain.

The received primary amplified signal is amplified by the secondary amplifying circuit, and the obtained secondary amplified signal is fed back to the control end of the primary amplifying circuit through the output end of the secondary amplifying circuit, so that the primary amplified signal output by the primary amplifying circuit is increased until the secondary amplified signal is amplified to a preset gain. The present embodiment achieves an improvement in gain of the operational amplifier circuit, and since the output impedance of the operational amplifier circuit is not increased, the bandwidth is not reduced.

In one embodiment, the first stage amplifying circuit includes:

a first-stage amplifying sub-circuit for outputting the first-stage amplifying signal according to the differential input signal;

the tail current source circuit is connected with the primary amplifying sub-circuit and is used for setting the preset gain;

the first active load circuit is connected with the primary amplifying sub-circuit and used as an active load of the primary amplifying sub-circuit;

the input end of the first active load circuit is connected with the output end of the second-stage amplifying circuit, and the impedance of the active load is correspondingly adjusted in response to the change of the second-stage amplifying signal, so that the first-stage amplifying signal is increased.

In an embodiment, the first-stage amplifying sub-circuit includes a first NMOS and a second NMOS connected with a common source, gates of the first NMOS and the second NMOS are input ends of the pair of differential input signals, substrates of sources of the first NMOS and the second NMOS are connected to a common ground, and a drain of the second NMOS is an output end of the first-stage amplifying circuit;

the tail current source circuit comprises a third NMOS tube and a fourth NMOS tube which are connected with a common source, and the sources of the third NMOS tube and the fourth NMOS tube are connected with a common ground; the grid electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube;

the first active load circuit comprises a first PMOS tube and a second PMOS tube which are connected with a common grid electrode, wherein the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrodes of the first PMOS tube and the second PMOS tube are configured to be connected with a power supply, and the grid electrodes of the first PMOS tube and the second PMOS tube are connected with the control end of the first-stage amplifying circuit and the output end of the second-stage amplifying circuit.

The tail current source circuit of the embodiment does not need an additional power supply bias circuit, so that the circuit of the operational amplifier is simpler. And the grid electrode of the first PMOS tube is connected with the output end of the secondary amplifying circuit, so that the loss of threshold voltage is avoided.

In one embodiment, the two-stage amplification circuit includes:

the secondary amplifying sub-circuit is connected with the primary amplifying circuit and is used for amplifying the primary amplifying signal and feeding the secondary amplifying signal back to the control end of the primary amplifying circuit through the output end of the secondary amplifying sub-circuit;

and the second active load circuit is connected with the secondary amplifying sub-circuit and used as an active load of the secondary amplifying sub-circuit.

In an embodiment, the second-stage amplifying sub-circuit includes a fifth NMOS transistor, a source electrode of the fifth NMOS transistor is connected to a common ground, a gate electrode of the fifth NMOS transistor is connected to an output end of the first-stage amplifying circuit, and a drain electrode of the fifth NMOS transistor is used as an output end of the second-stage amplifying signal;

the second active load circuit comprises a third PMOS tube, the grid electrode of the third PMOS tube is connected with the drain electrode and the control end of the primary amplifying circuit, and the source electrode of the third PMOS tube is connected with the common ground.

In an embodiment, the two-stage amplifying circuit further includes:

and the signal output circuit is connected with the secondary amplifying sub-circuit and is used for reducing the secondary amplifying signal output by the secondary amplifying sub-circuit.

The signal output circuit reduces the secondary amplified signal output by the secondary amplifying sub-circuit so as to reduce the influence of channel modulation effect and ensure the stability.

In an embodiment, the signal output circuit includes a sixth NMOS transistor, a source of the sixth NMOS transistor is connected to a gate of the fifth NMOS transistor, a drain of the sixth NMOS transistor is used as the output end of the second-stage amplified signal, and the gate of the sixth NMOS transistor is connected to the drain of the sixth NMOS transistor.

In an embodiment, the two-stage amplifying circuit further includes:

the compensation circuit comprises a first resistor and a first capacitor which are connected in series between the output end of the primary amplifying circuit and the output end of the secondary amplifying circuit.

A Miller compensation with a zero adjustment function is formed through the first resistor and the first capacitor, and is used for improving the stability of the operational amplifier circuit.

In a second aspect, an embodiment of the present utility model provides an operational amplifier circuit, including:

a first-stage amplifying circuit having an input terminal, an output terminal, and a control terminal, the input terminal being configured to receive a pair of differential input signals and to output an amplified first-stage amplified signal from the output terminal thereof; and

the two paths of second-stage amplifying circuits are respectively provided with an input end and an output end, the input ends of the two paths of second-stage amplifying circuits are connected with the output end of the first-stage amplifying circuit, the second-stage amplifying circuits can amplify received first-stage amplifying signals, and the acquired second-stage amplifying signals are fed back to the control end of the first-stage amplifying circuit through the output end of the second-stage amplifying circuit, so that the first-stage amplifying signals output by the first-stage amplifying circuit are increased until the second-stage amplifying signals are amplified to preset gains.

The operational amplifier circuit in the embodiment is provided with two paths of two-stage amplifier circuits, the two paths of two-stage amplifier circuits are symmetrical in structure, the gain of the operational amplifier circuit is improved, and the output impedance of the operational amplifier circuit is not increased, so that the bandwidth is not reduced.

In a third aspect, an embodiment of the present utility model provides an operational amplifier chip including an operational amplifier circuit as described in the first aspect or the second aspect.

The operational amplifier chip achieves an improvement in gain, and since the output impedance is not increased, the bandwidth is not reduced.

Drawings

Fig. 1 is a schematic diagram of an operational amplifier circuit according to a first embodiment of the present utility model;

FIG. 2 is a schematic circuit diagram of an operational amplifier circuit according to an embodiment of the present utility model;

FIG. 3 is a schematic circuit diagram of another operational amplifier circuit according to an embodiment of the present utility model;

FIG. 4 is a schematic circuit diagram of another operational amplifier circuit according to an embodiment of the present utility model;

FIG. 5 is a schematic diagram of an operational amplifier circuit according to another embodiment of the present utility model;

FIG. 6 is a circuit diagram of an operational amplifier circuit according to another embodiment of the present utility model;

FIG. 7 is a circuit diagram of another operational amplifier circuit according to another embodiment of the present utility model;

fig. 8 is a circuit diagram of another operational amplifier according to another embodiment of the present utility model.

Detailed Description

The present utility model will be described and illustrated with reference to the accompanying drawings and examples in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model. All other embodiments, which can be made by a person of ordinary skill in the art based on the embodiments provided by the present utility model without making any inventive effort, are intended to fall within the scope of the present utility model. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the utility model. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the described embodiments of the utility model can be combined with other embodiments without conflict.

Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this utility model belongs. The terms "a," "an," "the," and similar referents in the context of the utility model are not to be construed as limiting the quantity, but rather as singular or plural. The terms "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in connection with the present utility model are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means greater than or equal to two. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. The terms "first," "second," "third," and the like, as used herein, are merely distinguishing between similar objects and not representing a particular ordering of objects.

Fig. 1 is a schematic diagram of an operational amplifier circuit according to an embodiment of the utility model. The operational amplifier circuit includes: a first-stage amplification circuit 10 having an input terminal, an output terminal, and a control terminal, the input terminal being configured to receive a pair of differential input signals and to output an amplified first-stage amplified signal from the output terminal thereof; the second-stage amplifying circuit 20 has an input end and an output end, the input end of the second-stage amplifying circuit 20 is connected with the output end of the first-stage amplifying circuit 10, the second-stage amplifying circuit 20 can amplify the received first-stage amplifying signal, and the obtained second-stage amplifying signal is fed back to the control end of the first-stage amplifying circuit 10 through the output end of the second-stage amplifying circuit 20, so that the first-stage amplifying signal output by the first-stage amplifying circuit 10 is increased until the second-stage amplifying signal is amplified to a preset gain.

The received primary amplified signal is amplified by the secondary amplifying circuit, and the obtained secondary amplified signal is fed back to the control end of the primary amplifying circuit through the output end of the secondary amplifying circuit, so that the primary amplified signal output by the primary amplifying circuit is increased until the secondary amplified signal is amplified to a preset gain. The present embodiment achieves an improvement in gain of the operational amplifier circuit, and since the output impedance of the operational amplifier circuit is not increased, the bandwidth is not reduced.

In one embodiment, the first stage amplification circuit 10 includes: a primary amplifying sub-circuit 101 for outputting the primary amplified signal according to the differential input signal; a tail current source circuit 102 connected to the first-stage amplifying sub-circuit 101 for setting the preset gain; the first active load circuit 103 is connected to the first stage amplifying sub-circuit 101 and is used as an active load of the first stage amplifying sub-circuit.

The input end of the first active load circuit is connected with the output end of the second-stage amplifying circuit, and the impedance of the active load is correspondingly adjusted in response to the change of the second-stage amplifying signal, so that the first-stage amplifying signal is increased.

The secondary amplifying circuit 20 includes: a second-stage amplifying sub-circuit 201, connected to the first-stage amplifying circuit, for amplifying the first-stage amplified signal, and feeding back the second-stage amplified signal to the control end of the first-stage amplifying circuit 10 via the output end of the second-stage amplifying sub-circuit; and a second active load circuit 202 connected to the secondary amplifying sub-circuit 201 and used as an active load of the secondary amplifying sub-circuit 201.

In this embodiment, the primary amplifying sub-circuit 101 amplifies a pair of differential input signals and outputs a primary amplifying signal to the secondary amplifying sub-circuit 201, the secondary amplifying sub-circuit 201 amplifies the primary amplifying signal again and outputs the secondary amplifying signal, and the secondary amplifying signal is fed back to the secondary amplifying sub-circuit 201 after passing through the second active load circuit 202 and the first active load circuit 103, thereby realizing continuous amplification of the secondary amplifying signal. The tail current source circuit 102 controls the amplification of the secondary amplified signal to a preset gain, so as to avoid the excessive gain. The tail current source circuit 102 is also used for common mode feedback of the primary amplified signal.

Fig. 2 is a schematic circuit diagram of an operational amplifier circuit according to an embodiment of the present utility model. As shown in fig. 2, the first-stage amplifying sub-circuit 201 includes a first NMOS transistor NM1 and a second NMOS transistor NM2 connected with a common source, gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 are input ends of the pair of differential input signals, substrates of sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected to a common ground, and a drain of the second NMOS transistor NM2 is an output end of the first-stage amplifying circuit.

The tail current source circuit 202 includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4 connected with a common source, and sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are connected with a common ground; the gate of the third NMOS transistor NM3 is connected to the drain of the first NMOS transistor NM1, the gate of the fourth NMOS transistor NM4 is connected to the drain of the second NMOS transistor NM2, the drain of the third NMOS transistor NM3 is connected to the source of the first NMOS transistor NM1, and the drain of the fourth NMOS transistor NM4 is connected to the source of the second NMOS transistor NM 2.

The first active load circuit 203 includes a first PMOS tube PM1 and a second PMOS tube PM2 that are connected with a common gate, a drain of the first PMOS tube PM1 is connected with a drain of the first NMOS tube NM1, a drain of the second PMOS tube PM2 is connected with a drain of the second NMOS tube NM2, sources of the first PMOS tube PM1 and the second PMOS tube PM2 are configured to be connected with a power supply, and gates of the first PMOS tube PM1 and the second PMOS tube PM2 are connected with an output end of the second amplifying circuit with a control end of the first amplifying circuit.

The second-stage amplifying sub-circuit 201 includes a fifth NMOS transistor, a source electrode of the fifth NMOS transistor is connected to a common ground, a gate electrode of the fifth NMOS transistor is connected to an output end of the first-stage amplifying circuit, and a drain electrode of the fifth NMOS transistor is used as an output end of the second-stage amplifying signal.

The second active load circuit 202 includes a third PMOS transistor, where a gate of the third PMOS transistor is connected to a drain of the third PMOS transistor and to a control terminal of the first stage amplifying circuit, and a source of the third PMOS transistor is connected to a common ground.

The circuit configuration of the operational amplifier circuit is further analyzed as follows. The first NMOS transistor NM1 and the second NMOS transistor NM2 are differential pair transistors, gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 respectively receive a pair of differential input signals INN and INP, and drains of the first NMOS transistor NM1 and the second NMOS transistor NM2 form an output end of the first amplified signal. The gate of the fifth NMOS transistor NM5 receives the first-stage amplified signal, and the fifth NMOS transistor NM5 amplifies the first-stage amplified signal again and outputs the amplified signal to the output terminal Vout of the second-stage amplified signal through the drain.

After the differential input signal is amplified by the second NMOS transistor NM2, the increase of the gate voltage of the fifth NMOS transistor NM5 results in an increase of the drain current of the fifth NMOS transistor NM5, so that the drain voltage of the fifth NMOS transistor NM5 is reduced. Because the grid electrode of the second PMOS tube PM2 and the grid electrode of the third PMOS tube PM3 are connected with the output end Vout, the voltage of the grid electrode of the third PMOS tube PM3 and the grid electrode of the second PMOS tube PM2 is reduced, the drain current of the second PMOS tube PM2 is increased, and the drain current of the fifth NMOS tube NM5 is continuously increased.

Since positive feedback with a gain greater than 1 will lead to loop instability, it must be as close to 1 as possible in order to obtain a large gain. The aspect ratio of the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the second PMOS transistor PM2, and the third PMOS transistor PM3 needs to satisfy:

(W ₅ /L ₅ )＝4·(W ₄ /L ₄ )，(W ₇ /L ₇ )＝2·(W ₈ /L ₈ )

wherein W is ₅ Represents the width, L, of the fifth NMOS transistor NM5 ₅ Indicating the length of the fifth NMOS transistor NM 5; w (W) ₄ Represents the width, L, of the fourth NMOS transistor NM4 ₄ Indicating the length of the fourth NMOS transistor NM 4; w (W) ₇ Representing the width, L, of the third PMOS tube PM3 ₇ Indicating the length of the third PMOS tube PM3; w (W) ₈ Representing the width, L, of the second PMOS tube PM2 ₈ Indicating the length of the second PMOS tube PM2.

In addition, since the gate of the third NMOS transistor NM3 is connected to the drain of the first NMOS transistor NM1, the gate of the fourth NMOS transistor NM4 is connected to the drain of the second NMOS transistor NM 2. The increase of the drain current of the second PMOS transistor PM2 causes the increase of the gate voltage of the fourth NMOS transistor NM4, so that the drain voltage of the fourth NMOS transistor NM4 decreases, and after the drain voltage of the fourth NMOS transistor NM4 decreases, the drain voltage of the second NMOS transistor NM2 also decreases, thereby reducing the amount by which the gate voltage of the fourth NMOS transistor NM4 increases, and also controlling the amount by which the gate voltage of the fifth NMOS transistor NM5 increases, thereby controlling the amplification of the second amplified signal to a preset gain, which is as close to 1 as possible.

It should be further noted that, since the gate of the third NMOS transistor NM3 is connected to the drain of the first NMOS transistor NM1, and the gate of the fourth NMOS transistor NM4 is connected to the drain of the second NMOS transistor NM2, the tail current source circuit 102 does not need an additional power bias circuit, so that the circuit of the operational amplifier circuit is simpler.

In the conventional operational amplifier circuit, the gate of the first PMOS tube PM1 in the first active load circuit 103 is connected to the drain, and the drain voltage of the first PMOS tube PM1 is greatly lost due to the existence of the threshold voltage. In this circuit structure, since the gate of the first PMOS PM1 is connected to the output end of the second active load circuit 202, the loss of the threshold voltage is avoided. By improving the connection mode of the first PMOS tube PM1, the equivalent impedance of the output end of the primary amplified signal is smaller, and a smaller time constant is caused. Therefore, the bias current of the operational amplifier circuit can be effectively reduced under the condition of ensuring the bandwidth and the gain.

Fig. 3 is a schematic circuit diagram of another operational amplifier circuit according to an embodiment of the present utility model. As shown in fig. 3, the two-stage amplification circuit 20 further includes: and the signal output circuit 203 is connected with the secondary amplifying sub-circuit 201 and is used for reducing the secondary amplifying signal output by the secondary amplifying sub-circuit.

Specifically, the signal output circuit 203 includes a sixth NMOS transistor NM6, a source of the sixth NMOS transistor NM6 is connected to a gate of the fifth NMOS transistor NM5, a drain of the sixth NMOS transistor NM6 is used as the output end of the second-stage amplified signal, and a gate of the sixth NMOS transistor NM6 is connected to a drain of the sixth NMOS transistor NM 6.

It should be noted that, the second-stage amplified signal is reduced by the sixth NMOS transistor NM6, so that the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 have a closer V _DS Thereby reducing the influence of the channel modulation effect on the channel modulation effect and ensuring the stability.

Fig. 4 is a schematic circuit diagram of another operational amplifier according to an embodiment of the present utility model. As shown in fig. 4, the two-stage amplification circuit 20 further includes: the compensation circuit 204 includes a first resistor R1 and a first capacitor C1 connected in series between the output terminal of the primary amplification circuit 10 and the output terminal of the secondary amplification circuit 20. The first resistor R1 and the first capacitor C1 form a miller compensation with a zero adjustment function for improving the stability of the operational amplifier circuit.

Fig. 5 is a schematic diagram of an operational amplifier circuit according to another embodiment of the present utility model. The operational amplifier circuit includes:

a first-stage amplification circuit 10 having an input terminal, an output terminal, and a control terminal, the input terminal being configured to receive a pair of differential input signals and to output an amplified first-stage amplified signal from the output terminal thereof; and

the two paths of second-stage amplifying circuits (20, 20') are respectively provided with an input end and an output end, the input ends of the two paths of second-stage amplifying circuits are connected with the output end of the first-stage amplifying circuit, the second-stage amplifying circuits can amplify received first-stage amplifying signals, and the acquired second-stage amplifying signals are fed back to the control end of the first-stage amplifying circuit through the output end of the second-stage amplifying circuit, so that the first-stage amplifying signals output by the first-stage amplifying circuits are increased until the second-stage amplifying signals are amplified to preset gains.

The difference from the above-described embodiment is that the operational amplifier circuit in this embodiment has two-way two-stage amplifier circuits, and thus has outputs of two-way two-stage amplified signals. The two-way two-stage amplifying circuit has symmetrical structure, realizes the improvement of the gain of the operational amplifying circuit, and does not reduce the bandwidth because the output impedance of the operational amplifying circuit is not increased.

Fig. 6 is a circuit diagram of an operational amplifier circuit according to another embodiment of the present utility model. The first-stage amplifying circuit 10 includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first PMOS transistor PM1, and a second PMOS transistor PM2. The one-path two-stage amplifying circuit 20 comprises a fifth NMOS tube NM5 and a third PMOS tube PM3; the other two-stage amplifying circuit 20' includes a seventh NMOS transistor NM7 and a fourth PMOS transistor PM4. The two input ends of the operational amplifier circuit are INN and INP, and the two output ends are Vout_ N, vout _P.

Fig. 7 is a circuit diagram of another operational amplifier circuit according to another embodiment of the present utility model. As shown in fig. 7, the two-way two-stage amplifying circuit further includes: and two paths of signal output circuits are respectively connected with the two paths of two-stage amplifying sub-circuits. One path of signal output circuit 203 includes a sixth NMOS transistor NM6, and the other path of signal output circuit 203' includes an eighth NMOS transistor NM8.

Fig. 8 is a circuit diagram of another operational amplifier according to another embodiment of the present utility model. As shown in fig. 8, the operational amplifier circuit further includes: two-way compensation circuit. The one-way compensation circuit 204 includes a first resistor R1 and a first capacitor C1 connected in series between the output terminal of the first-stage amplification circuit 10 and the output terminal of the second-stage amplification circuit 20. The other compensation circuit 204 'includes a second resistor R2 and a second capacitor C2 connected in series between the output of the first-stage amplification circuit 10 and the output of the other second-stage amplification circuit 20'.

It should be noted that, the working principles and beneficial effects of the primary amplifying circuit, the secondary amplifying circuit, the signal output circuit and the compensating circuit are described in detail in the above embodiments, so that the description is omitted in this embodiment.

The embodiment of the utility model also provides an operational amplifier chip which comprises the operational amplifier circuit in the embodiment.

It should be noted that, the working principle and the beneficial effects of the operational amplifier circuit are described in detail in the above embodiments, so that the description is omitted in this embodiment.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the utility model, which are described in detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.

Claims (10)

1. An operational amplifier circuit, comprising:

a first-stage amplifying circuit having an input terminal, an output terminal, and a control terminal, the input terminal being configured to receive a pair of differential input signals and to output an amplified first-stage amplified signal from the output terminal thereof; and

the second-stage amplifying circuit is provided with an input end and an output end, the input end of the second-stage amplifying circuit is connected with the output end of the first-stage amplifying circuit, the second-stage amplifying circuit can amplify the received first-stage amplifying signal, and the acquired second-stage amplifying signal is fed back to the control end of the first-stage amplifying circuit through the output end of the second-stage amplifying circuit, so that the first-stage amplifying signal output by the first-stage amplifying circuit is increased until the second-stage amplifying signal is amplified to a preset gain.

2. The operational amplifier circuit of claim 1, wherein the primary amplifying circuit comprises:

a first-stage amplifying sub-circuit for outputting the first-stage amplifying signal according to the differential input signal;

the tail current source circuit is connected with the primary amplifying sub-circuit and is used for setting the preset gain;

the first active load circuit is connected with the primary amplifying sub-circuit and used as an active load of the primary amplifying sub-circuit;

the input end of the first active load circuit is connected with the output end of the second-stage amplifying circuit, and the impedance of the active load is correspondingly adjusted in response to the change of the second-stage amplifying signal, so that the first-stage amplifying signal is increased.

3. The operational amplifier circuit of claim 2, wherein the first stage amplifier sub-circuit comprises a first NMOS transistor and a second NMOS transistor connected at a common source, gates of the first NMOS transistor and the second NMOS transistor are input ends of the pair of differential input signals, substrates of sources of the first NMOS transistor and the second NMOS transistor are connected to a common ground, and a drain of the second NMOS transistor is an output end of the first stage amplifier circuit;

the tail current source circuit comprises a third NMOS tube and a fourth NMOS tube which are connected with a common source, and the sources of the third NMOS tube and the fourth NMOS tube are connected with a common ground; the grid electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube;

the first active load circuit comprises a first PMOS tube and a second PMOS tube which are connected with a common grid electrode, wherein the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrodes of the first PMOS tube and the second PMOS tube are configured to be connected with a power supply, and the grid electrodes of the first PMOS tube and the second PMOS tube are connected with the control end of the first-stage amplifying circuit and the output end of the second-stage amplifying circuit.

4. An operational amplifier circuit according to any one of claims 1 to 3, wherein the two-stage amplifying circuit comprises:

the secondary amplifying sub-circuit is connected with the primary amplifying circuit and is used for amplifying the primary amplifying signal and feeding the secondary amplifying signal back to the control end of the primary amplifying circuit through the output end of the secondary amplifying sub-circuit;

and the second active load circuit is connected with the secondary amplifying sub-circuit and used as an active load of the secondary amplifying sub-circuit.

5. The operational amplifier circuit of claim 4, wherein the second stage amplifying sub-circuit comprises a fifth NMOS transistor, a source electrode of the fifth NMOS transistor is connected to a common ground, a gate electrode of the fifth NMOS transistor is connected to an output end of the first stage amplifying circuit, and a drain electrode of the fifth NMOS transistor is used as an output end of the second stage amplifying signal;

the second active load circuit comprises a third PMOS tube, the grid electrode of the third PMOS tube is connected with the drain electrode and the control end of the primary amplifying circuit, and the source electrode of the third PMOS tube is connected with the common ground.

6. The operational amplifier circuit of claim 5, wherein the two-stage amplifier circuit further comprises:

and the signal output circuit is connected with the secondary amplifying sub-circuit and is used for reducing the secondary amplifying signal output by the secondary amplifying sub-circuit.

7. The operational amplifier circuit of claim 6, wherein the signal output circuit comprises a sixth NMOS transistor, a source of the sixth NMOS transistor is connected to a gate of the fifth NMOS transistor, a drain of the sixth NMOS transistor is used as the output terminal of the second-stage amplified signal, and a gate of the sixth NMOS transistor is connected to the drain of the sixth NMOS transistor.

8. The operational amplifier circuit of claim 4, wherein the two-stage amplifier circuit further comprises:

the compensation circuit comprises a first resistor and a first capacitor which are connected in series between the output end of the primary amplifying circuit and the output end of the secondary amplifying circuit.

9. An operational amplifier circuit, comprising:

a first-stage amplifying circuit having an input terminal, an output terminal, and a control terminal, the input terminal being configured to receive a pair of differential input signals and to output an amplified first-stage amplified signal from the output terminal thereof; and

the two paths of second-stage amplifying circuits are respectively provided with an input end and an output end, the input ends of the two paths of second-stage amplifying circuits are connected with the output end of the first-stage amplifying circuit, the second-stage amplifying circuits can amplify received first-stage amplifying signals, and the acquired second-stage amplifying signals are fed back to the control end of the first-stage amplifying circuit through the output end of the second-stage amplifying circuit, so that the first-stage amplifying signals output by the first-stage amplifying circuit are increased until the second-stage amplifying signals are amplified to preset gains.

10. An operational amplifier chip comprising an operational amplifier circuit according to any one of claims 1 to 9.