CN219980445U

CN219980445U - Switching circuit, control device, chip, battery management system and electric device

Info

Publication number: CN219980445U
Application number: CN202122066563.9U
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Zhuhai Maiju Microelectronics Co Ltd
Current assignee: Zhuhai Maiju Microelectronics Co Ltd
Priority date: 2020-09-01
Filing date: 2021-08-30
Publication date: 2023-11-07
Anticipated expiration: 2031-08-30
Also published as: CN114123372A; CN112398192A

Abstract

The present disclosure provides a switching circuit as a charge-discharge switching circuit and for controlling a charge current and/or a discharge current of a battery/cell, comprising: the MOS transistor comprises a first MOS transistor, a second MOS transistor and a switch, wherein the grid electrode of the first MOS transistor receives a first control signal so as to conduct on and off, the first MOS transistor is a low-voltage-resistant MOS transistor, the grid electrode of the second MOS transistor receives a second control signal so as to conduct on and off, the second MOS transistor is a high-voltage-resistant MOS transistor, one end of the switch is connected with the grid electrode of the second MOS transistor, the other end of the switch is connected with the source electrode of the second MOS transistor, and the switch is conducted so that the second MOS transistor is turned off before the first MOS transistor is turned off or is turned off at the same time as the first MOS transistor is turned off under the condition that the first MOS transistor is turned off. A control device, a chip, a battery management system and an electric device are also provided.

Description

Switching circuit, control device, chip, battery management system and electric device

Technical Field

The present disclosure relates to a switching circuit, a control device, a chip, a battery management system, and an electrical apparatus.

Background

In the battery system, overcharge and overdischarge of the battery not only reduce the service life of the battery, but also cause safety accidents of explosion and fire in severe cases. The battery is, for example, a lithium battery pack or the like.

Fig. 1 shows a conventional overcurrent detection method according to the prior art.

When the battery is normally discharged, the voltages of the output control signals OD and OC of the driving unit are about VDD, 5V or 15V, the control signals OD and OC are respectively connected to the gates (G) of the protection switch MOSFETs M1 and M2, at this time, M1 and M2 operate in the linear region, the drains (D) and sources (S) of M1 and M2 are equivalent to an on-resistance, and the on-resistance value is R _on 。

Discharge current I _dsg From the P-terminal to the B-terminal, the voltage at the P-terminal is higher, when the voltage difference between the P-terminal and the B-terminal is detected (I _dsg *R _on ) When a certain limit value is reached, the voltage of the control signal OD changes from VDD to VB- (B-terminal voltage), thereby turning off M1 and turning off the discharge path. The control signal OC may still remain at a potential such as VDD and M2 may still be in an on state.

Similarly, when the battery is normally charged, the gate voltages of M1, M2 are VDD. The current flows from the B-terminal to the P-terminal, the voltage at the P-terminal is lower, and when the voltage difference between the B-terminal and the P-terminal (I _chg *R _on ) When a certain limit value is reached, the voltage of the control signal OC is changed from VDD to VB-, for example, and M2 is turned off, thereby cutting off the charging path. The control signal OD may still be maintained such as VDD potential, M1 may still be in an on state.

In the circuit configuration shown in FIG. 1, during normal charging, the on-resistances R of M1, M2 _on Is connected in series in the circuit of the battery and the external charger, so that the power loss P caused by the on-resistance of M1 and M2 is generated when the system is charged _Loss ＝I _chg *[2*R _on ] ² This power loss directly translates into heating of the system. Thus, the temperature rise due to heat loss of M2 of M1 during system charging is Δt=p _Loss And/(c×m), where C is the system specific heat coefficient and m is the system mass.

Since the safe operating temperature of a lithium battery system is usually about 45 ℃, it is necessary to control the maximum value I of the charging current in order to control the system temperature rise due to the heat dissipation of the on-resistance of M1 and M2 of the system _chg(max) ＝P _Loss(max) /([2*R _on ] ² ) Thus, the charging current becomes small, and the charging time of the system tends to be prolonged.

Similarly, during discharge, the on-resistances R of M1 and M2 _on Is connected in series with the battery and the load (R _Load ) Heat loss P due to on-resistance of M1 and M2 _Loss ＝I _dsg *[2*R _on ] ² . This power loss reduces the efficiency of battery energy utilization and also limits the maximum discharge current. Δt=p due to heat loss of M1 and M2 when the system is discharged _Loss And/(c×m), where C is the system specific heat coefficient and m is the system mass. Since the safe operating temperature of a lithium battery system is usually about 45 ℃, it is necessary to control the maximum value I of the charging current in order to control the system temperature rise due to the heat dissipation of the on-resistance of M1 and M2 of the system _dsg(max) ＝P _Loss(max) /([2*R _on ] ² ). This will limit the maximum current that the battery system can output.

Disclosure of Invention

In order to solve one of the above technical problems, the present disclosure provides a charge-discharge switch circuit, a charge-discharge control device, a chip, a battery management system, and an electrical apparatus.

According to one aspect, a charge-discharge switching circuit for controlling a battery/battery charge current and/or discharge current comprises:

a first MOS transistor, wherein a grid electrode of the first MOS transistor receives a first control signal so as to be turned on and off, the first MOS transistor is a low-voltage-resistant MOS transistor, and a source electrode or a drain electrode of the first MOS transistor is connected with a battery side;

the grid electrode of the second MOS transistor receives a second control signal so as to be turned on and turned off, the second MOS transistor is a high-voltage-resistant MOS transistor, the source electrode or the drain electrode of the second MOS transistor is connected with an external load or an external charger side, and the drain electrode or the source electrode of the second MOS transistor is connected with the drain electrode or the source electrode of the first MOS transistor; and

and one end of the switch is connected with the grid electrode of the second MOS transistor, and the other end of the switch is connected with the source electrode of the second MOS transistor, so that when the first MOS transistor is turned off, the switch is turned on to enable the second MOS transistor to be turned off before the first MOS transistor is turned off or to be turned off while the first MOS transistor is turned off.

According to at least one embodiment of the present disclosure, the first MOS transistor is a discharging MOS transistor and the first control signal is a discharging control signal, the second MOS transistor is a charging MOS transistor and the second control signal is a charging control signal, a source of the first MOS transistor is connected to a battery side, a source of the second MOS transistor is connected to an external load or an external charger side, and a drain of the second MOS transistor is connected to a drain of the second MOS transistor.

According to at least one embodiment of the present disclosure, the first MOS transistor is a charge MOS transistor and the first control signal is a discharge control signal, the second MOS transistor is a discharge MOS transistor and the second control signal is a discharge control signal, a drain of the first MOS transistor is connected to a battery side, a drain of the second MOS transistor is connected to an external load or an external charger side, and a source of the second MOS transistor is connected to a source of the second MOS transistor.

According to at least one embodiment of the present disclosure, the battery side is a low voltage side of the battery, the external load or external charger side is a low voltage side of the external load or a low voltage side of the external charger, or the battery side is a high voltage side of the battery, and the external load or external charger side is a high voltage side of the external load or a high voltage side of the external charger.

According to at least one embodiment of the present disclosure, a high voltage protection diode is connected between the source and the drain of the first MOS transistor.

According to at least one embodiment of the present disclosure, the on-resistance of the first MOS transistor is smaller than the on-resistance of the second MOS transistor.

According to at least one embodiment of the present disclosure, the first MOS transistor and the second MOS transistor are NMOS transistors.

According to at least one embodiment of the present disclosure, the switch further includes a second resistor, wherein one end of the second resistor is connected to the gate of the switch NMOS transistor, and the other end of the second resistor is connected to the source of the switch NMOS transistor, the gate of the switch NMOS transistor is connected to the current signal, the drain of the switch NMOS transistor is connected to the gate of the second MOS transistor, and the source of the switch NMOS transistor is connected to the source of the second MOS transistor.

According to at least one embodiment of the present disclosure, the current signal is provided such that the second MOS transistor is turned off rapidly by a voltage developed across the second resistor when the second MOS transistor needs to be turned off.

According to at least one embodiment of the present disclosure, the first resistor further includes a first resistor, one end of the first resistor is connected to the gate of the second MOS transistor and the other end of the first resistor is connected to the source of the second MOS transistor.

According to at least one embodiment of the present disclosure, the switch further includes a second high voltage protection diode, the switch is an NMOS transistor for a switch, a positive terminal of the second high voltage protection diode is connected to a gate of the NMOS transistor for a switch and a negative terminal of the second high voltage protection diode is connected to a source of the NMOS transistor for a switch, the gate of the NMOS transistor for a switch is connected to a current signal, a drain of the NMOS transistor for a switch is connected to a gate of the second MOS transistor, and a source of the NMOS transistor for a switch is connected to a source of the second MOS transistor.

According to at least one embodiment of the present disclosure, the current signal is provided when it is required to turn off the second MOS transistor, which is rapidly turned off by a voltage formed on the second high voltage protection diode.

In accordance with at least one embodiment of the present disclosure, a first high voltage protection diode is further included, a positive terminal of the first high voltage protection diode being connected to a gate of the second MOS transistor and a negative terminal of the high voltage protection diode being connected to a source of the second MOS transistor.

According to at least one embodiment of the present disclosure, the switch is an N-channel junction field effect transistor, a gate of the N-channel junction field effect transistor is connected to a source of the second MOS transistor, a drain of the N-channel junction field effect transistor is connected to a gate of the second MOS transistor, and a source of the N-channel junction field effect transistor is connected to a source of the second MOS transistor.

According to at least one embodiment of the present disclosure, when it is desired to turn off the second MOS transistor, the N-channel junction field effect transistor is turned off rapidly so that the second MOS transistor is turned off rapidly.

According to another aspect, a charge-discharge control device for controlling a charge current and/or a discharge current of a battery/battery pack includes:

a charge-discharge switching circuit as described above; and

and the driving circuit is used for providing the first control signal and the second control signal.

a charge-discharge switching circuit as described above; and

and the driving circuit is used for providing the first control signal, the second control signal and the current signal.

According to at least one embodiment of the present disclosure, further comprising:

the voltage acquisition unit is used for acquiring the voltage of the battery/battery pack, and the detection circuit is used for detecting the charging current and/or the discharging current; and

and a control logic circuit which provides a control signal to the driving circuit based on a signal from the voltage acquisition unit and/or the detection circuit.

According to still another aspect, a chip is integrated with the charge-discharge switching circuit as described above, or with the charge-discharge control device as described above.

According to still another aspect, a battery management system is characterized by comprising the charge-discharge switch circuit as described above, or comprising the charge-discharge control device as described above, or comprising the chip as described above.

According to yet another aspect, an electrical device comprises:

a battery/battery pack for powering other components in the electrical device; and

the charge-discharge switching circuit as described above, or the charge-discharge control device as described above, or the chip as described above, or the battery management system as described above.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 shows a prior art battery management schematic.

Fig. 2 shows a schematic structure of a high withstand voltage transistor.

Fig. 3 shows a battery management schematic.

Fig. 4 shows a battery management schematic.

Fig. 5 shows a battery management schematic.

Fig. 6 shows a battery management schematic.

Fig. 7 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 10 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 11 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 12 shows a schematic diagram of an electrical device according to one embodiment of the present disclosure.

Detailed Description

The present disclosure is described in further detail below with reference to the drawings and the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant content and not limiting of the present disclosure. It should be further noted that, for convenience of description, only a portion relevant to the present disclosure is shown in the drawings.

In addition, embodiments of the present disclosure and features of the embodiments may be combined with each other without conflict. The technical aspects of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the exemplary implementations/embodiments shown are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Thus, unless otherwise indicated, features of the various implementations/embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concepts of the present disclosure.

The use of cross-hatching and/or shading in the drawings is typically used to clarify the boundaries between adjacent components. As such, the presence or absence of cross-hatching or shading does not convey or represent any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated components, and/or any other characteristic, attribute, property, etc. of a component, unless indicated. In addition, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While the exemplary embodiments may be variously implemented, the specific process sequences may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described. Moreover, like reference numerals designate like parts.

When an element is referred to as being "on" or "over", "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. For this reason, the term "connected" may refer to physical connections, electrical connections, and the like, with or without intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "under … …," under … …, "" under … …, "" lower, "" above … …, "" upper, "" above … …, "" higher "and" side (e.g., as in "sidewall"), etc., to describe one component's relationship to another (other) component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "below" … … can encompass both an orientation of "above" and "below". Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising," and variations thereof, are used in the present specification, the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof is described, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not as degree terms, and as such, are used to explain the inherent deviations of measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

In the battery management application environment, in the circuit structure shown in fig. 1, the transistors M1 and M2 must both adopt MOSFETs of high voltage-withstanding structure, the basic structure of which is shown in fig. 2, and the corresponding high voltage-withstanding MOSFET on-resistance R _DS,on The six parts are combined together, that is,

R _DS,on ＝R _s,metal +R _source +R _channel +R _drift +R _drain +R _d,metal 。

wherein R is _s,metal R is the source contact resistance _source Drift resistance of neutral region of source, R _channel Is the channel resistance, R _drift Is drift resistance of lightly doped voltage-resistant region, R _drain Drift resistance of neutral region of drain electrode, R _d,metal Is the drain contact resistance.

V _GS Is the gate-source voltage, V _Th C is the threshold on voltage of NMOSFET _ox Is the unit capacitance of the gate oxide layer, mu _n，ch Electron mobility, μ for NMOSFET channel _n，drift Electron mobility for voltage-resistant drift region, N _drift N-type impurity mobility, d, of the withstand voltage drift region _drift L is the depth of the vertical direction of the channel of the withstand voltage drift region _drift Length W of the voltage-resistant drift region in the direction of the channel _drift The BV is the Drain-Source (Drain-Source) breakdown voltage of the NMOSFET, and V is the voltage in volts (used to normalize the BV, where BV/V is a dimensionless physical quantity) for the width of the voltage-resistant drift region perpendicular to the channel direction.

A high-voltage-resistant NMOSFET (for example, the Source-Drain voltage resistance is greater than 10V) is equivalent to a low-voltage-resistant NMOSFET (for example, the Source-Drain voltage resistance is less than 5V), a long lightly doped voltage-resistant drift region (drift area) must be adopted in the device structure, and the higher the Drain-Source voltage resistance is, the higher the doping concentration N of the drift region _drift The lower the length L of the drift region _drift The longer.

From the above formula of the withstand voltage drift region resistance, it can be known that the higher the withstand voltage is, the more lightly doped withstand voltage drift region resistance R _drift The larger the on-resistance of the NMOSFET is increased. In general andin other words, for high voltage resistant NMOSFETs, the drift region resistance dominates.

In conventional protection switch circuit designs, 2 high withstand voltage MOSFETs in series must be employed.

In order to solve the problems existing in the prior art, for example, to solve the problems of power loss caused by a charging switch and a discharging switch, thereby affecting the performance of a battery system, etc., it is necessary to reduce the series on-resistance of MOSFETs in a current path. Therefore, only the MOSFET M1 or M2 shown in fig. 1 may be used in series with the current path, and one of the MOSFETs may be used as the charge switch and the discharge switch. Obviously, when one MOSFET is adopted, the on-resistance can be reduced by half, and the power consumption is reduced by half. But the following problems occur if a high voltage tolerant MOSFET is used.

The following will explain the case of employing one MOSFET as the charge switch and the discharge switch.

Fig. 3 shows a case where the battery is discharged. The charge/discharge switch is described by taking the case where only M1 is used and M2 is omitted as an example, and as shown in fig. 3, the source S of the MOS transistor M1 is connected to the B-terminal of the battery, the drain D of the MOS transistor M1 is connected to the P-terminal of the external load, and the MOS transistor M1 has a parasitic diode D1. The gate G of the MOS transistor M1 receives a control signal from the driving unit to turn on and off. Wherein the source S of the MOS transistor M1 is shorted to the substrate (Bulk, B terminal) of the MOS transistor M1. By using one MOS transistor M1, the on-resistance R of the charge-discharge switch will obviously be made _on Reduced to half.

When the battery discharges to an external load, the flow direction of current in the loop is as follows: discharge current I _dsg From the P-terminal to the B-terminal, the voltage at the B-terminal being higher than the voltage at the P-terminal, when the voltage difference between the P-terminal and the B-terminal is detected (I _dsg *R _on ) When a certain threshold is reached, the voltage of the control signal of the gate of the MOS transistor M1 changes from a high level (for example, VDD, the power supply voltage of the driving unit) to VP- (voltage of the P-terminal), thereby turning off the M1 and turning off the discharge path.

Fig. 4 shows a case of battery charging. The charge-discharge switch uses only M1 and omits M2For example, as shown in fig. 4, the source S of the MOS transistor M1 is connected to the B-terminal of the battery, the drain D of the MOS transistor M1 is connected to the P-terminal of the external load, and the MOS transistor M1 has a parasitic diode D1. The gate G of the MOS transistor M1 receives a control signal from the driving unit to turn on and off. Wherein the source S of the MOS transistor M1 is shorted to the substrate (Bulk, B terminal) of the MOS transistor M1. By using one MOS transistor M1, the on-resistance R of the charge-discharge switch will obviously be made _on Reduced to half.

When the battery is charged by an external charger, the flowing direction of the current in the loop is as follows: charging current I _chg From the B-terminal to the P-terminal, the voltage at the P-terminal being higher than the voltage at the B-terminal, when the voltage difference between the B-terminal and the P-terminal is detected (I _chg *R _on ) When a certain threshold is reached, the control signal voltage of the gate of the MOS transistor M1 is changed from a high level (VDD, drive circuit supply voltage) to VB-, i.e., the gate G and the source S are shorted, vg=vs=vb-.

D1 is a natural parasitic body diode of the MOSFET M1, the positive terminal (anode, P-type doping) of the parasitic diode D1 is the P-well (Bulk) of the MOSFET M1, and the negative terminal (cathode, N-type doping) of the parasitic diode D1 is the drain D of the MOSFET M1. Therefore, even if the voltage of the control signal of the gate G of the MOSFET M1 is VB-, the MOSFET M1 is turned off (the conductive channel is not formed), the charging current continues to flow through the parasitic diode D1, and the battery continues to be charged.

Therefore, due to the parasitic diode D1, the MOSFET M1 still cannot completely turn off the charging current in the case of the charging overcurrent.

The following description will be given for the case where the charge/discharge switch uses only M2 and omits M1.

Fig. 5 shows an example in the discharge case, as shown in fig. 5, the drain D of the MOS transistor M2 is connected to the B-terminal of the battery, and the source S of the MOS transistor M2 is connected to the P-terminal of the external load, the MOS transistor M2 having a parasitic diode D1. The gate G of the MOS transistor M2 receives a control signal from the driving unit to turn on and off. Wherein the source S of the MOS transistor M2 is shorted to the substrate (Bulk, B terminal) of the MOS transistor M2. By using a MOS transistor M2, the on-resistance R of the charge-discharge switch is obviously caused _on Reduced to half.

When the battery discharges to the load, the flow direction of the current in the loop is as follows: discharge current I _dsg From the P-terminal to the B-terminal, the voltage at the B-terminal is higher, when the voltage difference between the P-terminal and the B-terminal is detected (I _dsg *R _on ) When a certain threshold is reached, the voltage of the gate control signal of the MOS transistor M2 is changed from a high level (VDD, driving circuit supply voltage) to VP-, and the gate G and the source S are shorted, vg=vs=vp-. Although VG-vs=0, the conduction channel of M2 disappears. However, since the positive terminal of the parasitic diode D1 is the P-type substrate region (bulk) of the MOS transistor M2 and is connected to the source S, that is, the P-terminal, and the negative terminal of the D1 is connected to the drain D of the MOS transistor M2, the battery can still continue to discharge the load through the parasitic diode D1 of the MOS transistor M2, and the discharge path cannot be completely turned off.

Fig. 6 shows an example in the case of charging, as shown in fig. 5, the drain D of the MOS transistor M2 is connected to the B-terminal of the battery, and the source S of the MOS transistor M2 is connected to the P-terminal of the external load, the MOS transistor M2 having a parasitic diode D1. The gate G of the MOS transistor M2 receives a control signal from the driving unit to turn on and off. Wherein the source S of the MOS transistor M2 is shorted to the substrate (Bulk, B terminal) of the MOS transistor M2. By using a MOS transistor M2, the on-resistance R of the charge-discharge switch is obviously caused _on Reduced to half.

When the battery is charged by the external charger, the current in the loop flows in the following direction: charging current I _chg From the B-terminal to the P-terminal, the voltage at the P-terminal is higher, when the voltage difference between the B-terminal and the P-terminal is detected (I _chg *R _on ) When a certain threshold is reached, in order to turn off the MOS transistor M2, the voltage of the control signal of the MOS transistor M2 is changed from a high level (VDD, driving circuit supply voltage) to VB-, i.e., the gate G and the source S are shorted, vg=vs=vb-, and the conduction channel of the MOS transistor M2 disappears, so that the MOS transistor M2 is turned off.

From the description of fig. 3 to 6, it can be seen that, although the on-resistance can be reduced by using the MOS transistor M1 or M2 alone, the current path cannot be completely turned off when a case in which a charging current or a discharging current flows therethrough occurs.

The present disclosure provides the following technical solutions to combine the problems existing in the prior art. In the embodiment of the present disclosure, the MOS transistor is in the form of an NMOSFET, but it should be understood by those skilled in the art that the MOS transistor may also be in the form of a PMOSFET, where the principle is the same as the above description, and will not be described herein for brevity.

In the present disclosure, in order to reduce the on-resistance of the NMOS transistor in the current path, a mode of combining the low withstand voltage NMOS transistor with the high withstand voltage NMOS transistor is adopted, for example, in the following description, the discharge control switch is replaced with the low withstand voltage NMOS transistor, and the charge control switch still adopts the high withstand voltage NMOS transistor. Of course, it will be appreciated by those skilled in the art in light of the principles of the present disclosure that the charge control switch may also be replaced with a low withstand voltage NMOS transistor, while the discharge control switch still employs a high withstand voltage NMOS transistor.

The present disclosure provides a charge-discharge switching circuit for controlling a charge current and/or a discharge current of a battery/cell, comprising: a first MOS transistor, wherein a grid electrode of the first MOS transistor receives a first control signal so as to be turned on and off, the first MOS transistor is a low-voltage-resistant MOS transistor, and a source electrode or a drain electrode of the first MOS transistor is connected with a battery side; the grid electrode of the second MOS transistor receives a second control signal so as to be turned on and turned off, the second MOS transistor is a high-voltage-resistant MOS transistor, the source electrode or the drain electrode of the second MOS transistor is connected with an external load or an external charger side, and the drain electrode or the source electrode of the second MOS transistor is connected with the drain electrode or the source electrode of the second MOS transistor; and one end of the switch is connected with the grid electrode of the second MOS transistor, and the other end of the switch is connected with the source electrode of the second MOS transistor, so that when the first MOS transistor is turned off, the switch is turned on to enable the second MOS transistor to be turned off before the first MOS transistor is turned off or to be turned off simultaneously with the first MOS transistor being turned off.

Further, the first MOS transistor is a discharging MOS transistor and the first control signal is a discharging control signal, the second MOS transistor is a charging MOS transistor and the second control signal is a charging control signal, a source of the first MOS transistor is connected to a battery side, a source of the second MOS transistor is connected to an external load or an external charger side, and a drain of the second MOS transistor is connected to a drain of the second MOS transistor.

Further, the first MOS transistor is a charge MOS transistor and the first control signal is a discharge control signal, the second MOS transistor is a discharge MOS transistor and the second control signal is a discharge control signal, a drain of the first MOS transistor is connected to a battery side, a drain of the second MOS transistor is connected to an external load or an external charger side, and a source of the second MOS transistor is connected to a source of the second MOS transistor.

Further, the battery side is a low voltage side of the battery, the external load or external charger side is a low voltage side of the external load or a low voltage side of the external charger, or the battery side is a high voltage side of the battery, and the external load or external charger side is a high voltage side of the external load or a high voltage side of the external charger.

Further, the on-resistance of the first MOS transistor is smaller than the on-resistance of the second MOS transistor. Therefore, for the first MOS transistor and the second MOS transistor which are connected in series, the on-resistance of the series circuit of the first MOS transistor and the second MOS transistor is obviously reduced because the on-resistance of the first MOS transistor is far smaller than that of the second MOS transistor, so that the power consumption is obviously reduced. In addition, in the case where the first and second MOS transistors are identical in size specification, it is apparent that the on-resistance of the first MOS transistor of low withstand voltage is much smaller than the on-resistance of the second MOS transistor of high withstand voltage. Even if the on-resistance of the first MOS transistor is made equal to the on-resistance of the second MOS transistor in the case of different specifications, the manufacturing cost of the low withstand voltage first MOS transistor is much lower than that of the high withstand voltage second MOS transistor, so that the system cost can be effectively reduced.

Further, a high-voltage protection diode is connected between the source electrode and the drain electrode of the first MOS transistor.

The technical aspects of the present disclosure will be described below with reference to specific examples.

< first embodiment >

As shown in fig. 7, this embodiment provides a charge and discharge control device that may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a driving unit 40, and a charge and discharge control switch 50.

The VDD generator 10 may be connected to the highest voltage of the battery/battery pack so as to generate a voltage VDD required inside the charge and discharge control device according to the highest voltage.

The voltage acquisition unit 20 may be used to acquire the voltage of the battery/battery pack, and in the case of a battery pack, the voltage acquisition unit 20 may be used to acquire the voltage of each battery.

The logic control circuit 30 may generate a control signal based on the collected battery/stack voltage. Of course the logic control circuit 30 may additionally generate control signals depending on the charging current and the discharging current.

The driving unit 40 supplies a signal for driving the charge and discharge control switch 50 according to a control signal of the logic control circuit 30.

The charge/discharge control switch 50 controls the charge current and the discharge current according to the received switch control signal.

The charge and discharge control switch 50 may include a first low withstand voltage NMOS transistor 100 serving as a discharge switch, a high withstand voltage NMOS transistor 200 serving as a charge switch, and a switching NMOS transistor 300.

The first low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200 may be connected in series to the high voltage side of the battery/cell stack or to the low voltage side of the battery/cell stack, and the series order of the two is not limited.

In the present embodiment, the first low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200 are connected in series to the low voltage side of the battery/cell stack, and the source S of the first low withstand voltage NMOS transistor 100 is connected to the low voltage side of the battery/cell stack.

The gate of the first low withstand voltage NMOS transistor 100 receives the discharge control signal OD from the driving unit 40, the gate of the high withstand voltage NMOS transistor 200 receives the charge control signal OC from the driving unit 40, and the drain of the first low withstand voltage NMOS transistor 100 is connected to the drain of the high withstand voltage NMOS transistor 200. The first low withstand voltage NMOS transistor 100 has a first parasitic diode D1, and the high withstand voltage NMOS transistor 200 has a second parasitic diode D2.

The positive terminal of the first high voltage protection diode 102 is connected to the source of the first low voltage withstand NMOS transistor 100, and the negative terminal of the first high voltage protection diode 102 is connected to the drain of the first low voltage withstand NMOS transistor 100.

The drain of the switching NMOS transistor 300 is connected to the gate of the high withstand voltage NMOS transistor 200, and the source of the switching NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200. A first resistor 302 is connected between the source and drain of the switching NMOS transistor 300.

The gate of the switching NMOS transistor 300 receives the current signal OB from the driving unit 40, and the gate of the switching NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200 through the second resistor 304. The switching NMOS transistor 300 may be in the form of a low withstand voltage and may be made small in size.

The source of the first low withstand voltage NMOS transistor 100 is connected to the low voltage terminal B-of the battery/cell stack, and the source of the high withstand voltage NMOS transistor 200 is connected to the low voltage terminal P-of the external load or charger. Those skilled in the art will also appreciate that the source of the high withstand voltage NMOS transistor 200 is connected to the low voltage terminal B-of the battery/cell stack, while the source of the first low withstand voltage NMOS transistor 100 is connected to the low voltage terminal P-of the external load or charger, which also performs the same function. Likewise, its connection to the high voltage side of the battery/stack may also perform the same function.

According to an embodiment of the present disclosure, the first low withstand voltage NMOS transistor 100 has a withstand voltage ofThe value can be 1.8-7V, i.e. V _GS 、V _GD 、V _DS Can be 1.8-7V. The withstand voltage of the high withstand voltage NMOS transistor 200 is related to the voltage of the cells, which is typically 1.5-2 times the sum of the voltages of each cell, e.g., in the case of 16 cells, the voltage of each cell is typically 4.5V, the withstand voltage is required to be 4.5×16 (1.5-2), e.g., the withstand voltage is greater than 108V, i.e., V _GS 、V _GD 、V _DS Greater than 108V. According to the foregoing description, the on-resistance is related to the withstand voltage value, and thus the on-resistance of the first low withstand voltage NMOS transistor 100 may be significantly smaller than that of the high withstand voltage NMOS transistor 200. And the withstand voltage of the switching NMOS transistor 300 may be 10 to 20V.

With the design of the present disclosure, the first low withstand voltage NMOS transistor 100 is a low withstand voltage type transistor, if so, when the first low withstand voltage NMOS transistor 100 is turned off, if the high withstand voltage NMOS transistor 200 cannot be turned off in time during the turn-off (e.g., before or while the first low withstand voltage NMOS transistor 100 is turned off), the high withstand voltage NMOS transistor 200 remains in an on state, so that the voltage of the P-terminal will be applied to the drain of the first low withstand voltage NMOS transistor 100. Since the voltage of the P-terminal will rise to the voltage value of the p+ terminal during the turn-off of the first low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200.

Since the high withstand voltage NMOS transistor 200 cannot be turned off in time, a rising voltage value of the P-terminal is applied to the drain of the first low withstand voltage NMOS transistor 100, and since the first low withstand voltage NMOS transistor 100 is a low withstand voltage type transistor, if a high voltage is applied to the drain thereof, damage to the first low withstand voltage NMOS transistor 100 tends to be caused.

Thus, in this embodiment, by providing a switch (in the form of the switching NMOS transistor 300), the high withstand voltage NMOS transistor 200 is turned off in time during the turn-off (for example, before or simultaneously with the turn-off of the first low withstand voltage NMOS transistor 100). So that the voltage value of the rising P-terminal is not applied to the drain of the first low withstand voltage NMOS transistor 100 but to the drain of the high withstand voltage NMOS transistor 200 (since the high withstand voltage NMOS transistor 200 is a high withstand voltage type transistor, the high voltage does not cause damage to the high withstand voltage NMOS transistor 200).

In the actual high withstand voltage NMOS transistor 200, a parasitic capacitance exists between the gate G and the source S, and even when V is present due to the parasitic capacitance _GS In the case of less than the threshold voltage, the high withstand voltage NMOS transistor 200 cannot be turned off promptly because a certain time is required for the charge discharge of the capacitor, so that the high withstand voltage NMOS transistor 200 cannot be turned off promptly even in the case where the voltage of the control signal of the gate is less than the threshold voltage. The parasitic capacitance of the high withstand voltage NMOS transistor 200 requires a circuit with the first resistor 302 to realize discharge of the electric charges. In this case, there is necessarily a case where the high withstand voltage NMOS transistor 200 turns off with a delay.

In the present embodiment, the high withstand voltage NMOS transistor 200 is turned off rapidly (parasitic capacitance is discharged rapidly) by a switch connected in series between the gate and the source of the high withstand voltage NMOS transistor 200, so that the high withstand voltage NMOS transistor 200 needs to be turned off.

When the high withstand voltage NMOS transistor 200 needs to be turned off, the driving voltage provides a current signal OB, and the current OB flows through the second resistor 304, so that a voltage is formed through the second resistor 304, which is greater than the gate-source voltage V of the switching NMOS transistor 300 _GS The switching NMOS transistor 300 is rapidly turned on, so that a path is formed between the gate and the source of the high withstand voltage NMOS transistor 200, which rapidly discharges parasitic capacitance between the gate and the source of the high withstand voltage NMOS transistor 200, thereby rapidly turning off the high withstand voltage NMOS transistor 200. In this way, the rising P-terminal voltage is not applied to the drain of the first low withstand voltage NMOS transistor 100, and the first low withstand voltage NMOS transistor 100 is not damaged.

In addition, the purpose of the first high voltage protection diode 102 connected in series between the source and the drain of the first low voltage NMOS transistor 100 is that when the first low voltage NMOS transistor 100 is turned off and the high voltage NMOS transistor 200 is not turned off in time, the high voltage at the P-terminal will be applied to the drain of the first low voltage NMOS transistor 100, the first high voltage protection diode 102 will play a role in protection, and the high voltage will reverse breakdown the first high voltage protection diode 102, thereby avoiding the damage of the first low voltage NMOS transistor 100. This is because the first high voltage protection diode 102 is reverse-broken down, thereby avoiding that the drain voltage of the first low withstand voltage NMOS transistor 100 is not excessively high.

With the arrangement of the present embodiment, the on-resistance value of the series NMOS transistor from the B-terminal to the P-terminal is:

R _on ＝R _DS,on (100)+R _DS,on (200) Wherein R is _on R is the sum of the on-resistances of the first low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200 _DS,on (100) Is the on-resistance of the first low withstand voltage NMOS transistor 100, R _DS,on (200) Is the on-resistance of the high withstand voltage NMOS transistor 200.

Also, since the first low withstand voltage NMOS transistor 100 is a low withstand voltage NMOSFET, the physical structure of the low withstand voltage NMOSFET does not require a low doping withstand voltage drift region, that is, R for the low withstand voltage NMOSFET _DS,on (100)＝R _s,metal +R _source +R _channel +R _drain +R _d,metal 。

Therefore, R for NMOSFETs of the same physical size _DS,on (100) Far less than R _DS,on (200) R is then _on ≈R _DS,on (200). Therefore, the use of the high-low voltage NMOSFETs in series can reduce the on-resistance of the MOSFETs in series by 1 time, and thus the heat loss caused by the on-resistance is reduced by 2 times.

< second embodiment >

As shown in fig. 8, this embodiment provides a charge and discharge control device that may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a driving unit 40, and a charge and discharge control switch 50.

The drain of the switching NMOS transistor 300 is connected to the gate of the high withstand voltage NMOS transistor 200, and the source of the switching NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200. A second high voltage protection diode 306 is connected between the source and the drain of the switch NMOS transistor 300, wherein the positive terminal of the second high voltage protection diode 306 is connected to the source of the high voltage NMOS transistor 200, and the negative terminal of the second high voltage protection diode 306 is connected to the gate of the high voltage NMOS transistor 200. Thus, when a current flows from the positive terminal to the negative terminal of the second high voltage protection diode 306, the breakdown voltage is 6.5-7.5V, so that the gate-source voltage of the high voltage-resistant NMOS transistor 200 can be ensured to be greater than the threshold on voltage, and the high voltage-resistant NMOS transistor 200 is turned on.

The gate of the switching NMOS transistor 300 receives the current signal OB from the driving unit 40, and the gate of the switching NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200 through the third high voltage protection diode 308, wherein the positive terminal of the third high voltage protection diode 308 is connected to the source of the high withstand voltage NMOS transistor 200, and the negative terminal of the third high voltage protection diode 308 is connected to the source of the switching NMOS transistor 300. The switching NMOS transistor 300 may be a low withstand voltage diode and may be made small in size.

According to an embodiment of the present disclosure, the withstand voltage value of the first low withstand voltage NMOS transistor 100 may be 1.8 to 7V, i.e., V _GS 、V _GD 、V _DS Can be 1.8-7V. The withstand voltage of the high withstand voltage NMOS transistor 200 is related to the voltage of the cells, which is typically 1.5-2 times the sum of the voltages of each cell, e.g., in the case of 16 cells, the voltage of each cell is typically 4.5V, the withstand voltage is required to be 4.5×16 (1.5-2), e.g., the withstand voltage is greater than 108V, i.e., V _GS 、V _GD 、V _DS Greater than 108V. According to the foregoing description, the on-resistance is related to the withstand voltage value, and thus the on-resistance of the first low withstand voltage NMOS transistor 100 may be significantly smaller than that of the high withstand voltage NMOS transistor 200. And the withstand voltage of the switching NMOS transistor 300 may be 10 to 20V.

In the actual high withstand voltage NMOS transistor 200, a parasitic capacitance exists between the gate G and the source S, and even when V is present due to the parasitic capacitance _GS In the case of less than the threshold voltage, the high withstand voltage NMOS transistor 200 cannot be turned off promptly because of electricity The charge of the capacitor needs a certain time to be discharged, so that the high withstand voltage NMOS transistor 200 cannot be turned off promptly even if the voltage of the control signal of the gate is less than the threshold voltage. The parasitic capacitance of the high withstand voltage NMOS transistor 200 requires a circuit with the second high voltage protection diode 306 to achieve discharge of the charge. In this case, there is necessarily a case where the high withstand voltage NMOS transistor 200 turns off with a delay.

When the high withstand voltage NMOS transistor 200 needs to be turned off, the driving voltage provides a current signal OB, and the current OB flows through the third high voltage protection diode 308, so that a voltage (breakdown voltage is typically 6.5-7.5V when current exists from the positive terminal to the negative terminal) is formed through the third high voltage protection diode 308, and the voltage is greater than the gate-source voltage V of the switching NMOS transistor 300 _GS The switching NMOS transistor 300 is rapidly turned on, so that a path is formed between the gate and the source of the high withstand voltage NMOS transistor 200, which rapidly discharges parasitic capacitance between the gate and the source of the high withstand voltage NMOS transistor 200, thereby rapidly turning off the high withstand voltage NMOS transistor 200. In this way, the rising P-terminal voltage is not applied to the drain of the first low withstand voltage NMOS transistor 100, and the first low withstand voltage NMOS transistor 100 is not damaged.

In addition, the purpose of the first high voltage protection diode 102 connected in series between the source and the drain of the first low voltage NMOS transistor 100 is that when the first low voltage NMOS transistor 100 is turned off and the high voltage NMOS transistor 200 is not turned off in time, the high voltage at the P-terminal will be applied to the drain of the first low voltage NMOS transistor 100, the first high voltage protection diode 102 will play a role in protection, and the high voltage will reverse breakdown the first high voltage protection diode 102, thereby avoiding the damage of the first low voltage NMOS transistor 100.

The on-resistance of the series NMOS transistor from the B-terminal to the P-terminal is thus:

< third embodiment >

As shown in fig. 9, this embodiment provides a charge and discharge control device that may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a driving unit 40, and a charge and discharge control switch 50.

The drain of the N-channel junction field effect transistor 400 is connected to the gate of the high withstand voltage NMOS transistor 200, and the source of the N-channel junction field effect transistor 400 is connected to the source of the high withstand voltage NMOS transistor 200. A third resistor 404 is connected between the source and drain of the N-channel junction field effect transistor 400. The gate of the N-channel junction field effect transistor 400 is connected to the source of the high withstand voltage NMOS transistor 200. The N-channel junction field effect transistor 400 is a low withstand voltage N-channel junction field effect transistor.

According to an embodiment of the present disclosure, the withstand voltage value of the first low withstand voltage NMOS transistor 100 may be 1.8 to 7V, i.e., V _GS 、V _GD 、V _DS Can be 1.8-7V. The withstand voltage of the high withstand voltage NMOS transistor 200 is related to the voltage of the cells, which is typically 1.5-2 times the sum of the voltages of each cell, e.g., in the case of 16 cells, the voltage of each cell is typically 4.5V, the withstand voltage is required to be 4.5×16 (1.5-2), e.g., the withstand voltage is greater than 108V, i.e., V _GS 、V _GD 、V _DS Greater than 108V. According to the foregoing description, the on-resistance is related to the withstand voltage value, and thus the on-resistance of the first low withstand voltage NMOS transistor 100 may be significantly smaller than that of the high withstand voltage NMOS transistor 200. And the withstand voltage of the N-channel junction field effect transistor 400 may be 10 to 20V.

In the actual high withstand voltage NMOS transistor 200, a parasitic capacitance exists between the gate G and the source S, and even when V is present due to the parasitic capacitance _GS In the case of less than the threshold voltage, the high withstand voltage NMOS transistor 200 cannot be turned off promptly because a certain time is required for the charge discharge of the capacitor, so that the high withstand voltage NMOS transistor 200 cannot be turned off promptly even in the case where the voltage of the control signal of the gate is less than the threshold voltage. The parasitic capacitance of the high withstand voltage NMOS transistor 200 requires a circuit with the third resistor 404 to realize discharge of the electric charges. In this case, there is necessarily a case where the high withstand voltage NMOS transistor 200 turns off with a delay.

When the high withstand voltage NMOS transistor 200 needs to be turned off, the N-channel junction field effect transistor 400 is turned on rapidly, so that a path is formed between the gate and the source of the high withstand voltage NMOS transistor 200, so that the parasitic capacitance between the gate and the source of the high withstand voltage NMOS transistor 200 is discharged rapidly, and the high withstand voltage NMOS transistor 200 is turned off rapidly. In this way, the rising P-terminal voltage is not applied to the drain of the first low withstand voltage NMOS transistor 100, and the first low withstand voltage NMOS transistor 100 is not damaged.

< fourth embodiment >

As shown in fig. 10, this embodiment provides a charge and discharge control device that may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a driving unit 40, and a charge and discharge control switch 50.

The drain of the switching NMOS transistor 300 is connected to the gate of the high withstand voltage NMOS transistor 200, and the source of the switching NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200. A fourth high voltage protection diode 402 is connected between the source and the drain of the switch NMOS transistor 300, wherein the positive terminal of the fourth high voltage protection diode 402 is connected to the source of the high voltage NMOS transistor 200, and the negative terminal of the fourth high voltage protection diode 402 is connected to the gate of the high voltage NMOS transistor 200.

In the actual high withstand voltage NMOS transistor 200, a parasitic capacitance exists between the gate G and the source S, and even when V is present due to the parasitic capacitance _GS If the threshold voltage is smaller than the threshold voltage, the high withstand voltage NMOS transistor 200 cannot be turned off rapidly, because A certain time is required for the charge release of the capacitor, so that the high withstand voltage NMOS transistor 200 cannot be turned off promptly even in the case where the voltage of the control signal of the gate is less than the threshold voltage. The parasitic capacitance of the high withstand voltage NMOS transistor 200 needs a circuit with the fourth high voltage protection diode 402 to realize discharge of the electric charges. In this case, there is necessarily a case where the high withstand voltage NMOS transistor 200 turns off with a delay.

R _on ＝R _DS,on (100)+R _DS,on (200) Wherein R is _on R is the sum of the on-resistances of the first low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200 _DS,on (100) Is the on-resistance of the first low withstand voltage NMOS transistor 100, R _DS,on (200) Is a high withstand voltage NMOS crystalOn-resistance of body tube 200.

According to another embodiment of the present disclosure, a chip is provided that is integrated with the charge-discharge control switch circuit as described above, such as the portion shown at reference numeral 50 in fig. 11. The chip may also incorporate a charge and discharge control device as described above, such as the one shown in fig. 1 at reference numeral 1000.

According to another embodiment of the present disclosure, the battery management system includes the charge and discharge control switch circuit as described above, or includes the charge and discharge control device as described above.

As shown in fig. 12, the present disclosure also provides an electrical device that may include a battery/battery pack for powering other components in the electrical device; the electrical device may also include a charge-discharge control switch circuit, charge-discharge control means or chip as described above.

In the description of the present specification, reference to the terms "one embodiment/manner," "some embodiments/manner," "example," "a particular example," "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/manner or example is included in at least one embodiment/manner or example of the application. In this specification, the schematic representations of the above terms are not necessarily for the same embodiment/manner or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/modes or examples described in this specification and the features of the various embodiments/modes or examples can be combined and combined by persons skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

It will be appreciated by those skilled in the art that the above-described embodiments are merely for clarity of illustration of the disclosure, and are not intended to limit the scope of the disclosure. Other variations or modifications will be apparent to persons skilled in the art from the foregoing disclosure, and such variations or modifications are intended to be within the scope of the present disclosure.

Claims

1. A switching circuit which is a charge/discharge switching circuit and which is used for controlling a charge current and/or a discharge current of a battery/cell, comprising:

2. The switching circuit of claim 1 wherein the first MOS transistor is a discharging MOS transistor and the first control signal is a discharging control signal, the second MOS transistor is a charging MOS transistor and the second control signal is a charging control signal, a source of the first MOS transistor is connected to a battery side, a source of the second MOS transistor is connected to an external load or an external charger side, and a drain of the second MOS transistor is connected to a drain of the second MOS transistor.

3. The switching circuit of claim 1 wherein the first MOS transistor is a charge MOS transistor and the first control signal is a discharge control signal, the second MOS transistor is a discharge MOS transistor and the second control signal is a discharge control signal, a drain of the first MOS transistor is connected to a battery side, a drain of the second MOS transistor is connected to an external load or an external charger side, and a source of the second MOS transistor is connected to a source of the second MOS transistor.

4. The switching circuit according to claim 1, wherein,

the battery side is the low voltage side of the battery, the external load or external charger side is the low voltage side of the external load or the low voltage side of the external charger, or

The battery side is a high voltage side of the battery, and the external load or the external charger side is a high voltage side of the external load or a high voltage side of the external charger.

5. The switching circuit according to claim 1, wherein a high voltage protection diode is connected between a source and a drain of the first MOS transistor.

6. The switching circuit of claim 1 wherein the on-resistance of the first MOS transistor is less than the on-resistance of the second MOS transistor.

7. The switching circuit of claim 6 wherein the first MOS transistor and the second MOS transistor are NMOS transistors.

8. The switching circuit according to any one of claims 1 to 7, further comprising a second resistor, wherein the switch is an NMOS transistor for a switch, one end of the second resistor is connected to a gate of the NMOS transistor for a switch and the other end of the second resistor is connected to a source of the NMOS transistor for a switch, the gate of the NMOS transistor for a switch is connected to a current signal, the drain of the NMOS transistor for a switch is connected to a gate of a second MOS transistor, and the source of the NMOS transistor for a switch is connected to a source of the second MOS transistor.

9. The switching circuit of claim 8 wherein the current signal is provided when a second MOS transistor is required to be turned off, the second MOS transistor being rapidly turned off by a voltage developed across the second resistor.

10. The switching circuit of claim 8 further comprising a first resistor having one end connected to a gate of the second MOS transistor and another end connected to a source of the second MOS transistor.

11. The switching circuit according to any one of claims 1 to 7, further comprising a second high voltage protection diode, wherein the switch is an NMOS transistor for switch, a positive terminal of the second high voltage protection diode is connected to a gate of the NMOS transistor for switch and a negative terminal of the second high voltage protection diode is connected to a source of the NMOS transistor for switch, the gate of the NMOS transistor for switch is connected to a current signal, a drain of the NMOS transistor for switch is connected to a gate of the second MOS transistor, and a source of the NMOS transistor for switch is connected to a source of the second MOS transistor.

12. The switching circuit of claim 11 wherein the current signal is provided when a second MOS transistor is required to be turned off, the second MOS transistor being turned off rapidly by a voltage developed across the second high voltage protection diode.

13. The switching circuit of claim 11 further comprising a first high voltage protection diode, a positive terminal of the first high voltage protection diode being connected to a gate of the second MOS transistor and a negative terminal of the high voltage protection diode being connected to a source of the second MOS transistor.

14. The switching circuit according to any one of claims 1 to 7, wherein the switch is an N-channel junction field effect transistor, a gate of the N-channel junction field effect transistor is connected to a source of a second MOS transistor, a drain of the N-channel junction field effect transistor is connected to a gate of the second MOS transistor, and a source of the N-channel junction field effect transistor is connected to a source of the second MOS transistor.

15. The switching circuit of claim 14 wherein when a second MOS transistor is required to be turned off, the N-channel junction field effect transistor is turned off rapidly such that the second MOS transistor is turned off rapidly.

16. The switching circuit of claim 12 further comprising a first resistor having one end connected to a gate of the second MOS transistor and another end connected to a source of the second MOS transistor.

17. The switching circuit of claim 14 further comprising a first high voltage protection diode, a positive terminal of the first high voltage protection diode being connected to a gate of the second MOS transistor and a negative terminal of the high voltage protection diode being connected to a source of the second MOS transistor.

18. A control device for controlling a charge current and/or a discharge current of a battery/battery pack, comprising:

the switching circuit of any one of claims 1 to 17; and

19. A control device for controlling a charge current and/or a discharge current of a battery/battery pack, comprising:

a switching circuit according to any one of claims 8 to 13; and

20. The control device according to claim 18 or 19, characterized by further comprising:

21. A chip, characterized in that it is integrated with a switching circuit according to any one of claims 1 to 17 or with a control device according to any one of claims 18 to 20.

22. A battery management system comprising a switching circuit as claimed in any one of claims 1 to 17, or comprising a control device as claimed in any one of claims 18 to 20, or comprising a chip as claimed in claim 21.

23. An electrical device, comprising:

a battery/battery pack for supplying power; and

the switching circuit according to any one of claims 1 to 17, or the control device according to any one of claims 18 to 20, or the chip according to claim 21, or the battery management system according to claim 22.