CN219873519U - Lead frame and semiconductor device for improving coating layering - Google Patents

Abstract

The utility model discloses a lead frame and a semiconductor device for improving layering of a plating layer, which comprise a die bonding pad, a semiconductor chip, a first pin, a second pin, a third pin, an electric connection structure and a plastic package body, wherein the semiconductor chip is arranged on the die bonding pad, the first pin and the second pin are arranged on the first side of the die bonding pad, the third pin is arranged on the second side of the die bonding pad, the electric connection structure is used for connecting the semiconductor chip with the first pin, the second pin and the third pin, the plastic package body is used for encapsulating the die bonding pad, the semiconductor chip, the first pin, the second pin, the third pin and the electric connection structure, a slide glass area and a first plating layer area which is arranged in the slide glass area and is smaller than the slide glass area are formed on the first surface of the die bonding pad, the first plating layer area is coated with a plating layer, and the semiconductor chip is configured in the slide glass area and is in electric contact with the plating layer. Compared with the prior art, the semiconductor device has the advantages of simple structure and high reliability, and can effectively prevent layering among interfaces of the lead frame, the semiconductor chip and the plastic package body.

Description

Lead frame and semiconductor device for improving coating layering

Technical Field

The utility model relates to the technical field of semiconductor devices, in particular to a lead frame for improving coating layering and a semiconductor device.

Background

In electronic packages, interface delamination is a major aspect of package performance reliability evaluation. Delamination is a tiny peeling or cracking between interfaces inside the package, generally above 1-2um, and mainly occurs between the package resin and the chip interface, between the package resin and the frame pad, between the package resin and the frame interface, between the chip and the silver paste interface, between the silver paste and the lead frame interface, and the like, thereby affecting the conductivity between the chip and the frame, resulting in reduced reliability of the packaged product.

In the existing packaging product, in order to increase the conductivity between the chip and the frame, the chip is usually installed after the whole silver plating is carried out on the frame, but under the current packaging technical condition, the whole process needs to carry out reflow on the chip and the frame for a plurality of times, when the reflow is carried out, the internal stress change of the packaging resin and the steam pressure change of internal moisture can be caused when the environment temperature of the packaging body changes, and the steam pressure change is larger than the bonding force between the packaging resin and the chip, the frame bonding pad and the frame surface, thereby peeling and cracks are caused between the packaging resin and the interface between the chip and the frame, the conductivity between the chip and the frame is reduced, and the reliability of the packaging product is poor.

Disclosure of Invention

Accordingly, the present utility model is directed to a lead frame and a semiconductor device with improved plating delamination, which solve the problems of low conductivity between the chip and the frame and poor reliability of the packaged product caused by the easy peeling and cracking between the chip and the frame interface in the prior art.

In order to achieve the above-mentioned object, the present utility model provides a lead frame for improving plating delamination, comprising at least one frame unit, wherein the frame unit comprises a frame having a process hole formed therethrough, a die pad formed in the process hole and connected to the frame, a first lead and a second lead disposed on a first side of the die pad and connected to the frame, and a third lead disposed on a second side opposite to the first side of the die pad and connected to the frame; the first surface of the die pad is formed with a carrier region and a first plating region which is positioned in the carrier region and has an area smaller than that of the carrier region.

Further, the inner wall of the process hole is provided with a first inner side wall and a second inner side wall which are oppositely arranged, one ends of the first pin and the second pin are connected to the first inner side wall, the other opposite ends of the first pin and the second pin are arranged at intervals with the first side of the die bonding pad, one end of the third pin is connected to the second inner side wall, and the other opposite end of the third pin is connected to the second side of the die bonding pad or is arranged at intervals with the die bonding pad.

Further, the first pin includes a first connecting rib parallel to the first inner side wall and a plurality of first leads connected between the first connecting rib and the first inner side wall, the first leads are parallel to the second pin and physically separated from the second pin, and one end of each first lead is connected with the first connecting rib, and the other end of each first lead is connected with the first inner side wall.

Further, the third pin includes a plurality of second leads disposed between the second side of the die pad and the second inner sidewall, the plurality of second leads are disposed parallel to each other, and one end of the second lead is connected to the second side of the die pad, and the other end is connected to the second inner sidewall;

or (b)

The third pin comprises a second connecting rib parallel to the second inner side wall and a plurality of third leads connected between the second connecting rib and the second inner side wall, the third leads are mutually parallel, one end of each third lead is connected with the second connecting rib, and the other end of each third lead is connected with the second inner side wall.

Further, the inner wall of the process hole is further provided with a third inner side wall and a fourth inner side wall which are arranged between the first inner side wall and the second inner side wall and are oppositely arranged, the die pad is further provided with a third side which is opposite to the third inner side wall and a fourth side which is opposite to the fourth inner side wall, and the third side and/or the fourth side of the die pad are integrally and outwards extended to form reinforcing ribs which are connected to the third inner side wall and/or the fourth inner side wall of the corresponding side.

Further, the first surface of the die pad is further formed with at least one second plating region located in the carrier region and independent of the first plating region, and the total area of the first plating region and the second plating region is smaller than the area of the carrier region.

In order to achieve the above object, another aspect of the present utility model provides a semiconductor device, including a die pad, a semiconductor chip mounted on the die pad, a first lead and a second lead disposed on a first side of the die pad, a third lead disposed on a second side of the die pad, an electrical connection structure connecting the semiconductor chip and the first lead, the second lead and the third lead, and a plastic package encapsulating the die pad, the semiconductor chip, the first lead, the second lead, the third lead and the electrical connection structure, wherein a carrier region and a first plating region disposed in the carrier region and having an area smaller than that of the carrier region are formed on a first surface of the die pad, the first plating region is coated with a plating layer, and the semiconductor chip is disposed in the carrier region and is in electrical contact with the plating layer.

Further, the semiconductor chip comprises a first part mounted on the slide area and a second part integrally formed on the first part, and a step is formed on the periphery of the first part beyond the outer side wall of the second part.

Further, the first pin, the second pin and the third pin are provided with welding pins which extend towards the direction far away from the die bonding pad and are exposed outside the plastic package body, and the surfaces of the welding pins are electroplated with electroplating coatings.

Further, the die pad is made of a copper frame, and the plating layer is a silver plating layer or a tin plating layer.

According to the utility model, the slide area is arranged on the die bonding pad, and the first plating layer area with the area smaller than that of the slide area is arranged in the slide area, so that the semiconductor chip is welded in the slide area, the bonding force between the slide area and the plastic package body is superior to that of the slide area due to the first plating layer area, and meanwhile, the bonding force among the lead frame, the semiconductor chip and the plastic package body and the conductivity among the lead frame and the semiconductor chip are considered, thereby improving the layering problem among all structural interfaces inside the semiconductor device and improving the reliability of the semiconductor device.

Drawings

Fig. 1 is a schematic view showing a structure of a lead frame for improving plating delamination according to a preferred embodiment of the present utility model.

Fig. 2 is a schematic structural view of a lead frame for improving plating delamination according to another embodiment of the present utility model.

Fig. 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present utility model.

Fig. 4 is an internal structural view of fig. 3.

The specification reference numerals are as follows:

the frame unit 10, the frame 11, the process hole 11a, the first inner sidewall 11b, the second inner sidewall 11c, the third inner sidewall 11d, the fourth inner sidewall 11e, the die pad 20, the carrier region 20a, the first plating region 20b, the second plating region 20c, the stiffener 21, the semiconductor chip 30, the step 31, the first lead 40, the first connection rib 41, the first lead 42, the second lead 50, the third lead 60, the second lead 61, the second connection rib 62, the third lead 63, the electrical connection structure 70, the plastic package 80, and the conductive paste 90.

Detailed Description

The following is a further detailed description of the embodiments:

examples

According to a preferred embodiment of the present utility model, a lead frame for improving plating delamination is provided, which includes a die pad 20 having a carrier region 20a and a first plating region 20b, wherein the first plating region 20b has a smaller area than the carrier region 20a and is located in the carrier region 20a, so that the delamination problem among the die pad 20, the semiconductor chip 30 and the plastic package 80 can be improved, and the reliability of the semiconductor device can be improved.

Referring to fig. 1, a schematic structure of a lead frame for forming a packaged semiconductor device with improved plating delamination according to an embodiment of the utility model is shown. The lead frame comprises at least one frame unit 10, and in particular, the lead frame generally comprises a plurality of frame units 10 distributed in an array, the lead frame is integrally stamped by copper strips to form a copper frame, and after the semiconductor device is packaged, the connected copper frame is cut into separate single semiconductor devices.

The frame unit 10 includes a frame 11, a die pad 20, a first lead 40, a second lead 50, and a third lead 60. The frame 11 is formed with a process hole 11a penetrating up and down, the first, second and third leads 40, 50 and 60 surround the die pad 20, and the die pad 20, the first, second and third leads 40, 50 and 60 are all located in the process hole 11a and connected to the frame 11. The frame 11 is used to provide mechanical support for the die pad 20, the first pin 40, the second pin 50, and the third pin 60 during packaging of the semiconductor device, but the frame 11 does not form part of the packaged semiconductor device.

In this embodiment, the process hole 11a is rectangular, the inner wall of the process hole 11a has a first inner sidewall 11b and a second inner sidewall 11c which are oppositely disposed, and a third inner sidewall 11d and a fourth inner sidewall 11e which are oppositely disposed and are disposed between the first inner sidewall 11b and the second inner sidewall 11c, that is, the first inner sidewall 11b, the third inner sidewall 11d, the second inner sidewall 11c and the fourth inner sidewall 11e sequentially intersect to form a 90 ° angle, so as to form the rectangular process hole 11a. It will be appreciated that in other embodiments, the process hole 11a may be configured in a different geometry, such as triangular, circular, polygonal, etc., such that the inner wall thereof does not necessarily consist of the first through fourth inner side walls 11e, but may also include a smaller or larger number of inner side walls; moreover, the included angle formed by the intersection of the inner side walls can also be a non-vertical angle, such as an acute angle, an obtuse angle, a round angle and the like.

The die pad 20 is disposed at a central position of the process hole 11a, and the geometric center of the die pad 20 may or may not coincide with the center of the process hole 11a, which may be determined according to the packaging parameters of the semiconductor device.

In this embodiment, the die pad 20 is substantially rectangular, and the outer periphery of the die pad 20 has a first side and a second side disposed opposite to each other, and a third side and a fourth side disposed between the first side and the second side and disposed opposite to each other. The first side of the die pad 20 is opposite to and spaced apart from the first inner sidewall 11b, the second side is opposite to and spaced apart from the second inner sidewall 11c, the first and second leads 40 and 50 are disposed on the first side of the die pad 20, and the third lead 60 is disposed on the second side of the die pad 20. The third and/or fourth sides of the die pad 20 are physically and correspondingly connected to the third and fourth inner side walls 11d and 11e; preferably, the third and/or fourth sides of the die pad 20 are integrally formed with ribs 21 extending outwardly therefrom, one end of the ribs 21 being connected to the third and fourth sides of the die pad 20 and the other end being connected to the third and fourth inner wall sides of the corresponding sides to enable the die pad 20 to be connected to the frame 11, thereby providing mechanical support to the die pad 20 through the frame 11. It is understood that in other embodiments, the die pad 20 may be configured in other geometric shapes, which may or may not be similar in shape to the structure of the process hole 11a.

The die pad 20 has a first surface and a second surface disposed opposite one another in the top-to-bottom direction, and the first surface of the die pad 20 is also the upper surface of the die pad 20, and the second surface is the lower surface of the die pad 20, for example. A carrier region 20a and a first plating region 20b are provided on the first surface of the die pad 20, the carrier region 20a being for supporting the semiconductor chip 30, the first plating region 20b being for improving conductivity between the semiconductor chip 30 and the die pad 20 after plating. The first plating region 20b is located in the carrier region 20a, and the area of the first plating region 20b is smaller than that of the carrier region 20a, so that the carrier region 20a has an area where plating is not performed.

In this embodiment, the plating layer of the first plating layer region 20b is a silver plating layer, and the die pad 20 (or the entire lead frame) is made of a copper frame, so that the region where no plating layer is performed on the die pad 20 is bare copper, the semiconductor chip 30 is in contact with the die pad 20 through the silver plating layer, the conductivity of the silver plating layer is superior to copper, and the bonding property of copper with the encapsulation resin (i.e., the plastic package 80 described below) is superior to the silver plating layer, thereby improving the problem of delamination between the semiconductor chip 30 and the die pad 20 and the interface of the plastic package 80 while ensuring the conductivity of the semiconductor device.

Preferably, at least one second plating region 20c is further formed on the first surface of the die pad 20 and in the corresponding carrier region 20a, the second plating region 20c is independent from the first plating region 20b, i.e. the second plating region 20c is not coincident with the first plating region 20b, and the second plating region 20c is also plated with a silver plating to increase the conductivity. In this embodiment, the area of the second plating layer region 20c may be the same as or different from that of the first plating layer region 20b, and when a plurality of second plating layer regions 20c are provided, the plurality of second plating layer regions 20c may be distributed in an array or randomly and non-coincident with the first plating layer region 20b, and meanwhile, the total area of the first plating layer region 20b and the second plating layer region 20c is smaller than that of the carrier region 20a, so that the carrier region 20a always has an area where no plating is performed to contact with the plastic package 80 and/or the chip. It is to be understood that, in the present embodiment, the second plating region 20c is not necessary, and in a specific implementation, only the first plating region 20b may be provided to electrically contact the semiconductor chip 30 and the die pad 20.

The first leads 40 are disposed on a first side of the die pad 20 and are connected to the frame 11. Specifically, one end of the first pin 40 is connected to the first inner sidewall 11b, and the other end of the first pin 40 is spaced from the first side of the die pad 20, that is, the corresponding end of the first pin 40 is physically separated from the first side of the die pad 20. The first pin 40 includes a first connecting rib 41 parallel to the first inner sidewall 11b and a plurality of first leads 42 connected between the first connecting rib 41 and the first inner sidewall 11b, the plurality of first leads 42 are connected together by the first connecting rib 41, one end of the first lead 42 is connected with the first connecting rib 41, and the other end of the first lead 42 is connected with the first inner sidewall 11 b. The first connection ribs 41 are disposed opposite to and spaced apart from the first side of the die pad 20 and physically separated from the die pad 20, the plurality of first leads 42 are disposed between the first connection ribs 41 and the first inner sidewall 11b at uniform intervals, and the plurality of first leads 42 are disposed parallel to the second pins 50 and physically separated from the second pins 50 to draw out signals of the semiconductor chip 30 after the semiconductor chip 30 is assembled.

The second pins 50 are disposed on the first side of the die pad 20 and are connected to the frame 11. Specifically, one end of the second pin 50 is connected to the first inner sidewall 11b, and the other end of the second pin 50 is spaced apart from the first side of the die pad 20, i.e., the corresponding end of the second pin 50 is physically separated from the first side of the die pad 20. The second lead 50 is an independent lead disposed parallel to the first lead 42, and is separated from the first connection rib 41 and the first lead 42, i.e., the independent lead is not connected to any other structure except the frame 11, and is cut after the semiconductor device is finally formed to draw out the signal of the semiconductor chip 30 after the semiconductor chip 30 is assembled.

The third pin 60 is disposed on the second side of the die pad 20 and is connected to the frame 11. Specifically, one end of the third pin 60 is connected to the second inner sidewall 11c, and the other end of the third pin 60 is connected to the second side of the die pad 20. The third lead 60 includes a plurality of second leads 61 disposed between the second side of the die pad 20 and the second inner sidewall 11c of the process hole 11a, the plurality of second leads 61 are disposed parallel to each other, and one end of the second lead 61 is connected to the second side of the die pad 20 and the other end is connected to the second inner sidewall 11c to lead out signals of the semiconductor chip 30 after the semiconductor chip 30 is assembled.

Fig. 2 is a schematic structural diagram of another embodiment of a lead frame according to the present utility model. The lead frame shown in fig. 2 is substantially the same as the lead frame shown in fig. 1, except that the third leads 60 are provided independently of the structure outside the die pad 20. In this embodiment, one end of the third pin 60 is connected to the second inner sidewall 11c, and the other end of the third pin 60 is spaced apart from the second side of the die pad 20, i.e., the corresponding end of the third pin 60 is physically separated from the second side of the die pad 20. The third pin 60 includes a second connecting rib 62 parallel to the second inner sidewall 11c, and a plurality of third leads 63 connected between the second connecting rib 62 and the second inner sidewall 11c, wherein the plurality of third leads 63 are connected together by the second connecting rib 62, one end of the third leads 63 is connected with the second connecting rib 62, and the other end of the third leads 63 is connected with the second inner sidewall 11 c. The second connection ribs 62 are disposed opposite to and spaced apart from the second side of the die pad 20 and physically separated from the die pad 20, a plurality of third leads 63 are disposed between the second connection ribs 62 and the second inner sidewall 11c at uniform intervals, and the plurality of third leads 63 are disposed parallel to each other to draw out signals of the semiconductor chip 30 after the semiconductor chip 30 is assembled.

Referring to fig. 3 and 4, a schematic structural view of a packaged semiconductor device formed based on the lead frame shown in fig. 2 is shown. The semiconductor device of the present embodiment includes a die pad 20, a semiconductor chip 30, a first lead 40, a second lead 50, a third lead 60, an electrical connection structure 70, and a plastic package 80. Taking the illustrated direction as an example, the lower surface of the semiconductor chip 30 is adhered to the die pad 20 by the conductive paste 90. In this embodiment, the semiconductor device is configured as a power device, such as a power transistor, a MOSFET, etc., and the semiconductor chip 30 has a first terminal, a second terminal and a third terminal, where the first terminal is a source, the second terminal is a gate and the third terminal is a drain, and the drain of the semiconductor chip 30 may be disposed on the upper surface or the lower surface of the semiconductor chip 30 (the upper surface in this embodiment, when the drain of the semiconductor chip 30 is disposed on the lower surface, the drain may be led out correspondingly with the third pin 60 on the lead frame shown in fig. 1) to provide a corresponding drain connection.

Specifically, the die pad 20 is provided with a carrier region 20a and a first plating region 20b, the first plating region 20b is coated with a plating layer, and the semiconductor chip 30 is configured to be adhered in the carrier region 20a by the conductive paste 90 and to be electrically conductive to the die pad 20 by the plating layer coated on the first plating region 20 b. The first lead 40, the second lead 50 and the third lead 60 can be electrically connected to corresponding terminals of the semiconductor chip 30 independently and correspondingly through the electrical connection structure 70, and preferably, according to the structures of the first lead 40, the second lead 50 and the third lead 60, the first lead 40 and the third lead 60 are usually connected to large current carrying terminals (such as a source electrode and a drain electrode), the second lead 50 is usually connected to small current carrying terminals (such as a grid electrode), and therefore, the first lead 40, the second lead 50 and the third lead 60 of the embodiment are respectively connected to a source electrode, a grid electrode and a drain electrode of the semiconductor chip 30 through the electrical connection structure 70 so as to provide electrical connection between each terminal of the semiconductor chip 30 and each lead of the lead frame, and further, source signals, grid signals and drain signals on the semiconductor chip 30 are led out. In this embodiment, the electrical connection structure 70 may be any existing structural implementation such as gold wires, conductive clips, and the like.

Preferably, the semiconductor chip 30 includes a first portion welded and fixed on the carrier region 20a and a second portion integrally formed on the first portion, the first portion of the semiconductor chip 30 is projected on a horizontal plane more than the second portion so that the periphery of the first portion extends beyond the outer side wall of the second portion, and a step 31 is formed at a transition position between the first portion and the second portion, and the step 31 has the functions of consuming and blocking solder. Specifically, when the first plating region 20b is disposed at the edge of the carrier region 20a, during the mounting of the semiconductor chip 30, the silver paste or solder applied to the first plating region 20b is pressed to overflow outward to generate local solder climbing, and at this time, the extruded silver paste or solder may be consumed and blocked due to the step 31, thereby achieving the purpose of preventing solder climbing.

In the present embodiment, after the semiconductor chip 30 is electrically connected to the lead frame, the semiconductor chip 30 and a portion of the lead frame are encapsulated by the plastic package 80. The plastic package 80 is injection molded from an electrically insulating material, which may be a material such as an insulating resin, ceramic, thermoset plastic, etc., and the plastic package 80 completely covers the semiconductor die and its associated die pad 20, electrical connection structure 70, and portions of the pins, etc. In this embodiment, after the molding of the molding body 80, a portion of the leads not covered by the molding body 80 are exposed outside the molding body 80 to form solder feet of the semiconductor device, and the surface of the solder feet is plated with an electroplating coating to provide electrical connection between the semiconductor device and an external circuit.

In the preparation of the semiconductor chip 30 of the present embodiment, first, a preformed lead frame, the semiconductor chip 30, and the electrical connection structure 70 are prepared. Then, silver paste or solder paste is sprayed on the first plating layer area 20b, the semiconductor chip 30 is placed on the slide area 20a by means of the machine table to adsorb the semiconductor chip 30, then the semiconductor chip 30 is placed on the slide area 20a by means of downward movement, the whole lead frame attached with the semiconductor chip 30 is sent into an oven to be baked at high temperature and welded and solidified to fix the semiconductor chip 30, and the source electrode, the grid electrode and the drain electrode of the semiconductor chip 30 are respectively bonded with the first pin 40, the second pin 50 and the third pin 60 by means of the electric connection structure 70. Next, the individual semiconductor chips 30 are molded with an insulating resin, and after curing, the flash remaining in the molding process is removed by high-pressure water to form the molded body 80. Then, impurities and oxides on the surface of the lead frame exposed outside the plastic package 80 are removed, and after the exposed surface is slightly corroded, a tin layer is electroplated on the exposed surface of the lead frame by an electrochemical method to form an electroplating coating. Finally, the surfaces of the lead frame and the plastic package body 80 are cleaned, and then baked, and after baking, the cut ribs are separated to form a single semiconductor device, so that the structure is simple, the reliability is high, and the delamination among the interfaces of the lead frame, the semiconductor chip 30 and the plastic package body 80 can be effectively prevented.

Claims (10)

1. The lead frame for improving plating layering comprises at least one frame unit, and is characterized in that the frame unit comprises a frame, a die pad, a first pin, a second pin and a third pin, wherein the frame is provided with a process hole in a penetrating mode, the die pad is formed in the process hole and connected to the frame, the first pin and the second pin are arranged on a first side of the die pad and connected to the frame, and the third pin is arranged on a second side opposite to the first side of the die pad and connected to the frame; the first surface of the die pad is formed with a carrier region and a first plating region which is positioned in the carrier region and has an area smaller than that of the carrier region.

2. The lead frame for improving plating delamination according to claim 1, wherein the inner wall of the process hole has a first inner sidewall and a second inner sidewall disposed opposite to each other, one end of the first and second leads is connected to the first inner sidewall, the other opposite ends of the first and second leads are spaced apart from the first side of the die pad, one end of the third lead is connected to the second inner sidewall, and the other opposite end of the third lead is connected to the second side of the die pad or spaced apart from the die pad.

3. The lead frame for improving plating delamination according to claim 2, wherein the first lead includes a first connecting rib disposed parallel to the first inner sidewall and a plurality of first leads connected between the first connecting rib and the first inner sidewall, the plurality of first leads being disposed parallel to the second lead and physically separated from the second lead, one end of the first lead being connected to the first connecting rib and the other end being connected to the first inner sidewall.

4. The lead frame for improving plating delamination according to claim 2, wherein the third pin comprises a plurality of second leads disposed between the second side of the die pad and a second inner side wall, the plurality of second leads being disposed parallel to each other, and one end of the second leads being connected to the second side of the die pad and the other end being connected to the second inner side wall;

or (b)

The third pin comprises a second connecting rib parallel to the second inner side wall and a plurality of third leads connected between the second connecting rib and the second inner side wall, the third leads are mutually parallel, one end of each third lead is connected with the second connecting rib, and the other end of each third lead is connected with the second inner side wall.

5. The lead frame for improving plating delamination according to claim 2, wherein the inner wall of the process hole further has a third inner side wall and a fourth inner side wall disposed between the first inner side wall and the second inner side wall and disposed in opposition, the die pad further has a third side disposed in opposition to the third inner side wall and a fourth side disposed in opposition to the fourth inner side wall, and the third side and/or the fourth side of the die pad are integrally extended outwardly with reinforcing ribs connected to the third inner side wall and/or the fourth inner side wall of the corresponding side.

6. The lead frame for improving plating delamination according to any one of claims 1-5, wherein the first surface of the die pad is further formed with at least one second plating region located inside the carrier region and independent of the first plating region, and a total area of the first and second plating regions is smaller than an area of the carrier region.

7. The semiconductor device is characterized by comprising a die pad, a semiconductor chip, a first pin, a second pin, a third pin, an electric connection structure and a plastic package body, wherein the semiconductor chip is installed on the die pad, the first pin and the second pin are arranged on the first side of the die pad, the third pin is arranged on the second side of the die pad, the electric connection structure is used for connecting the semiconductor chip with the first pin, the second pin and the third pin, the plastic package body is used for packaging the die pad, the semiconductor chip, the first pin, the second pin, the third pin and the electric connection structure, a carrier region and a first coating region which is arranged in the carrier region and has an area smaller than that of the carrier region are formed on the first surface of the die pad, the first coating region is coated with a coating, and the semiconductor chip is arranged in the carrier region and is in electric contact with the coating.

8. The semiconductor device of claim 7, wherein the semiconductor chip includes a first portion mounted on the carrier region and a second portion integrally formed on the first portion, the first portion having a step formed around and outwardly beyond an outer sidewall of the second portion.

9. The semiconductor device of claim 7, wherein the first, second and third leads each have a solder leg extending away from the die pad and exposed outside the plastic package, a surface of the solder leg being plated with a plating coating.

10. A semiconductor device according to any one of claims 7 to 9, wherein the die pad is made of a copper frame, and the plating is a silver plating or a tin plating.