CN219779988U - Novel Buck power factor correction converter - Google Patents
Novel Buck power factor correction converter Download PDFInfo
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- CN219779988U CN219779988U CN202321277361.1U CN202321277361U CN219779988U CN 219779988 U CN219779988 U CN 219779988U CN 202321277361 U CN202321277361 U CN 202321277361U CN 219779988 U CN219779988 U CN 219779988U
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- 238000006243 chemical reaction Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
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- 238000012887 quadratic function Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
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- 230000003321 amplification Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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Abstract
The utility model discloses a novel Buck power factor correction converter, which comprises a main power circuit and a control circuit; the main power circuit comprises an alternating current source, an EMI filter, two sets of parallel Buck and auxiliary Flyback circuits which respectively work on positive and negative half cycles of a power frequency power supply, and an output filter capacitor C connected in series 1 And C 2 Load R o The method comprises the steps of carrying out a first treatment on the surface of the The control circuit comprises a voltage sampling circuitThe voltage comparator CMP1, the zero crossing detection circuit, the RS trigger and the switch gating circuit. The utility model effectively solves the problem of dead zone of input current of the traditional Buck PFC converter by connecting the auxiliary Flyback circuit in parallel, and adopts a segmented constant-conduction time control method to ensure that the converter works in a Buck stage and a Flyback stage in one power frequency period and has different conduction times, thereby reducing the peak value of inductance current, reducing the conduction loss of a switching tube and further improving the power factor in a wide input voltage range.
Description
Technical Field
The utility model relates to the technical field of power electronics, in particular to a novel Buck power factor correction converter.
Background
With the development of society and technology, efficient utilization of electric energy is becoming more and more important, and utilization of electric energy is not separated from power electronics technology. The power electronic equipment such as a switch power supply and the like is used as an electric energy conversion device, has the advantages of high power density, high efficiency, small volume, low cost and the like, and is widely applied to the scenes such as an adapter, LED illumination, a medical equipment power supply and the like. However, the large-scale application of the power electronic equipment can cause serious problems of damaging the safe and stable operation of the power grid, such as current distortion, harmonic pollution, power factor reduction and the like at the input side of the power grid. Therefore, how to increase the power factor and improve the power quality is a focus of attention.
In order to improve the power factor, meet the related harmonic standard and reduce the influence on the power quality of a power grid, the input current and the input voltage can be identical in phase or sinusoidal along with the input voltage, an AC-DC power conversion technology with the function is called a power factor correction (Power Factor Correction, PFC) technology, and a rectification topological circuit adopting the PFC technology is called a power factor correction converter. PFC converters can be classified according to different classification methods: the power conversion device can be divided into a single stage and two stages according to the stage number of the power conversion, and compared with the two stages, the single stage has the advantages of high power factor, high efficiency, small volume and the like; according to whether an active device is adopted or not, the active PFC can be divided into passive PFC and active PFC, compared with a filter inductor and a capacitor which are huge in size in a passive PFC circuit, the active PFC effectively reduces the size of the converter by introducing closed loop feedback to control high-frequency on-off of a switching tube, and meanwhile, can well correct the input current waveform and has a higher power factor; inductor current continuity can be classified into inductor current continuity mode (Continuous Conduction Mode, CCM), inductor current critical continuity mode (Critical conduction Mode, CRM) and inductor current discontinuous mode (Discontinuous Conduction Mode, DCM) according to whether the inductor current is continuous or not. The PFC converter working in the CRM has the advantages of zero current on of a switching tube, no reverse recovery current of a diode, small switching loss of the converter and the like, and the converter is simpler to control in the mode.
At present, the PFC converters commonly used in the market include Boost (Boost) converters, buck (Buck) converters, flyback (Flyback) converters and Buck-Boost (Buck-Boost) converters, wherein the most classical PFC converters belong to Boost PFC converters, which can effectively improve power factors and reduce current harmonics, but have the defects of high loss during low-voltage input, high device stress of the later-stage converters, and the like, and are the bottleneck for restricting the development of the PFC converters. The Buck PFC converter can well solve the problem, and in the low-voltage input occasion, the input and output voltages are relatively close due to the characteristic of self-step-down of the Buck circuit, so that relatively high efficiency can be realized; in addition, the advantages of low Buck PFC output voltage, small common mode EMI noise, no need of a surge limiter, small main inductance and the like make the Buck PFC output voltage gradually become a research hot spot of a power factor correction technology.
However, the conventional Buck PFC converter has inherent zero-crossing distortion and dead zone, i.e. the circuit cannot work normally when the input voltage is lower than the output voltage, and the input current is zero, and this dead zone time greatly increases the input current harmonic wave, and limits the improvement of the PF value. Therefore, the novel Buck power factor correction converter is provided, the Buck and the auxiliary Flyback circuit are connected in parallel at the input end, and when the input voltage is lower than the switching voltage, the auxiliary Flyback circuit works; when the input voltage is higher than the switching voltage, the Buck circuit works; therefore, the dead zone problem of the traditional Buck PFC converter is solved. For the control mode, the traditional Constant on-time (COT) control is that the conduction time in each switching period is the same, but the control is simple, but the defects of large peak value of inductance current, large conduction loss of a switching tube and low PF value at low voltage exist.
Disclosure of Invention
Therefore, the utility model aims to provide a novel Buck power factor correction converter which can work in a Buck or Flyback mode by comparing the magnitude of an input voltage and a switching voltage, so as to solve the problem of zero-crossing distortion of the traditional Buck PFC converter near the position where the input voltage is smaller; and the control of the sectional constant conduction time (Segmented Constant on-time, SCOT) is adopted, so that the power factor is further improved, the inductance current peak value is reduced, and the conduction loss of a switching tube is reduced on the basis of COT. The specific scheme is as follows:
the utility model relates to a novel Buck power factor correction converter, which comprises a main power circuit and a control circuit; the main power circuit comprises an alternating current source, an EMI filter, two sets of parallel Buck and auxiliary Flyback circuits which respectively work on positive and negative half cycles of a power frequency power supply, and an output filter capacitor C connected in series 1 And C 2 Load R o The method comprises the steps of carrying out a first treatment on the surface of the The control circuit comprises a voltage sampling circuit, an error amplifying circuit, a sawtooth wave generating circuit, a voltage comparator CMP1, a zero crossing detection circuit, an RS trigger and a switch gating circuit;
the main power circuit comprises an alternating current source (1), an EMI filter (2), a positive half-cycle Buck-Flyback PFC circuit (3), a negative half-cycle Buck-Flyback PFC circuit (4) and an output filter capacitor C 1 (5) Output filter capacitor C 2 (6) And a DC load (7); the alternating current source (1) is connected with the input port of the EMI filter (2), and the upper end of the output port of the EMI filter (2) is connected with the diode D 1 (301) And diode D 5 (304) Anode, diode D of (c) 2 (401) And diode D 6 (404) The lower end of the output port of the EMI filter (2) is connected with the diode D 3 (306) Anode, diode D of (c) 4 (406) Cathode of (a) switching tube S 3 (305) Source electrode of (S) switch tube 4 (405) Drain electrode of (C), output filter capacitor (C) 1 (5) Negative electrode of (2) and output filter capacitor C 2 (6) The positive pole of the positive half cycle Buck-Flyback PFC circuit (3) is connected with the negative half cycle Buck-Flyback PFC circuit (4) as a neutral line; in the positive half cycle Buck-Flyback PFC circuit (3), a diode D 1 (301) Cathode and switching tube S of (2) 1 (302) Is connected with the drain electrode of the switch tube S 1 (302) Source electrode of (C) is connected with diode D 3 (306) Cathode of (d) and transformer T 1 (303) The homonymous ends of the secondary windings are connected, and the transformer T 1 (303) Output filter capacitor C with different-name end connection of secondary winding 1 (5) And the upper end of the direct current load (7), diode D 5 (304) Cathode of (d) and transformer T 1 (303) The same-name ends of the primary windings are connected, and the transformer T 1 (303) Different-name terminating switch tube S of primary winding 3 (305) Drain electrode of transformer T 1 (303) The same name end of the third winding is connected with the primary side ground, and the transformer T 1 (303) The different name end of the third winding outputs zero crossing detection signal v ZCD1 Giving the control circuit; in the negative half cycle Buck-Flyback PFC circuit (4), a filter capacitor C is output 2 (6) The negative pole of the (C) is connected with the lower end of the DC load (7) and the transformer T 2 (403) The synonym end of the secondary winding is grounded and connected to the ground, the transformer T 2 (403) The same-name end of the secondary winding is connected with a diode D 4 (406) Anode and switching tube S of (2) 2 (402) Is connected with the drain electrode of the switch tube S 2 (402) Source electrode of (D) and diode D 2 (401) Anode of (C) is connected with switch tube S 4 (405) Source electrode of (1) is connected with transformer T 2 (403) Different name end of primary winding and transformer T 2 (403) Homonymous terminal of primary winding and diode D 6 (404) Is connected with the anode of the transformer T 2 (403) The same name end of the third winding is connected with the primary side ground, and the transformer T 2 (403) The different name end of the third winding outputs zero crossing detection signal v ZCD2 Giving the control circuit;
the control circuit comprises a voltage sampling circuit (8), an error amplifying circuit (9), a sawtooth wave generating circuit (10), a first voltage comparator (11), a zero crossing detection circuit (12), an RS trigger (13) and a switch gating circuit (14); the voltage sampling circuit (8) is connected with the direct current load (7) of the main power circuit in parallel and is used for collecting the output voltage of the main power circuit; the input end of the error amplifying circuit (9) is connected with the output end of the voltage sampling circuit (8), the output end of the error amplifying circuit (9) is connected with the negative end of the first voltage comparator (11), and the error amplifying circuit (9) is used for outputting an error signal of the output voltage of the main power circuit; the sawtooth wave generating circuit (10) performs capacitance feeding through a direct current sourceThe repeated charge and discharge operation of the row generates a sawtooth wave signal, and the output end of the sawtooth wave signal is connected with the positive end of the first voltage comparator (11); the output end of the first voltage comparator (11) is connected with the R end of the RS trigger (13), the S end of the RS trigger (13) is connected with the output of the zero-crossing detection circuit (12), and the output signal Q of the RS trigger (13) is connected with the input of the switch gating circuit (14); the zero-crossing detection circuit (12) has an input of a zero-crossing detection signal v passing through an adder ZCD1 And v ZCD2 The method comprises the steps of carrying out a first treatment on the surface of the The switch gating circuit (14) judges which switch tube is driven to be conducted by comparing the instantaneous voltage of the alternating current source (1) with zero and switching voltage, and the output of the switch tube is a switch tube S 1 (302) Switch tube S 2 (402) Switch tube S 3 (305) And a switch tube S 4 (405) Is connected to the gate of each switching tube.
Optionally, the main power circuit adopts a connection mode of parallel input and series output, namely, the Buck circuit and the auxiliary Flyback circuit are integrated in parallel at the input end, and whether the Buck circuit and the auxiliary Flyback circuit work or not depends on the relation between the instantaneous voltage of the alternating current source (1) and the switching voltage, and the filter capacitor C is output 1 (5) And output filter capacitor C 2 (6) At the output, the output terminals are connected in series, each carrying half of the output voltage.
Optionally, the main power circuit is provided with two independent Buck-Flyback PFC circuits, namely a positive half-cycle Buck-Flyback PFC circuit (3) and a negative half-cycle Buck-Flyback PFC circuit (4), and takes a neutral line as a boundary line, when the instantaneous voltage of the alternating current source (1) is greater than zero, the positive half-cycle Buck-Flyback PFC circuit (3) above the neutral line works, and when the instantaneous voltage of the alternating current source (1) is less than zero, the negative half-cycle Buck-Flyback PFC circuit (4) below the neutral line works.
Optionally, the transformer T 1 (303) And a transformer T 2 (403) Comprising the following steps: the primary winding is used as a primary inductor of an auxiliary Flyback loop, the secondary winding is used as a secondary inductor of a Buck loop, and the third winding is used for collecting zero-crossing detection signals; the turns ratio of the primary side and the secondary side is n 1, and the left ends of the three windings are the same-name ends.
Optionally, the voltage sampling circuit (8) includes a first voltage dividing resistor (801) and a second voltage dividing resistor (802) connected in series, the first voltage dividing resistor (801) and the second voltage dividing resistor (802) are connected in parallel, two ends of a direct current load (7) of the novel Buck power factor correction converter serve as input ends of the voltage sampling circuit (8), and a common end of the first voltage dividing resistor (801) and the second voltage dividing resistor (802) serves as output ends of the voltage sampling circuit (8).
Optionally, the error amplification circuit (9) comprises a loop compensation circuit (901), an error amplifier (902) and a first reference power supply (903); the loop compensation circuit (901) is connected in parallel with the negative end and the output end of the error amplifier (902), the positive end of the error amplifier (902) is connected with the positive end of the first reference power supply (903), the negative electrode of the first reference power supply (903) is used as the reference voltage end of the error amplifier circuit (9), the output end of the error amplifier (902) is used as the output end of the error amplifier circuit (9), and the negative end of the error amplifier (902) is used as the input end of the error amplifier circuit (9).
Optionally, the sawtooth wave generating circuit (10) comprises a charging current source (1001), a switching tube S 5 (1002) First timing capacitor C 3 (1003) Second timing capacitor C 4 (1004) And a switch tube S 6 (1005) The method comprises the steps of carrying out a first treatment on the surface of the The negative electrode of the charging current source (1001) is grounded, the positive electrode is used as a first input end and is connected with the switch tube S 5 (1002) One end of (C) a second timing capacitor (C) 4 (1004) Positive electrode of (c) and switching tube S 6 (1005) One end of the switch tube S is connected with the positive end of the first voltage comparator (11) 5 (1002) And the other end of the first timing capacitor C 3 (1003) The positive electrode of the first timing capacitor C 3 (1003) Negative electrode of (C) second timing capacitor 4 (1004) Is connected with the negative electrode of the switch tube S 6 (1005) The other ends of the two are all grounded; a fifth output v of the switch gating circuit (14) gb Is connected to a second input of the sawtooth wave generating circuit (10) for controlling the switching tube S 5 (1002) The Q end of the RS trigger (13) is connected with the third input end of the sawtooth wave generating circuit (10) to control the switching tube S 6 (1005) Is turned on and off; the sawtooth wave generating circuit(10) And outputting sawtooth wave signals with different on-time according to the operation of the main power circuit in the Buck or Flyback stage.
Optionally, the switch gating circuit (14) comprises v in A detection circuit (141), a phase detection circuit (142), a first subtractor (143), a second subtractor (144), a logic circuit (145); further, the phase detection circuit (142) includes a second voltage comparator (1421), a third voltage comparator (1422), a fourth voltage comparator (1423), a fifth voltage comparator (1424), a second reference power supply (1425), and a third reference power supply (1426), and the logic and driving circuit (145) includes a first and gate (1451), a second and gate (1452), a third and gate (1453), a fourth and gate (1454), a nor gate (1455), a first driving circuit (1456), a second driving circuit (1457), a third driving circuit (1458), a fourth driving circuit (1459), and a fifth driving circuit (14510); wherein the v in The detection circuit (141) is mainly used for detecting the instantaneous voltage of the AC source (1), v in The output end of the detection circuit (141) is connected with the positive input ends of a second voltage comparator (1421) and a fourth voltage comparator (1423) in the phase detection circuit (142), the negative input ends of a third voltage comparator (1422) and a fifth voltage comparator (1424), the negative input ends of the second voltage comparator (1421) are connected with the positive input end of the third voltage comparator (1422) and are grounded, the positive input ends of the fourth voltage comparator (1423) and the fifth voltage comparator (1424) are respectively connected with the positive electrodes of a second reference power supply (1425) and a third reference power supply (1426), the negative electrodes of the second reference power supply (1425) and the third reference power supply (1426) are respectively connected with the ground, the output ends of the second voltage comparator (1421) and the third voltage comparator (1422) are respectively connected with the positive input ends of the first subtractor (143) and the second subtractor (144), the output ends of the fourth voltage comparator (1423) are respectively connected with the negative ends of the first subtractor (1423) and the first subtractor (145) and the second subtractor (145) and the output ends of the third subtractor (145) and the first and the second comparator (1454) are respectively connected with the output ends of the first and the third subtractor (1454) and the first and the second comparator (145); the output of the first subtracter (143) is connected to one input of a second AND gate (1452) and a NOR gate (1455), and the output of the second subtracter (144) is connected to a fourth AND gate (14)54 One input of the nor gate (1455) is connected to the other input of the nor gate; the other input ends of the first AND gate (1451), the second AND gate (1452), the third AND gate (1453) and the fourth AND gate (1454) are respectively connected with the Q end of the RS trigger (13), the output ends of the first AND gate (1451), the second AND gate (1452), the third AND gate (1453), the fourth AND gate (1454) and the NOR gate (1455) are respectively connected with the input ends of the first driving circuit (1456), the second driving circuit (1457), the third driving circuit (1458), the fourth driving circuit (1459) and the fifth driving circuit (14510), and the first driving circuit (1456), the second driving circuit (1457), the third driving circuit (1458) and the fourth driving circuit (1459) respectively output driving signals v g1 、v g2 、v g3 And v g4 And are respectively connected to a switching tube S in the main power circuit 1 (302) Switch tube S 2 (402) Switch tube S 3 (305) And a switch tube S 4 (405) The output end of the fifth driving circuit (14510) outputs a driving signal v gb A second input terminal connected to the sawtooth wave generating circuit (10); the output ends of the first driving circuit (1456), the second driving circuit (1457), the third driving circuit (1458), the fourth driving circuit (1459) and the fifth driving circuit (14510) are respectively used as a first output end, a second output end, a third output end, a fourth output end and a fifth output end of the switch gating circuit (14), and the v in An input end of the detection circuit (141) and a Q end of the RS trigger (13) serve as input ends of the switch gating circuit (14).
Optionally, the second reference power supply (1425) and the third reference power supply (1426) are respectively switching voltages V between positive half cycle Buck and Flyback modes b And a switching voltage-V between negative half-cycle Buck and Flyback modes b To make the switching between the two operating states smoother, the size is set to be slightly higher than V o A value of/2.
Optionally, after the Q end of the RS trigger (13) outputs the total driving signal and passes through the switch gating circuit (14), different positive half cycles or negative half cycles, buck or Flyback switching tubes S are generated 1 (302) Switch tube S 2 (402) Switch tube S 3 (305) Switch tube S 4 (405) And a switch tube S 5 (1002) Is provided.
In summary, by adopting the above technical scheme, the power factor correction converter provided by the utility model can at least achieve the following beneficial effects: (1) The problem of dead zone of input current of the traditional Buck PFC converter is solved, the harmonic content of the input current is effectively reduced, and the power factor is improved; (2) The SCOT control is adopted, so that the inductance current peak value and the effective value of the switching tube current are reduced, the conduction loss of the converter is reduced, the efficiency of the converter is improved, and the power factor is further improved; (3) Compared with the traditional non-isolated Buck PFC circuit, only two switching tubes, two diodes and two inductance windings are added, the switch control strategy is relatively simple to realize, the overall cost of the circuit is increased little, and the bridge-free, output capacitance series voltage division, independent operation of positive and negative half cycles and the improvement of the performance can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only embodiments of the present utility model, and other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a conventional Buck PFC converter;
fig. 2 is a schematic diagram of key waveforms of a conventional Buck PFC converter;
fig. 3 shows an input voltage v of a conventional Buck PFC converter in Input current i in Inductor current i L And output voltage V o Is a simulation waveform diagram of (1);
fig. 4 is a schematic diagram of a main circuit structure of a novel Buck power factor correction converter according to an embodiment of the present utility model;
fig. 5a is an equivalent circuit diagram of a novel Buck power factor correction converter disclosed in the embodiment of the utility model in a Flyback mode when the novel Buck power factor correction converter works in a positive half cycle of a power frequency power supply, wherein the equivalent circuit diagram comprises two modes, namely a mode 1 and a mode 2;
fig. 5b is an equivalent circuit diagram of the novel Buck power factor correction converter disclosed in the embodiment of the utility model in a Buck mode when the novel Buck power factor correction converter works in a positive half cycle of a power frequency power supply, wherein the equivalent circuit diagram comprises two modes, namely a mode 3 and a mode 4;
FIG. 6 is a schematic diagram of a main power circuit and a control circuit of a novel Buck PFC converter according to an embodiment of the present utility model;
FIG. 7 is a schematic diagram of a conventional sawtooth wave generating circuit under constant on-time control;
FIG. 8 is a schematic diagram of the main waveforms of a novel Buck PFC converter according to an embodiment of the present utility model;
fig. 9 shows an input voltage v of a novel Buck pfc converter according to an embodiment of the present utility model in Input current i in Primary inductor current i Lp1 、i Lp2 Secondary inductor current i Ls1 、i Ls2 And output voltage V o Is a simulation waveform diagram of (1);
fig. 10 is an enlarged simulation waveform diagram of a novel Buck power factor correction converter at a Buck and Flyback mode switching position according to an embodiment of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
1. Dead zone problem of traditional Buck PFC converter
As mentioned above, although the Buck PFC converter has its own unique advantages, there is a fatal problem as shown in fig. 2 and 3: when the input voltage v is in Less than the output voltage V o At the time, a current i is input in At zero, there is a large zero crossing distortion and dead zoneProblems; only when the voltage v is input in Greater than the output voltage V o The converter can work normally, so that a higher power factor cannot be obtained. Due to the dead zone, the conventional Buck PFC converter requires a trade-off between efficiency and total harmonic distortion (Total Harmonic Distortion, THD) of the input current if the output voltage V o Increased, but THD conditions worsen despite the increased efficiency; on the contrary, when the output voltage V o The efficiency is greatly reduced when reduced, and therefore a relatively fixed output voltage is required to achieve the desired THD and high efficiency. And due to the existence of inherent dead time, the traditional Buck PFC converter has limited PF and high current distortion, is difficult to meet the current harmonic requirement, and limits the application scene of the traditional Buck PFC converter, especially for a lighting system.
Based on this, the utility model provides a novel Buck power factor correction converter, so as to solve the dead zone problem of the traditional Buck PFC converter, and the structure schematic diagram of the main circuit is shown in fig. 4.
2. Novel working principle of Buck power factor correction converter
Setting: 1. all devices are ideal elements; 2. the output filter capacitor is large enough, and the output voltage ripple is small compared with the direct current thereof; 3. the switching frequency of the switching tube is much greater than the input ac voltage frequency.
Fig. 5a, fig. 5b and fig. 8 show the equivalent circuit and the main waveform diagrams of the novel Buck power factor correction converter in different modes when the novel Buck power factor correction converter works in the positive half cycle of the power frequency power supply. When the input voltage v in Less than the switching voltage V b When the circuit is operated in the Flyback mode, the switch tube S 3 Work, S 1 And remain off. When the switch tube S 3 When conducting, the input voltage is applied to the transformer T 1 Primary inductance L of (2) p1 Charging with current i Lp1 Starting with zero and v in /L p1 The slope of (2) rises linearly, and the output filter capacitor C is connected in series 1 And C 2 Supplying power to the load; when the switch tube S 3 When turned off, energy is transferred to the transformer T 1 Secondary inductance L of (2) s1 And pass through D 3 Freewheel at this time L s1 The voltage across it is-V o /2，i Ls1 In V form o /2L s1 Is decreased in slope and i Ls1 A new cycle is started when it falls to zero. When the input voltage v in Greater than switching voltage V b When the circuit operates in Buck mode, the switch tube S 1 Work, S 3 And remain off. When the switch tube S 1 When conducting, the transformer T 1 Secondary inductance L of (2) s1 The voltage across it is v in -V o /2, its current i Ls1 Starting from zero with (v) in -V o /2)/L s1 Slope of (v) increases linearly in To output filter capacitor C 1 、C 2 And a load power supply; when the switch tube S 1 When turned off, i Ls1 Through D 3 Freewheel at this time L s1 The voltage across it is-V o /2，i Ls1 In V form o /2L s1 Is decreased in slope and i Ls1 A new cycle is started when it falls to zero.
Without loss of generality, the input ac voltage v is defined in The expression of (2) is:
v in ＝V m sinωt (1)
wherein V is m And ω are the amplitude and angular frequency of the input ac voltage, respectively.
In one switching cycle, the converter is divided into two working states of Flyback topology work and Buck topology work.
When the input voltage v in Less than the switching voltage V b During the Flyback topology operation, the peak value i of the primary inductance current Lp1_pk The method comprises the following steps:
wherein t is on_f Is the on time.
Then the energy is transferred to the secondary side for release, and the peak value i of the secondary inductance current Ls1_pk2 The method comprises the following steps:
wherein V is o To output voltage t off_f Is the off time.
Due to the transformer T 1 The current peak ratio of the primary and secondary side inductance windings is the reciprocal of the turns ratio n, and is obtained by the formulas (2) and (3):
according to the formulas (3) and (4), it is possible to obtain a flow through the switching tube S in one switching cycle 3 The average value of (2) is:
when the input voltage v in Greater than switching voltage V b When in Buck topology work, the secondary inductance current peak value i Ls1_pk1 The method comprises the following steps:
wherein t is on_b Is the on time.
Within each switching period, L s1 The volt-second area balance at both ends, i.e
Wherein V is o To output voltage t off_b Is the off time.
From the formulae (1) and (7):
according to the formulas (6) and (8), the flow through the switching tube S in one switching period can be obtained 1 The average value of (2) is:
because the parallel auxiliary Flyback topology compensates the input current dead zone of the traditional Buck converter, the input current is not zero in the whole power frequency period.
Thus, the current i is input in The method comprises the following steps:
wherein the method comprises the steps of
On-time t in both phases of operation on_f And t on_b Meanwhile, the control strategy is a traditional constant-on-time control strategy, and at the moment, although the auxiliary Flyback converter compensates the dead zone part of the input current of the Buck converter, the waveform of the input current has larger distortion than a sine, the harmonic content is more, the defects of large peak value of the inductance current, large conduction loss of a switching tube and the like exist, and particularly when the turn ratio n is smaller, the situation is more serious.
Therefore, the present utility model provides a method for controlling the conduction time in a segmented manner, that is, the conduction time in two working phases is different, and the method is applied to the present embodiment, so as to effectively overcome the above-mentioned shortcomings of the conventional control of the conduction time.
3. Novel control for improving PF value
3.1 on-time expression maximizing PF
From the formulas (1) and (10), it can be found that when the duty ratios are different, the average value P of the input power of the converter in half the power frequency period in The method comprises the following steps:
wherein T is line Is the input voltage period.
Setting conversionThe efficiency of the device is 100%, the input power is equal to the output power, i.e. P in ＝P o The on-time t is obtained by equation (11) on_f And t on_b The relation between the two is:
from the formulas (10) and (12), the PF value with respect to t can be obtained on_b The expression of (2) is:
wherein I is in_rms Is an input current effective value;
as can be seen from the expression of the PF of the formula (13), the root of the denominator part is related to t on_b The quadratic function of (2) has a quadratic function coefficient greater than 0, a first order coefficient less than 0, and a constant term greater than 0, so that the quadratic function has a minimum value, namely the position of the symmetry axis; so at a constant V m Under this, an optimal t can be solved on_b_opt So that the PF value takes a maximum value at the input voltage. The optimum t on_b_opt The values are:
the combination of formula (12) and formula (14) can obtain the optimal t on_f_opt The values are:
by substituting equation (14) into equation (13), the power factor PF at the optimal on time can be calculated opt The method comprises the following steps:
that is, when the on-time of the Buck and Flyback stages takes the values of the equation (14) and the equation (15), respectively, the PF value of the converter is optimal at this time, but the on-time needs to be continuously adjusted along with the change of the input voltage, which will definitely increase the complexity of the control circuit. The method introduces a segmented definite conduction concept, namely that the conduction time of each working stage is fixed and different from each other to form a ratio so as to simplify a control circuit on the basis of maximally improving the power factor.
The ratio k of the on-time of the Buck and Flyback phases is defined as:
by fitting a curve of the optimal on-time ratio k versus the input voltage, it can be found that k decreases with increasing input voltage. For this reason, an attempt is made to fix k over a wide input voltage range (90-265 Vac), find its optimal solution to find a relatively good PF value, simplifying the control circuit.
Without loss of generality, a fixed on-time ratio K for the two phases of operation is defined as:
substituting the above formula (18) into formula (12) yields:
by substituting equations (19) and (20) into equation (13), the power factor PF can be derived for the ratio of the on-time of the Flyback phase to the Buck phase of K K The method comprises the following steps:
power factor PF at different K values can be obtained by least square method K Power factor PF at optimum constant on-time opt The error expression between them is:
3.2 control Circuit and implementation
Based on equation (22), an optimal K value such that error is minimized, i.e., an optimal fixed on-time ratio, can be found and applied to the sawtooth wave generating circuit (10) shown in fig. 6. Compared with the sawtooth wave generating circuit under the conventional COT control mode shown in FIG. 7, the SCOT has the first timing capacitor C added 3 And a switch tube S 5 And the parallel branch circuit is formed. Under the COT control mode, the on-time expression of the output signal is as follows:
that is, the on-time is equation (23) regardless of whether the converter is operating in Flyback or Buck phases. In contrast, SCOT is controlled by switching tube S 5 To turn on and off the capacitor and thereby change the value of the equivalent timing capacitor in the circuit.
In the Flyback stage, a switching tube S 5 The equivalent timing capacitor is only the second timing capacitor C 4 The on time is as follows:
in the Buck stage, the switch tube S 5 The conduction and equivalent timing capacitance is the first timing capacitance C 3 And a second timing capacitor C 4 Parallel connection, the conduction time is as follows:
thus, by controlling C 3 And C 4 The magnitude relation of the capacitance can realize the fixed on-time ratio K of the two working phases, thereby maximizing the power factor on the basis of simplifying the control loop.
Setting test conditions: the effective value of the input voltage is 110V, the frequency f=50Hz, the switching voltage is 55V, the output voltage is 100V, the output power is 100W, and the transformer T 1 And T 2 The turns ratio of (2:1) is 2, and the input voltage v of the novel Buck power factor correction converter is obtained in Input current i in Primary inductor current i Lp1 、i Lp2 Secondary inductor current i Ls1 、i Ls2 And output voltage V o As shown in figure 9, when the input voltage is smaller, the Buck cannot work due to the dead zone, and the parallel auxiliary Flyback circuit replaces the dead zone process of the traditional Buck, so that the input current still exists near the zero crossing of the input voltage, and the power factor of the converter is effectively improved; in addition, SCOT control is adopted, so that the defects of large peak value of inductance current, large conduction loss of a switching tube and lower PF value at a low voltage in the traditional COT control are overcome, power transmission is balanced, the power factor of the converter is further improved, the power factor is larger than 0.97 in the full voltage range, and high power factor input is realized.
According to the analysis, the conversion circuit and the control method thereof provided by the utility model can realize higher power factor, solve the problem of dead zone of input current of the traditional Buck PFC converter, and meanwhile, the control of the sectional fixed on time ensures that the power transmission is more balanced, and further improves the power factor of the converter.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present utility model.
The above describes a novel Buck power factor correction converter provided by the present utility model in detail, and specific examples are applied herein to illustrate the principles and embodiments of the present utility model, and the above examples are only used to help understand the method and core ideas of the present utility model; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present utility model, the present description should not be construed as limiting the present utility model in view of the above.
Claims (10)
1. The novel Buck power factor correction converter is characterized by comprising a main power circuit and a control circuit, wherein the main power circuit comprises an alternating current source, an EMI filter, two sets of parallel Buck and auxiliary Flyback circuits which respectively work on positive and negative half cycles of a power frequency power supply, and an output filter capacitor C connected in series 1 And C 2 Load R o The method comprises the steps of carrying out a first treatment on the surface of the The control circuit comprises a voltage sampling circuit, an error amplifying circuit, a sawtooth wave generating circuit, a voltage comparator CMP1, a zero crossing detection circuit, an RS trigger and a switch gating circuit;
the main power circuit comprises an alternating current source (1), an EMI filter (2), a positive half-cycle Buck-Flyback PFC circuit (3), a negative half-cycle Buck-Flyback PFC circuit (4) and an output filter capacitor C 1 (5) Output filter capacitor C 2 (6) And a DC load (7); the alternating current source (1) is connected with the input port of the EMI filter (2), and the upper end of the output port of the EMI filter (2) is connected with the diode D 1 (301) And diode D 5 (304) Anode, diode D of (c) 2 (401) And diode D 6 (404) The lower end of the output port of the EMI filter (2) is connected with the diode D 3 (306) Anode, diode D of (c) 4 (406) Cathode of (a) switching tube S 3 (305) Source electrode of (S) switch tube 4 (405) Drain electrode of (C), output filter capacitor (C) 1 (5) Negative electrode of (2) and output filter capacitor C 2 (6) The positive pole of the positive half cycle Buck-Flyback PFC circuit (3) is connected with the negative half cycle Buck-Flyback PFC circuit (4) as a neutral line; in the positive half cycle Buck-Flyback PFC circuit (3), a diode D 1 (301) Cathode and switching tube S of (2) 1 (302) Is connected with the drain electrode of the switch tube S 1 (302) Source electrode of (C) is connected with diode D 3 (306) Cathode of (d) and transformer T 1 (303) The homonymous ends of the secondary windings are connected, and the transformer T 1 (303) Output filter capacitor C with different-name end connection of secondary winding 1 (5) And the upper end of the direct current load (7), diode D 5 (304) A kind of electronic deviceCathode and transformer T 1 (303) The same-name ends of the primary windings are connected, and the transformer T 1 (303) Different-name terminating switch tube S of primary winding 3 (305) Drain electrode of transformer T 1 (303) The same name end of the third winding is connected with the primary side ground, and the transformer T 1 (303) The different name end of the third winding outputs zero crossing detection signal v ZCD1 Giving the control circuit; in the negative half cycle Buck-Flyback PFC circuit (4), a filter capacitor C is output 2 (6) The negative pole of the (C) is connected with the lower end of the DC load (7) and the transformer T 2 (403) The synonym end of the secondary winding is grounded and connected to the ground, the transformer T 2 (403) The same-name end of the secondary winding is connected with a diode D 4 (406) Anode and switching tube S of (2) 2 (402) Is connected with the drain electrode of the switch tube S 2 (402) Source electrode of (D) and diode D 2 (401) Anode of (C) is connected with switch tube S 4 (405) Source electrode of (1) is connected with transformer T 2 (403) Different name end of primary winding and transformer T 2 (403) Homonymous terminal of primary winding and diode D 6 (404) Is connected with the anode of the transformer T 2 (403) The same name end of the third winding is connected with the primary side ground, and the transformer T 2 (403) The different name end of the third winding outputs zero crossing detection signal v ZCD2 Giving the control circuit;
the control circuit comprises a voltage sampling circuit (8), an error amplifying circuit (9), a sawtooth wave generating circuit (10), a first voltage comparator (11), a zero crossing detection circuit (12), an RS trigger (13) and a switch gating circuit (14); the voltage sampling circuit (8) is connected with the direct current load (7) of the main power circuit in parallel and is used for collecting the output voltage of the main power circuit; the input end of the error amplifying circuit (9) is connected with the output end of the voltage sampling circuit (8), the output end of the error amplifying circuit (9) is connected with the negative end of the first voltage comparator (11), and the error amplifying circuit (9) is used for outputting an error signal of the output voltage of the main power circuit; the sawtooth wave generating circuit (10) generates sawtooth wave signals by repeatedly charging and discharging the capacitor through a direct current source, and the output end of the sawtooth wave generating circuit is connected to the positive end of the first voltage comparator (11); the output end of the first voltage comparator (11) is connected with the R end of the RS trigger (13), and the S end of the RS trigger (13) is connected with the zero-crossing detection circuit (12)The output of the RS trigger (13) is connected with the input of the switch gating circuit (14); the zero-crossing detection circuit (12) has an input of a zero-crossing detection signal v passing through an adder ZCD1 And v ZCD2 The method comprises the steps of carrying out a first treatment on the surface of the The switch gating circuit (14) judges which switch tube is driven to be conducted by comparing the instantaneous voltage of the alternating current source (1) with zero and switching voltage, and the output of the switch tube is a switch tube S 1 (302) Switch tube S 2 (402) Switch tube S 3 (305) And a switch tube S 4 (405) Is connected to the gate of each switching tube.
2. The novel Buck power factor correction converter as claimed in claim 1, wherein the main power circuit adopts a connection mode of input parallel connection and output series connection, namely, the Buck circuit and the auxiliary Flyback circuit are integrated in parallel at the input end, and whether the two circuits work or not depends on the magnitude relation between the instantaneous voltage and the switching voltage of the alternating current source (1), and the filter capacitor C is output 1 (5) And output filter capacitor C 2 (6) At the output, the output terminals are connected in series, each carrying half of the output voltage.
3. The novel Buck power factor correction converter according to claim 1, wherein the main power circuit has two independent Buck-Flyback PFC circuits, namely a positive half-cycle Buck-Flyback PFC circuit (3) and a negative half-cycle Buck-Flyback PFC circuit (4), and takes a neutral line as a boundary line, when the instantaneous voltage of the ac source (1) is greater than zero, the positive half-cycle Buck-Flyback PFC circuit (3) above the neutral line operates, and when the instantaneous voltage of the ac source (1) is less than zero, the negative half-cycle Buck-Flyback PFC circuit (4) below the neutral line operates.
4. The novel Buck power factor correction converter of claim 1, wherein said transformer T 1 (303) And a transformer T 2 (403) Comprising the following steps: the primary winding is used as a primary inductor of an auxiliary Flyback loop, the secondary winding is used as a secondary inductor of a Buck loop, and the third winding is used for collecting zero-crossing detection signals; and former and auxiliaryThe turns ratio of the edge is n 1, and the left ends of the three windings are the same name ends.
5. The novel Buck power factor correction converter according to claim 1, wherein the voltage sampling circuit (8) comprises a first voltage dividing resistor (801) and a second voltage dividing resistor (802) which are connected in series, the first voltage dividing resistor (801) and the second voltage dividing resistor (802) are connected in parallel with two ends of a direct current load (7) of the novel Buck power factor correction converter to serve as input ends of the voltage sampling circuit (8), and a common end of the first voltage dividing resistor (801) and the second voltage dividing resistor (802) serves as output ends of the voltage sampling circuit (8).
6. The novel Buck power factor correction converter of claim 1, wherein the error amplifier circuit (9) includes a loop compensation circuit (901), an error amplifier (902), and a first reference power supply (903); the loop compensation circuit (901) is connected in parallel with the negative end and the output end of the error amplifier (902), the positive end of the error amplifier (902) is connected with the positive end of the first reference power supply (903), the negative electrode of the first reference power supply (903) is used as the reference voltage end of the error amplifier circuit (9), the output end of the error amplifier (902) is used as the output end of the error amplifier circuit (9), and the negative end of the error amplifier (902) is used as the input end of the error amplifier circuit (9).
7. The novel Buck power factor correction converter as claimed in claim 1, wherein the sawtooth wave generating circuit (10) comprises a charging current source (1001) and a switching tube S 5 (1002) First timing capacitor C 3 (1003) Second timing capacitor C 4 (1004) And a switch tube S 6 (1005) The method comprises the steps of carrying out a first treatment on the surface of the The negative electrode of the charging current source (1001) is grounded, the positive electrode is used as a first input end and is connected with the switch tube S 5 (1002) One end of (C) a second timing capacitor (C) 4 (1004) Positive electrode of (c) and switching tube S 6 (1005) One end of the switch tube S is connected with the positive end of the first voltage comparator (11) 5 (1002) And the other end of the first timing capacitor C 3 (1003) The positive electrode of the first timing capacitor C 3 (1003) Negative electrode of (C) second timing capacitor 4 (1004) Is connected with the negative electrode of the switch tube S 6 (1005) The other ends of the two are all grounded; a fifth output v of the switch gating circuit (14) gb Is connected to a second input of the sawtooth wave generating circuit (10) for controlling the switching tube S 5 (1002) The Q end of the RS trigger (13) is connected with the third input end of the sawtooth wave generating circuit (10) to control the switching tube S 6 (1005) Is turned on and off; the sawtooth wave generating circuit (10) outputs sawtooth wave signals with different on-time according to the main power circuit working in a Buck or Flyback stage.
8. A novel Buck power factor correction converter in accordance with claim 1, wherein the switch gating circuit (14) includes v in A detection circuit (141), a phase detection circuit (142), a first subtractor (143), a second subtractor (144), a logic circuit (145); further, the phase detection circuit (142) includes a second voltage comparator (1421), a third voltage comparator (1422), a fourth voltage comparator (1423), a fifth voltage comparator (1424), a second reference power supply (1425), and a third reference power supply (1426), and the logic and driving circuit (145) includes a first and gate (1451), a second and gate (1452), a third and gate (1453), a fourth and gate (1454), a nor gate (1455), a first driving circuit (1456), a second driving circuit (1457), a third driving circuit (1458), a fourth driving circuit (1459), and a fifth driving circuit (14510); wherein the v in The detection circuit (141) is mainly used for detecting the instantaneous voltage of the AC source (1), v in The output of the detection circuit (141) is connected with the positive input ends of a second voltage comparator (1421) and a fourth voltage comparator (1423) in the phase detection circuit (142), the negative input ends of a third voltage comparator (1422) and a fifth voltage comparator (1424), the negative input end of the second voltage comparator (1421) is connected with the positive input end of the third voltage comparator (1422) and grounded, the negative input end of the fourth voltage comparator (1423) and the positive input end of the fifth voltage comparator (1424) are respectively connected with a second reference power supply (1425) and a third reference power supply (1426)) The anodes of the second reference power supply (1425) and the third reference power supply (1426) are connected to the ground, the output ends of the second voltage comparator (1421) and the third voltage comparator (1422) are respectively connected to the positive input ends of the first subtracter (143) and the second subtracter (144), the output end of the fourth voltage comparator (1423) is connected to the negative input end of the first subtracter (143) and one input end of a first AND gate (1451) in the logic and driving circuit (145), and the output end of the fifth voltage comparator (1424) is connected to the negative input end of the second subtracter (144) and one input end of a third AND gate (1453) in the logic and driving circuit (145); an output end of the first subtracter (143) is connected with one input end of a second AND gate (1452) and a NOR gate (1455), and an output end of the second subtracter (144) is connected with one input end of a fourth AND gate (1454) and the other input end of the NOR gate (1455); the other input ends of the first AND gate (1451), the second AND gate (1452), the third AND gate (1453) and the fourth AND gate (1454) are respectively connected with the Q end of the RS trigger (13), the output ends of the first AND gate (1451), the second AND gate (1452), the third AND gate (1453), the fourth AND gate (1454) and the NOR gate (1455) are respectively connected with the input ends of the first driving circuit (1456), the second driving circuit (1457), the third driving circuit (1458), the fourth driving circuit (1459) and the fifth driving circuit (14510), and the first driving circuit (1456), the second driving circuit (1457), the third driving circuit (1458) and the fourth driving circuit (1459) respectively output driving signals v g1 、v g2 、v g3 And v g4 And are respectively connected to a switching tube S in the main power circuit 1 (302) Switch tube S 2 (402) Switch tube S 3 (305) And a switch tube S 4 (405) The output end of the fifth driving circuit (14510) outputs a driving signal v gb A second input terminal connected to the sawtooth wave generating circuit (10); the output ends of the first driving circuit (1456), the second driving circuit (1457), the third driving circuit (1458), the fourth driving circuit (1459) and the fifth driving circuit (14510) are respectively used as a first output end, a second output end, a third output end, a fourth output end and a fifth output end of the switch gating circuit (14), and the v in An input end of the detection circuit (141) and a Q end of the RS trigger (13) serve as input ends of the switch gating circuit (14).
9. The novel Buck pfc converter of claim 8, wherein the second reference power supply (1425) and the third reference power supply (1426) are switching voltages V between positive half-cycle Buck and Flyback modes, respectively b And a switching voltage-V between negative half-cycle Buck and Flyback modes b To make the switching between the two operating states smoother, the size is set to be slightly higher than V o A value of/2.
10. The novel Buck power factor correction converter as claimed in claim 1, wherein the Q end of the RS trigger (13) outputs a total driving signal to pass through the switch gating circuit (14) to generate different positive or negative half cycles, buck or Flyback switching tube S 1 (302) Switch tube S 2 (402) Switch tube S 3 (305) Switch tube S 4 (405) And a switch tube S 5 (1002) Is provided.
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