CN219695367U

CN219695367U - Integrated circuit high-temperature service life test system

Info

Publication number: CN219695367U
Application number: CN202321224329.7U
Authority: CN
Inventors: 胡久恒; 许卫; 胡久旺; 安浙文
Original assignee: Hangzhou Gaokun Electronic Technology Co ltd
Current assignee: Hangzhou Gaokun Electronic Technology Co ltd
Priority date: 2023-05-19
Filing date: 2023-05-19
Publication date: 2023-09-15
Anticipated expiration: 2033-05-19

Abstract

The utility model discloses a high-temperature service life test system of an integrated circuit, belonging to the technical field of testing; the system comprises an FPGA module, a microcontroller ARM, a power supply module and an aging box; the burn-in box is internally provided with a device under test DUT; the FPGA module and the microcontroller ARM are both connected with the level conversion circuit; the VDD pin and the GND pin of the DUT are connected with pins corresponding to the power supply module; the FPGA module is connected with the upper computer. According to the utility model, for Scan and Mbit tests, an FPGA module is adopted to apply an excitation signal to a DUT according to pattern file data, and the Scan out of the DUT is read back and compared with the original pattern to confirm that the output accords with the expectation; for the Function test, a microcontroller ARM is adopted as a master control, and firmware burning and register value reading can be respectively and independently carried out on each DUT.

Description

Integrated circuit high-temperature service life test system

Technical Field

The utility model relates to the technical field of testing, in particular to a high-temperature service life test system for an integrated circuit.

Background

When the integrated circuit device or module is aged, an external excitation signal is applied to the integrated circuit device or module except for providing a working power supply, the aging process is called dynamic aging, and the integrated circuit high-temperature dynamic aging system can be used for carrying out high-temperature dynamic aging tests on various digital, analog and digital-analog hybrid integrated circuits and micro-electronic circuits such as SOC circuits, microprocessors, memories and the like. The current monitoring of a single DUT can not be carried out by the existing foreign ICHTOL, the internal register value can not be read by the MCU device, and the output state of the DUT can not be read back in real time by the scan test. The prior art scheme cannot monitor the current of a single device, only can monitor the total voltage and current, and cannot read the register value and state back. The conventional scheme can only be used for ageing of a conventional combinational logic circuit, and for an integrated circuit such as an MCU, the ageing state of the integrated circuit cannot be effectively detected, so that ageing screening, test authentication and the like are not facilitated.

Disclosure of Invention

The utility model aims to provide an efficient integrated circuit high-temperature service life test system.

In order to solve the technical problems, the utility model provides an integrated circuit high-temperature service life test system, which comprises an FPGA module, a microcontroller ARM, a power supply module and an aging box;

the burn-in box is internally provided with a device under test DUT;

the FPGA module and the microcontroller ARM are both connected with the level conversion circuit;

the power module supplies power for the FPGA module, the microcontroller ARM and the DUT;

the DUT includes SCAN_IN pin, SCAN_OUT pin, SCAN_EN pin, SCAN_COM pin, NRST pin, SCAN_CLK pin, SWCLK pin, SWDIO pin, VDD pin and GND pin;

the SCAN_IN pin, the SCAN_OUT pin, the SCAN_EN pin, the SCAN_COM pin, the NRST pin, the SCAN_CLK pin, the SWCLK pin and the SWDIO pin of the DUT are all connected with pins corresponding to the level conversion circuit;

the VDD pin and the GND pin of the DUT are connected with pins corresponding to the power supply module;

the FPGA module is connected with the upper computer.

Preferably, the power module comprises a Direct Current (DC) power supply and a distributed power supply group;

the direct current power supply DC directly supplies power to the level conversion circuit;

the direct current power supply DC supplies power to the FPGA module after passing through the first voltage conversion circuit;

the direct current power supply DC supplies power to the microcontroller ARM after passing through the second voltage conversion circuit;

the direct current power supply DC is connected with a distributed power supply group, and the distributed power supply group supplies power to a device under test DUT through a power supply control module;

and the VDD pin and the GND pin of the DUT are connected with pins corresponding to the power supply control module.

Preferably, the distributed power group comprises a number of distributed power DPSs.

Preferably, the power control module comprises a DPS power management module, a current acquisition module, a power switch control module and an overvoltage and overcurrent protection circuit;

the distributed power supply DPS is connected with a VDD pin and a GND pin of a device under test DUT after sequentially passing through a DPS power supply management module, a current acquisition module and an overvoltage and overcurrent protection circuit;

the current acquisition module is connected with the power switch control module;

the power switch control module is connected with the DPS power management module.

Preferably, the direct current power supply DC is a 36V direct current power supply.

Preferably, the first voltage conversion circuit and the second voltage conversion circuit are both 36V to 5V conversion circuits.

Preferably, the microcontroller ARM is an STM32F429 chip.

Preferably, the FPGA module is connected with the upper computer through a hundred meganet port.

Compared with the prior art, the utility model has the beneficial effects that:

according to the utility model, for Scan and Mbit tests, an FPGA module is adopted to apply an excitation signal to a DUT according to pattern file data, and the Scan out of the DUT is read back and compared with the original pattern to confirm that the output accords with the expectation; for the Function test, a microcontroller ARM is adopted as a master control, and firmware burning and register value reading can be respectively and independently carried out on each DUT.

Drawings

The following describes the embodiments of the present utility model in further detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a single channel system of an integrated circuit high temperature operating life test system;

FIG. 2 is a schematic diagram of the structure of a DUT;

FIG. 3 is a schematic diagram of firmware burn-in and register values of four DUT's under test of example 1;

fig. 4 is a schematic diagram of a real-time scanout waveform review of example 1.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model. The present utility model may be embodied in many other forms than those herein described, and those skilled in the art will readily appreciate that the present utility model may be similarly embodied without departing from the spirit or essential characteristics thereof, and therefore the present utility model is not limited to the specific embodiments disclosed below.

The terminology used in the one or more embodiments of the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of the specification. As used in this specification, one or more embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used in one or more embodiments of the present specification refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It should be understood that, although the terms first, second, etc. may be used in one or more embodiments of this specification to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first may also be referred to as a second, and similarly, a second may also be referred to as a first, without departing from the scope of one or more embodiments of the present description. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.

The utility model is described in further detail below with reference to the attached drawing figures:

the utility model provides an integrated circuit high-temperature service life test system, which comprises an FPGA module, a microcontroller ARM, a power supply module and an aging box;

the burn-in box is internally provided with a device under test DUT;

the FPGA module is connected with the upper computer.

Preferably, the microcontroller ARM is an STM32F429 chip.

In order to better illustrate the technical effects of the present utility model, the present utility model provides the following specific embodiments to illustrate the above technical flow:

example 1, an integrated circuit high temperature operational life test system:

the design and system block diagram of this embodiment is shown in fig. 1;

the power supply part (direct current power supply DC and distributed power supply DPS) of the embodiment realizes the power supply, voltage and current monitoring of the DUT; the drive board adopts the design of combining an FPGA module and a microcontroller ARM, the FPGA module realizes communication, scan signal application and signal review, and the microcontroller ARM reads the firmware and the register of each DUT through simulating SWD read-write time sequence, so that the running result can be read back in real time.

According to the voltage and current monitoring scheme, voltage and current monitoring can be performed on each DUT, and the structure of four DUTs is shown in FIG. 2;

the firmware burning and register value reading result of the DUT of the present embodiment is shown in fig. 3;

in this embodiment, the real-time scanout waveform is checked back, so that the oscilloscope is omitted to see the output of each DUT, the test time is saved, and the obtained real-time scanout waveform is shown in FIG. 4.

The SCAN control pin and the SCAN detection pin of the DUT are connected with pins corresponding to the level conversion circuit; and the VDD pin and the GND pin of the DUT are connected with pins corresponding to the DPS power management module.

The embodiment is designed specifically for solving the problems of the prior art, for Scan and Mbit tests, an FPGA module is adopted to apply excitation signals to a DUT according to pattern file data, and the Scan out of the DUT is read back, compared with the original pattern file, and the output is confirmed to accord with expectations, and the FPGA module can adopt an EP2C8Q208C8N chip and the like; for the Function test, an MCU (microcontroller ARM) with an ARM Cortex-M4 kernel is adopted as a master control, and an STM32F429 chip and the like can be adopted to respectively and independently perform firmware burning and register value reading on each device DUT to be tested. Wherein 8 devices under test DUTs are a group of control signals, and 5 groups are total.

The integrated circuit high-temperature service life test system has the advantages that:

1. the whole equipment supports 16 channels, 40 DUTs are simultaneously aged in each channel, and the temperature of an aging box is 150 degrees at most;

2. aging supports three aging modes of scan/mbist/function;

the highest frequency of the scan test supports 10MHz, and scan out detection and waveform display are supported;

4. supporting the monitoring of the running current of each DUT and the reading of the register value of each DUT;

5. and supporting overvoltage protection of software and hardware and overcurrent protection of hardware.

The foregoing is merely illustrative of specific embodiments of the present utility model, and the scope of the present utility model is not limited thereto, but any changes or substitutions within the technical scope of the present utility model should be covered by the scope of the present utility model. Therefore, the protection scope of the present utility model shall be subject to the protection scope of the claims.

Claims

1. An integrated circuit high temperature service life test system, characterized in that: the device comprises an FPGA module, a microcontroller ARM, a power supply module and an aging box;

the burn-in box is internally provided with a device under test DUT;

the FPGA module is connected with the upper computer.

2. The integrated circuit high temperature operational life test system of claim 1, wherein: the power module comprises a Direct Current (DC) power supply and a distributed power supply group;

3. The integrated circuit high temperature operational life test system of claim 2, wherein:

the distributed power group includes a number of distributed power DPSs.

4. The integrated circuit high temperature operational life test system of claim 3, wherein:

the power supply control module comprises a DPS power supply management module, a current acquisition module, a power supply switch control module and an overvoltage and overcurrent protection circuit;

5. The integrated circuit high temperature operational life test system of claim 2, wherein:

the direct current power supply DC is 36V direct current power supply.

6. The integrated circuit high temperature operational life test system of claim 2, wherein:

the first voltage conversion circuit and the second voltage conversion circuit are both 36V-to-5V conversion circuits.

7. The integrated circuit high temperature operational life test system of claim 1, wherein:

the microcontroller ARM is an STM32F429 chip.

8. The integrated circuit high temperature operational life test system of claim 1, wherein:

the FPGA module is connected with the upper computer through a hundred meganet port.