CN219676576U - Interface circuit compatible with LVDS signals and EDP signals - Google Patents
Interface circuit compatible with LVDS signals and EDP signals Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The utility model provides an interface circuit compatible with LVDS signals and EDP signals, which comprises a power supply, an EDP signal-to-LVDS signal circuit and an EDP signal direct transmission circuit, wherein the input end of the EDP signal-to-LVDS signal circuit is connected with the output end of a central processing unit, the power supply is connected with the EDP signal-to-LVDS signal circuit, the EDP signal direct transmission circuit and a display main board in a power supply way, and the output end of the EDP signal-to-LVDS signal circuit and the output end of the EDP signal direct transmission circuit are connected with the input end of the display main board. The beneficial effects of the utility model are as follows: the EDP signal can be transmitted to the LVDS signal display main board after being converted into the LVDS signal, and the EDP signal can be directly transmitted to the EDP signal display main board.
Description
Technical Field
The utility model relates to the technical field of interface circuits, in particular to an interface circuit compatible with LVDS signals and EDP signals.
Background
In the field of computers, a central processing unit (CPU, english) is one of the main devices of an electronic computer, and is a core accessory in the computer. Its function is mainly to interpret computer instructions and process data in computer software. All operations in the computer are core components for reading instructions, decoding the instructions and executing the instructions by the CPU. The CPU is now commonly used in many electronic devices, such as mobile terminals, industrial terminals, PCs, etc.
LVDS (Low-VoltageDifference Signaling), a Low-voltage differential signal, is a signal transmission mode proposed by the national semiconductor company of United states in 1994, is a level standard, and LVDS interface, also called RS-644 bus interface, is a data transmission and interface technology which occurs only in the 90 th year of the 20 th century.
EDP (EmbeddedDisplayport), i.e. the embedded display port, is an internal digital interface based on Displayport architecture and protocol, and EDP is commonly applied to various products with embedded display panels, such as notebook computers, tablet computers, etc. The EDP signal is mainly composed of MainLink, AUXCH and HPD.
At present, the display signal of the display main board is usually an EDP signal sent by the central processing unit, and is finally displayed on the display screen after being received by the display main board of the display screen, but the display main board can only directly display one display signal, and the most widely used display main boards at present are an LVDS signal display main board and an EDP signal display main board. Therefore, when the display main board is an LVDS signal display main board, an EDP signal is required to be converted by using an EDP signal-to-LVDS signal interface and then transmitted to the LVDS signal display main board for display; when the display main board is an EDP signal display main board, the EDP signal interface needs to be replaced, the switching is frequent, and the use is very troublesome for a user.
Disclosure of Invention
In order to solve the problems in the prior art, the utility model provides an interface circuit compatible with LVDS signals and EDP signals, which is arranged between a central processing unit and a display main board, and through an EDP signal-to-LVDS signal circuit and an EDP signal direct transmission circuit which are mutually matched, the purposes of transmitting the EDP signals to an LVDS signal display main board after converting the LVDS signals into the LVDS signal display main board and directly transmitting the EDP signals to the EDP signal display main board are achieved, no matter whether the display main board is the LVDS signal display main board or the EDP signal display main board, no signal interface is required to be switched, the use is simple, the time and the labor are saved, and the problem that the LVDS signal display main board and the EDP signal display main board in the prior art are very troublesome in that the display signal interface is required to be frequently switched is solved.
The utility model provides an interface circuit compatible with LVDS signals and EDP signals, which is arranged between a central processing unit and a display main board and comprises a power supply, an EDP signal-to-LVDS signal circuit and an EDP signal direct transmission circuit, wherein the input end of the EDP signal-to-LVDS signal circuit is connected with the output end of the central processing unit, the power supply is in power supply connection with the EDP signal-to-LVDS signal circuit, the EDP signal direct transmission circuit and the display main board, the output end of the EDP signal-to-LVDS signal circuit and the output end of the EDP signal direct transmission circuit are connected with the input end of the display main board, the EDP signal-to-LVDS signal circuit can convert an EDP signal sent by the central processing unit into an LVDS signal and then transmit the LVDS signal to the LVDS signal display main board, and the EDP signal direct transmission circuit can directly transmit the EDP signal sent by the central processing unit to the EDP signal display main board.
The utility model further improves, the display main board is provided with a display signal receiving interface, a resistor R1 and a resistor R2, the display signal receiving interface is provided with 44 pins, wherein the 9 th pin of the display signal receiving interface is connected with one end of the resistor R1, the other end of the resistor R1 is connected with the power supply, the 1 st pin of the display signal receiving interface is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the power supply, the 13 th, 15 th, 32 nd, 34 th, 36 th and 38 th pins of the display signal receiving interface are connected with the output end of the EDP signal direct transmission circuit, and the 19 th, 21 nd, 23 th, 25 th, 27 th, 29 th, 31 th, 33 th and 35 th pins of the display signal receiving interface are connected with the output end of the EDP signal converting LVDS signal circuit.
The utility model further improves, the EDP signal converting LVDS signal circuit comprises a conversion chip U30, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a resistor R501 and a resistor R502, wherein the conversion chip U30 is provided with 68 pins, a 64 th pin of the conversion chip U30 is connected with one end of the capacitor C7, a 65 th pin of the conversion chip U30 is connected with one end of the capacitor C8, a 61 th pin of the conversion chip U30 is connected with one end of the capacitor C9, a 62 th pin of the conversion chip U30 is connected with one end of the capacitor C10, a 43 th pin of the conversion chip U30 is connected with one end of the capacitor C11, a 44 th pin of the conversion chip U30 is connected with one end of the capacitor C12, the other end of the capacitor C7, the other end of the capacitor C8, the other end of the capacitor C9, the other end of the capacitor C10, the other end of the capacitor C11 and the other end of the capacitor C12 are connected with the output end of the central processing unit, the 54 th pin of the conversion chip U30 is connected with one end of the resistor R501, the 53 rd pin of the conversion chip U30 is connected with one end of the resistor R502, the other end of the resistor R501 and the other end of the resistor R502 are connected with the power supply, and the 22 nd, 23 nd, 26 nd, 27 nd, 28 nd, 29 nd, 30 nd, 31 nd, 24 nd and 25 nd pins of the conversion chip U30 are respectively connected with the 19 nd, 21 nd, 23 nd, 25 nd, 27 nd, 29 nd, 31 nd, 33 nd, 35 nd and 37 nd pins of the display signal receiving interface.
The utility model further improves, the EDP signal direct transmission circuit comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a resistor R3 and a resistor R4, wherein one end of the capacitor C1 is connected with a 13 th pin of the display signal receiving interface and one end of the resistor R3, the other end of the resistor R3 is connected with the power supply, one end of the capacitor C2 is connected with a 15 th pin of the display signal receiving interface and one end of the resistor R4, the other end of the resistor R4 is grounded, one end of the capacitor C3 is connected with a 32 th pin of the display signal receiving interface, one end of the capacitor C4 is connected with a 36 th pin of the display signal receiving interface, one end of the capacitor C6 is connected with a 38 th pin of the display signal receiving interface, and the other end of the capacitor C1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4, and the other end of the capacitor C5 are connected with a central processor.
The utility model is further improved, and the model of the conversion chip U30 is CH7511B.
According to the utility model, the resistance value of the resistor R1 is 4.7KΩ, and the resistance value of the resistor R2 is 4.7KΩ.
According to the utility model, the resistance value of the resistor R3 is 100KΩ, and the resistance value of the resistor R4 is 100KΩ.
According to the utility model, the capacitance values of the capacitor C1, the capacitor C2, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6, the capacitor C7, the capacitor C8, the capacitor C9, the capacitor C10, the capacitor C11 and the capacitor C12 are all 0.1uF.
Compared with the prior art, the utility model has the beneficial effects that: the utility model provides an interface circuit compatible with LVDS signals and EDP signals, which is arranged between a central processing unit and a display main board, and through an EDP signal-to-LVDS signal circuit and an EDP signal direct transmission circuit which are mutually matched, the EDP signal-to-LVDS signal circuit can convert the EDP signals sent by the central processing unit into LVDS signals and then transmit the LVDS signals to an LVDS signal display main board, the EDP signal direct transmission circuit can directly transmit the EDP signals sent by the central processing unit to the EDP signal display main board, the purposes that the EDP signals can be transmitted to the LVDS signal display main board after being converted into LVDS signals and can also directly transmit the EDP signals to the EDP signal display main board are achieved, no matter whether the display main board is the LVDS signal display main board or the EDP signal display main board needs to switch signal interfaces are achieved, the use is simple, time and labor are saved, and the problem that the LVDS signal display main board and the EDP signal display main board needs frequent switching of the display signal interfaces in the prior art is very troublesome is solved.
Drawings
In order to more clearly illustrate the utility model or the solutions of the prior art, a brief description will be given below of the drawings used in the description of the embodiments or the prior art, it being obvious that the drawings in the description below are some embodiments of the utility model and that other drawings can be obtained from them without the inventive effort of a person skilled in the art.
FIG. 1 is a circuit diagram of an interface circuit compatible with LVDS signals and EDP signals in accordance with the present utility model;
fig. 2 is a circuit diagram of the EDP signal to LVDS signal circuit of the present utility model.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model; the terms "comprising" and "having" and any variations thereof in the description of the utility model and the claims and the description of the drawings above are intended to cover a non-exclusive inclusion. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the utility model. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
In order to make the person skilled in the art better understand the solution of the present utility model, the technical solution of the embodiment of the present utility model will be clearly and completely described below with reference to the accompanying drawings.
As shown in fig. 1-2, the interface circuit compatible with LVDS signals and EDP signals provided by the utility model is arranged between a central processing unit and a display main board, and comprises a power supply, an EDP signal-to-LVDS signal circuit and an EDP signal direct transmission circuit, wherein the input end of the EDP signal-to-LVDS signal circuit and the input end of the EDP signal direct transmission circuit are connected with the output end of the central processing unit, the power supply is connected with the EDP signal-to-LVDS signal circuit, the EDP signal direct transmission circuit and the display main board in a power supply way, and the output end of the EDP signal-to-LVDS signal circuit and the output end of the EDP signal direct transmission circuit are connected with the input end of the display main board. In this embodiment, the EDP signal-to-LVDS signal circuit can convert the EDP signal sent by the central processor into an LVDS signal and then transmit the LVDS signal to the LVDS signal display main board, and the EDP signal direct transmission circuit can directly transmit the EDP signal sent by the central processor to the EDP signal display main board, so that the purpose of not only completing the transmission of the EDP signal to the LVDS signal display main board after the conversion of the EDP signal to the LVDS signal, but also directly transmitting the EDP signal to the EDP signal display main board is achieved, no matter whether the display main board is the LVDS signal display main board or the EDP signal display main board, no need to switch signal interfaces, and the use is simple, time-saving and labor-saving.
As shown in FIG. 1, the display main board is provided with a display signal receiving interface, a resistor R1 and a resistor R2, the display signal receiving interface is provided with 44 pins, wherein the 9 th pin of the display signal receiving interface is connected with one end of the resistor R1, the other end of the resistor R1 is connected with a power supply, the 1 st pin of the display signal receiving interface is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the power supply, the 13 th, 15 th, 32 th, 34 th, 36 th and 38 th pins of the display signal receiving interface are connected with the output end of the EDP signal direct transmission circuit, and the 19 th, 21 th, 23 th, 25 th, 27 th, 29 th, 31 th, 33 th, 35 th and 37 th pins of the display signal receiving interface are connected with the output end of the EDP signal to LVDS signal circuit. The resistance of the resistor R1 is 4.7kΩ, the resistance of the resistor R2 is 4.7kΩ, and the capacitance of each of the capacitor C7, the capacitor C8, the capacitor C9, the capacitor C10, the capacitor C11, and the capacitor C12 is 0.1uF. In this embodiment, the display main board is used for receiving the display signal and displaying the display signal on the display screen, and the display main board is mainly divided into an LVDS signal display main board and an EDP signal display main board.
As shown in fig. 1-2, the EDP signal converting LVDS signal circuit comprises a conversion chip U30, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a resistor R501 and a resistor R502, wherein the conversion chip U30 is provided with 68 pins, a 64 th pin of the conversion chip U30 is connected with one end of the capacitor C7, a 65 th pin of the conversion chip U30 is connected with one end of the capacitor C8, a 61 th pin of the conversion chip U30 is connected with one end of the capacitor C9, a 62 th pin of the conversion chip U30 is connected with one end of the capacitor C10, a 43 rd pin of the conversion chip U30 is connected with one end of the capacitor C11, a 44 th pin of the conversion chip U30 is connected with one end of the capacitor C12, the other end of the capacitor C7, the other end of the capacitor C8, the other end of the capacitor C9, the other end of the capacitor C10, the other end of the capacitor C11 and the other end of the capacitor C12 are connected with the output end of the CPU, the 54 th pin of the conversion chip U30 is connected with one end of the resistor R501, the 53 th pin of the conversion chip U30 is connected with one end of the resistor R502, the other end of the resistor R501 and the other end of the resistor R502 are connected with a power supply, and the 22 th, 23 th, 26 th, 27 th, 28 th, 29 th, 30 th, 31 th, 24 th and 25 th pins of the conversion chip U30 are respectively connected with 19 th, 21 th, 23 th, 25 th, 27 th, 29 th, 31 th, 33 th, 35 th and 37 th pins of a display signal receiving interface. The model of the conversion chip U30 is CH7511B. In this embodiment, the EDP signal-to-LVDS signal circuit is configured to convert an EDP signal sent by the central processor into an LVDS signal and transmit the LVDS signal to the LVDS signal display motherboard.
As shown in FIG. 1, the EDP signal direct transmission circuit comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a resistor R3 and a resistor R4, wherein one end of the capacitor C1 is connected with a 13 th pin of a display signal receiving interface and one end of the resistor R3, the other end of the resistor R3 is connected with a power supply, one end of the capacitor C2 is connected with a 15 th pin of the display signal receiving interface and one end of the resistor R4, the other end of the resistor R4 is grounded, one end of the capacitor C3 is connected with a 32 th pin of the display signal receiving interface, one end of the capacitor C4 is connected with a 34 th pin of the display signal receiving interface, one end of the capacitor C5 is connected with a 36 th pin of the display signal receiving interface, one end of the capacitor C6 is connected with a 38 th pin of the display signal receiving interface, and the other end of the capacitor C1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4, the other end of the capacitor C5 and the other end of the capacitor C6 are connected with the output end of the CPU. The resistance of the resistor R3 is 100kΩ, the resistance of the resistor R4 is 100kΩ, and the capacitance of each of the capacitor C1, the capacitor C2, the capacitor C3, the capacitor C4, the capacitor C5, and the capacitor C6 is 0.1uF. In this embodiment, the EDP signal direct transmission circuit is configured to directly transmit the EDP signal sent by the central processor to the EDP signal display motherboard.
Therefore, the utility model provides the interface circuit compatible with the LVDS signals and the EDP signals, which is arranged between the central processing unit and the display main board, and the EDP signals sent by the central processing unit can be converted into LVDS signals by the EDP signal-to-LVDS signal circuit and then transmitted to the LVDS signal display main board through the mutually matched EDP signal-to-LVDS signal circuit and EDP signal direct transmission circuit, and the EDP signal direct transmission circuit can directly transmit the EDP signals sent by the central processing unit to the EDP signal display main board.
The above embodiments are preferred embodiments of the present utility model, and are not intended to limit the scope of the present utility model, which includes but is not limited to the embodiments, and equivalent modifications according to the present utility model are within the scope of the present utility model.
Claims (8)
1. An interface circuit compatible with LVDS signals and EDP signals is arranged between a central processing unit and a display main board, and is characterized in that: the LED display device comprises a power supply, an EDP signal-to-LVDS signal circuit and an EDP signal direct transmission circuit, wherein the input end of the EDP signal-to-LVDS signal circuit is connected with the output end of a central processing unit, the power supply is connected with the EDP signal-to-LVDS signal circuit, the EDP signal direct transmission circuit is in power supply connection with a display main board, the output end of the EDP signal-to-LVDS signal circuit, the output end of the EDP signal direct transmission circuit is connected with the input end of the display main board, the EDP signal-to-LVDS signal circuit can convert an EDP signal sent by the central processing unit into an LVDS signal and then transmit the LVDS signal to the LVDS signal display main board, and the EDP signal direct transmission circuit can directly transmit the EDP signal sent by the central processing unit to the EDP signal display main board.
2. The interface circuit compatible with LVDS signals and EDP signals of claim 1, wherein: the display main board is provided with a display signal receiving interface, a resistor R1 and a resistor R2, wherein the display signal receiving interface is provided with 44 pins, the 9 th pin of the display signal receiving interface is connected with one end of the resistor R1, the other end of the resistor R1 is connected with a power supply, the 1 st pin of the display signal receiving interface is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the power supply, the 13 th, 15 th, 32 th, 34 th, 36 th and 38 th pins of the display signal receiving interface are connected with the output end of the EDP signal direct transmission circuit, and the 19 th, 21 th, 23 th, 25 th, 27 th, 29 th, 31 th, 33 th, 35 th and 37 th pins of the display signal receiving interface are connected with the output end of the EDP signal converting LVDS signal circuit.
3. The interface circuit compatible with LVDS signals and EDP signals of claim 2, wherein: the EDP signal-to-LVDS signal circuit comprises a conversion chip U30, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a resistor R501 and a resistor R502, wherein 68 pins are arranged on the conversion chip U30, a 64 th pin of the conversion chip U30 is connected with one end of the capacitor C7, a 65 th pin of the conversion chip U30 is connected with one end of the capacitor C8, a 61 th pin of the conversion chip U30 is connected with one end of the capacitor C9, a 62 th pin of the conversion chip U30 is connected with one end of the capacitor C10, a 43 rd pin of the conversion chip U30 is connected with one end of the capacitor C11, a 44 th pin of the conversion chip U30 is connected with one end of the capacitor C12, the other end of the capacitor C7, the other end of the capacitor C8, the other end of the capacitor C9, the other end of the capacitor C10, the other end of the capacitor C11 and the other end of the capacitor C12 are connected with the output end of the central processing unit, the 54 th pin of the conversion chip U30 is connected with one end of the resistor R501, the 53 rd pin of the conversion chip U30 is connected with one end of the resistor R502, the other end of the resistor R501 and the other end of the resistor R502 are connected with the power supply, and the 22 nd, 23 nd, 26 nd, 27 nd, 28 nd, 29 nd, 30 nd, 31 nd, 24 nd and 25 nd pins of the conversion chip U30 are respectively connected with the 19 nd, 21 nd, 23 nd, 25 nd, 27 nd, 29 nd, 31 nd, 33 nd, 35 nd and 37 nd pins of the display signal receiving interface.
4. The interface circuit compatible with LVDS signals and EDP signals of claim 3, wherein: the EDP signal direct transmission circuit comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a resistor R3 and a resistor R4, wherein one end of the capacitor C1 is connected with a 13 th pin of a display signal receiving interface and one end of the resistor R3, the other end of the resistor R3 is connected with a power supply, one end of the capacitor C2 is connected with a 15 th pin of the display signal receiving interface and one end of the resistor R4, the other end of the resistor R4 is grounded, one end of the capacitor C3 is connected with a 32 th pin of the display signal receiving interface, one end of the capacitor C4 is connected with a 34 th pin of the display signal receiving interface, one end of the capacitor C5 is connected with a 36 th pin of the display signal receiving interface, the other end of the capacitor C6 is connected with a 38 th pin of the display signal receiving interface, and the other end of the capacitor C1, the other end of the capacitor C3, the other end of the capacitor C4, the other end of the capacitor C5, and the other end of the capacitor C5 are connected with a central processor.
5. The interface circuit compatible with LVDS signals and EDP signals of claim 4, wherein: the model of the conversion chip U30 is CH7511B.
6. The interface circuit compatible with LVDS signals and EDP signals of claim 5, wherein: the resistance value of the resistor R1 is 4.7KΩ, and the resistance value of the resistor R2 is 4.7KΩ.
7. The interface circuit compatible with LVDS signals and EDP signals of claim 6, wherein: the resistance value of the resistor R3 is 100KΩ, and the resistance value of the resistor R4 is 100KΩ.
8. The interface circuit compatible with LVDS signals and EDP signals of claim 7, wherein: the capacitance values of the capacitor C1, the capacitor C2, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6, the capacitor C7, the capacitor C8, the capacitor C9, the capacitor C10, the capacitor C11 and the capacitor C12 are all 0.1uF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320624995.3U CN219676576U (en) | 2023-03-27 | 2023-03-27 | Interface circuit compatible with LVDS signals and EDP signals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320624995.3U CN219676576U (en) | 2023-03-27 | 2023-03-27 | Interface circuit compatible with LVDS signals and EDP signals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219676576U true CN219676576U (en) | 2023-09-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320624995.3U Active CN219676576U (en) | 2023-03-27 | 2023-03-27 | Interface circuit compatible with LVDS signals and EDP signals |
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| Country | Link |
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| CN (1) | CN219676576U (en) |
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- 2023-03-27 CN CN202320624995.3U patent/CN219676576U/en active Active
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