CN219657884U - Readout electronics system - Google Patents
Readout electronics system Download PDFInfo
- Publication number
- CN219657884U CN219657884U CN202321084053.7U CN202321084053U CN219657884U CN 219657884 U CN219657884 U CN 219657884U CN 202321084053 U CN202321084053 U CN 202321084053U CN 219657884 U CN219657884 U CN 219657884U
- Authority
- CN
- China
- Prior art keywords
- signal
- signal processing
- processing module
- output
- signal output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012545 processing Methods 0.000 claims abstract description 127
- 238000006243 chemical reaction Methods 0.000 claims description 21
- 238000007493 shaping process Methods 0.000 claims description 10
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052744 lithium Inorganic materials 0.000 claims description 2
- 238000005259 measurement Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000001956 neutron scattering Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 239000006123 lithium glass Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E30/00—Energy generation of nuclear origin
- Y02E30/30—Nuclear fission reactors
Landscapes
- Measurement Of Radiation (AREA)
Abstract
The present disclosure provides a readout electronics system comprising: the front-end signal processing device at least comprises a first signal processing module and a second signal processing module, wherein the first signal processing module is used for processing the electric signals output by the two-dimensional neutron detector so as to obtain two-dimensional digital signal output and single-channel analog signal output; the second signal processing module is used for processing the electric signal output by the one-dimensional neutron detector to obtain pulse signal output or energy signal output; the data processor comprises a programmable logic array and a multi-interface circuit, the multi-interface circuit at least comprises a first interface circuit and a second interface circuit, the signal output of the first signal processing module can be transmitted to the programmable logic array through the first interface circuit, and the signal output of the second signal processing module can be transmitted to the programmable logic array through the second interface circuit; the first signal processing module and the second signal processing module are mutually independent.
Description
Technical Field
The present disclosure relates to the field of neutron monitoring technology, and in particular, to a readout electronics system.
Background
Neutrons, like rays, have wavelets and are obtained by measuring the change in momentum after scattering with a sample through similar scattering techniques, and internal defects, cracks and stress distribution of the sample can be obtained by measuring the attenuation of penetrating samples through similar imaging techniques. Meanwhile, the neutron scattering technology has the remarkable characteristics and advantages of identifiable isotopes, strong penetrating power, high nondestructive performance and the like, so that the neutron scientific device at home and abroad can be rapidly developed.
The neutron scattering technology is started later in China, and is currently developed vigorously, and the established large neutron scattering device comprises a China spallation neutron source, a China Mian Yang research heap and a China advanced research heap.
CSNS (chinese spallation neutron source) is put into formal operation by national acceptance in 2018, 8 and 23 as a national major scientific and technological infrastructure, becoming the fourth pulsed spallation neutron source in the world. CSNS will provide a powerful research platform for basic research and new technology development in many areas.
The neutron beam incidence intensity of the neutron spectrometer is influenced by a plurality of factors such as accelerator power, proton targeting efficiency, neutron generation efficiency, neutron beam transmission efficiency and the like, and changes of the neutron beam incidence intensity can increase system errors, so that experimental measurement results are influenced.
The method is to place a neutron beam monitor at the outlet of the neutron conduit to measure the change of the incident neutron intensity along with time and provide normalized parameters for the spectrometer, so that the system error caused by the change of the neutron beam incident intensity can be effectively reduced.
The neutron beam monitor has the main function of measuring the change of the intensity of an incident neutron beam along with time, thereby providing a fitting basis for the measurement result of a spectrometer. In addition, the time of flight of neutrons is also an important item of information, directly corresponding to the de broglie wavelength, and the spectrometer needs to give the wavelength distribution of the neutron beam mass from the results of the beam monitor. There is also sometimes a need for a beam monitor to provide location measurement information of neutron hit cases, as required to monitor the beam spot shape. Along with the development of large neutron sources, the neutron flux is continuously improved, and higher requirements are put forward on the counting rate, resolution and the like of a neutron beam monitor, so that the requirements of the neutron beam monitor are more diversified in order to adapt to the requirements of different spectrometers, and the common beam monitor comprises GEM type detectors, low-pressure 3He type detectors, lithium glass type detectors and the like with various sizes. Based on the above situation, there is a need for a readout electronics system with high versatility to meet the testing requirements of various beam monitors.
Disclosure of Invention
The present disclosure provides a readout electronics system, which is implemented by the following technical scheme.
According to some embodiments of the present disclosure, a readout electronics system of the present disclosure includes:
the front-end signal processing device at least comprises a first signal processing module and a second signal processing module, wherein the first signal processing module is used for processing the electric signals output by the two-dimensional neutron detector so as to obtain two-dimensional digital signal output and single-channel analog signal output; the second signal processing module is used for processing the electric signal output by the one-dimensional neutron detector to obtain pulse signal output or energy signal output;
a data processor comprising a programmable logic array and a multi-interface circuit, the multi-interface circuit comprising at least a first interface circuit via which a signal output of the first signal processing module can be transferred to the programmable logic array and a second interface circuit via which a signal output of the second signal processing module can be transferred to the programmable logic array;
wherein the first signal processing module and the second signal processing module are independent from each other.
The first signal processing module includes a plurality of first signal processing units, each for processing an electrical signal output by one channel of the two-dimensional neutron detector, so that the first signal processing module can obtain a two-dimensional digital signal output and a single-channel analog signal output.
A readout electronics system according to at least one embodiment of the present disclosure, the first signal processing unit includes:
the amplifying and shaping circuit is used for amplifying and shaping the electric signal received from the two-dimensional neutron detector;
the signal buffer is used for dividing the signal output by the amplifying and shaping circuit into two paths of signals;
the signal discriminator is used for judging and selecting one of the two paths of signals output by the signal buffer and outputting a high-level signal/a low-level signal;
a signal latch that signal latches the high-level signal/low-level signal to output a digital signal;
the signal switch is used for controlling the on-off of the other signal in the two paths of signals output by the signal buffer, so that the signal is controllably transmitted to the analog signal output unit of the first signal processing module to output an analog signal.
The readout electronics system according to at least one embodiment of the present disclosure, the first signal processing module further comprises:
the channel multiplexing unit is used for converting signals output by the signal latches of the plurality of first signal processing units into one-path digital signals and outputting the digital signals.
A readout electronics system according to at least one embodiment of the present disclosure, the second signal processing module comprising:
the analog-to-digital conversion unit is used for performing analog-to-digital conversion on the electric signal output by the one-dimensional neutron detector to obtain the energy signal output;
a pulse detector unit for pulse counting the electric signal output by the one-dimensional neutron detector to obtain the pulse signal output;
wherein the analog-to-digital conversion unit and the pulse detector unit are controllably not operated simultaneously.
The readout electronics system according to at least one embodiment of the present disclosure, the analog-to-digital conversion unit and the pulse detector unit are controlled by the programmable logic array of the data processor to operate at different times.
The readout electronics system according to at least one embodiment of the present disclosure, the second signal processing module further comprises:
and the analog-to-digital conversion unit and the pulse detector unit are controlled by the FPGA module to work at different times.
The readout electronics system according to at least one embodiment of the present disclosure, the second signal processing module further comprises:
and the threshold control unit is used for outputting a direct current level to be used as a comparison threshold value for obtaining the pulse signal output so as to realize the output of the TTL pulse signal.
The readout electronics system according to at least one embodiment of the present disclosure, the first signal processing module and the second signal processing module are each configured as a circuit board.
The two-dimensional neutron detector comprises a GEM type detector and the one-dimensional neutron detector comprises a 3He type detector or a lithium glass type detector according to at least one embodiment of the present disclosure.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.
Fig. 1 is a schematic block diagram of the overall structure of a readout electronics system according to an embodiment of the present disclosure.
Fig. 2 is a block diagram of the first signal processing module of the readout electronics system according to one embodiment of the present disclosure.
Fig. 3 is a block diagram of the second signal processing module of the readout electronics system of one embodiment of the present disclosure.
Description of the reference numerals
100. Front-end signal processing device
101. First signal processing module
102. Second signal processing module
200. Data processor
201. Programmable logic array
202. Multi-interface circuit
1000. Readout electronics system
1011. First signal processing unit
1012. Analog signal output unit
1013. Channel multiplexing unit
1021. Analog-to-digital conversion unit
1022 pulse detector unit
1023FPGA module
1024. Threshold control unit
2021. First interface circuit
2022. A second interface circuit.
Detailed Description
The present disclosure is described in further detail below with reference to the drawings and the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant content and not limiting of the present disclosure. It should be further noted that, for convenience of description, only a portion relevant to the present disclosure is shown in the drawings.
In addition, embodiments of the present disclosure and features of the embodiments may be combined with each other without conflict. The technical aspects of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Unless otherwise indicated, the exemplary implementations/embodiments shown are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Thus, unless otherwise indicated, features of the various implementations/embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concepts of the present disclosure.
The use of cross-hatching and/or shading in the drawings is typically used to clarify the boundaries between adjacent components. As such, the presence or absence of cross-hatching or shading does not convey or represent any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated components, and/or any other characteristic, attribute, property, etc. of a component, unless indicated. In addition, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While the exemplary embodiments may be variously implemented, the specific process sequences may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described. Moreover, like reference numerals designate like parts.
When an element is referred to as being "on" or "over", "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. For this reason, the term "connected" may refer to physical connections, electrical connections, and the like, with or without intermediate components.
For descriptive purposes, the present disclosure may use spatially relative terms such as "under … …," under … …, "" under … …, "" lower, "" above … …, "" upper, "" above … …, "" higher "and" side (e.g., in "sidewall") to describe one component's relationship to another (other) component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "below" … … can encompass both an orientation of "above" and "below". Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising," and variations thereof, are used in the present specification, the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof is described, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not as degree terms, and as such, are used to explain the inherent deviations of measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.
Fig. 1 is a schematic block diagram of the overall structure of a readout electronics system according to an embodiment of the present disclosure.
Referring to fig. 1, in some embodiments of the present disclosure, a readout electronics system 1000 of the present disclosure includes: the front-end signal processing device 100, the front-end signal processing device 100 at least comprises a first signal processing module 101 and a second signal processing module 102, and the first signal processing module 101 is used for processing an electrical signal (such as a charge signal) output by the two-dimensional neutron detector so as to obtain a two-dimensional digital signal output and a single-channel analog signal output; the second signal processing module 102 is configured to process the electrical signal output by the one-dimensional neutron detector to obtain a pulse signal output or an energy signal output; and a data processor 200, the data processor 200 comprising a programmable logic array 201 (FPGA) and a multi-interface circuit 202, the multi-interface circuit 202 comprising at least a first interface circuit 2021 and a second interface circuit 2022, the signal output of the first signal processing module 101 being capable of being transferred to the programmable logic array 201 via the first interface circuit 2021, the signal output of the second signal processing module 102 being capable of being transferred to the programmable logic array 201 via the second interface circuit 2022.
Wherein the first signal processing module 101 and the second signal processing module 102 are independent from each other.
The readout electronics system 1000 of the present disclosure mainly includes a front-end signal processing device 100 and a data processor 200, and a general-purpose readout electronics system is constructed by configuring a plurality of signal processing modules in the front-end signal processing device 100, and a plurality of interface circuits are configured in the data processor 200 to receive signals of the respective signal processing modules, so that transmission and processing of various detector signals are realized.
Wherein, the front-end signal processing device 100 realizes functions such as the digitization of the detector signal; the data processor 200 realizes the functions of selecting, processing, packing, transmitting and the like of data.
The data processor of the present disclosure may employ a K7-325T low power programmable logic array as a master chip.
The front-end signal processing device 100 can flexibly switch according to different types of detectors, the switching mode comprises hard switching, a signal processing module is determined according to the types of the detectors, and interaction with the data processor 200 is realized through a hardware interface circuit.
It should be noted that, under the teaching of the technical solution of the present disclosure, a person skilled in the art may adjust the number/type of the signal processing modules, which all fall within the protection scope of the present disclosure.
In some embodiments of the present disclosure, as shown in fig. 1, the data processor 200 is also configured with dynamic memory,
the data processor 200 of the present disclosure implements a multi-interface circuit, and can access different signal processing modules of the front-end signal processing device 100 according to actual requirements, and meanwhile, designs a circuit system with an FPGA as a core, and implements data processing and data caching through the FPGA, and can implement interaction with an upper computer by adopting a SITCP protocol.
The multi-interface circuit of the data processor 200 can realize signal access of LVDS, LVPECL, TTL and other different level standards, and is convenient for the access of a front-end signal processing device.
Fig. 2 is a block diagram of the first signal processing module 101 of the readout electronics system 1000 of one embodiment of the present disclosure.
In some embodiments of the present disclosure, the first signal processing module 101 of the present disclosure includes a plurality of first signal processing units 1011 (only one first signal processing unit 1011 is shown in fig. 2), each first signal processing unit 1011 for processing an electrical signal output by one channel of the two-dimensional neutron detector, so that the first signal processing module 101 can obtain a two-dimensional digital signal output and a single-channel analog signal output.
As shown in fig. 2, in some embodiments of the present disclosure, the first signal processing unit 1011 of the present disclosure includes: the amplifying and shaping circuit is used for amplifying and shaping the electric signal received from the two-dimensional neutron detector; the signal buffer divides the signal output by the amplifying and shaping circuit into two paths of signals; the signal discriminator is used for judging and selecting one of the two paths of signals output by the signal buffer and outputting a high-level signal/low-level signal; a signal latch that performs signal latching on a high level signal/a low level signal to output a digital signal; and a signal switch, which is used for controlling the on-off of the other signal of the two signals output by the signal buffer, so that the signal is controllably transmitted to the analog signal output unit 1012 of the first signal processing module 101 to output an analog signal.
The digital signal output and optionally single-channel analog signal output are realized through the circuit structure design.
In some embodiments of the present disclosure, the first signal processing module 101 of the present disclosure further includes: and the channel multiplexing unit 1013, the channel multiplexing unit 1013 is configured to convert the signals output by the signal latches of the plurality of first signal processing units 1011 into one digital signal and output the digital signal.
The first signal processing module 101 of the present disclosure may be implemented based on a commercial ASIC module.
In some embodiments of the present disclosure, the front-end signal processing apparatus 100 is switched to the first signal processing module 101 when a two-dimensional neutron detector is used.
The output signals of the two-dimensional neutron detector can be connected to a plurality of first signal processing units 1011, the signals are divided into two paths through a signal buffer after being amplified and shaped, one path of the signals are sent to an analog signal output unit, the other path of the signals are sent to a signal discriminator for discrimination, if the signals exceed a threshold value, high levels are output, otherwise, low levels are output, the level values are subjected to signal latching, and the signal latching clock frequency can be 10MHz; the single ASIC module comprises 64 signal processing units (namely a first signal processing unit 1011), so that detection of 64 paths of signals of the two-dimensional neutron detector can be realized, 2 ASIC modules can be connected, signal measurement of 128 channels of the two-dimensional neutron detector can be realized, and the corresponding X, Y direction channels of the two-dimensional neutron detector can be connected according to requirements, so that two-dimensional signal reading can be realized.
Referring to fig. 2, after the charge signal output by the two-dimensional neutron detector is processed by the amplifying and shaping circuit, the charge signal is sent to the signal discriminator (comparator) for discrimination through the signal buffer, in order to improve channel multiplexing, the signal output by the signal discriminator is latched by using the signal latch, and the conversion of 64 paths of digital signals into 16 paths of digital signals can be realized based on the channel multiplexing unit for outputting. In use, a different number of first signal processing modules 101 may be connected to the data processor 200 by cables to enable readout of different area two-dimensional neutron detectors.
The channel multiplexing unit in fig. 2 may employ a 4-channel multiplexer, the readout clock may be 40MHz, and signals latched and output by adjacent 4-channel signals are converted into 1-channel digital signals by the channel multiplexer, so that the digital signals output by each first signal processing module 101 are 16-channel.
When a commercial ASIC module is used as the first signal processing module of the present disclosure, the first signal processing module may further configure the I2C interface unit, decoder, test signal generator, control unit, bias generator, chip address generator, and the like.
Those skilled in the art may adjust the structure of the first signal processing module 101, etc. in the light of the technical solution of the present disclosure, which all fall within the protection scope of the present disclosure.
Fig. 3 is a block diagram of the second signal processing module 102 of the readout electronics system 1000 of one embodiment of the present disclosure.
Referring to fig. 3, in some embodiments of the present disclosure, the second signal processing module 102 of the readout electronics system 1000 of the present disclosure includes: the analog-to-digital conversion unit 1021 is used for performing analog-to-digital conversion on the electric signal output by the one-dimensional neutron detector so as to obtain energy signal output; and a pulse detector unit 1022, the pulse detector unit 1022 being configured to perform pulse counting on the electrical signal output by the one-dimensional neutron detector to obtain a pulse signal output; wherein the analog-to-digital conversion unit 1021 and the pulse detector unit 1022 are controllably not operated simultaneously.
In some embodiments of the present disclosure, the analog-to-digital conversion unit 1021 and the pulse detector unit 1022 of the second signal processing module 102 of the readout electronics system 1000 of the present disclosure are controlled to operate at different times by the programmable logic array 201 of the data processor 200.
In other embodiments of the present disclosure, referring to fig. 3, the second signal processing module 102 of the present disclosure further includes: the FPGA block 1023, the analog-to-digital conversion unit 1021, and the pulse detector unit 1022 are controlled by the FPGA block 1023 to not operate simultaneously.
Preferably, with continued reference to fig. 3, the second signal processing module 102 of the present disclosure further comprises: and a threshold control unit 1024, where the threshold control unit 1024 is configured to output a dc level as a comparison threshold for obtaining the output of the pulse signal, so as to output the TTL pulse signal.
The analog-to-digital conversion unit 1021 of the second signal processing module 102 of the present disclosure may implement the digitization of two paths of analog signals by using a parallel analog-to-digital converter (ADC) with a 14-bit sampling clock of 80M, and when measuring the energy spectrum of the detection signal of the one-dimensional neutron detector, the analog-to-digital conversion unit 1021 needs to be activated.
The threshold control unit 1024 of the second signal processing module 102 of the present disclosure may use a 14-bit digital-to-analog converter (DAC), and may be controlled by a host computer (not shown) to implement a dc level output with a dynamic range of 0-3.3V. The front end of the one-dimensional neutron detector receives the level value as a threshold value of the comparator, and can output TTL pulse signals.
The pulse detector unit 1022 of the second signal processing module 102 of the present disclosure is enabled when performing pulse count measurement, and can receive a control command of an upper computer according to requirements, and perform setting of a detection time range.
The second signal processing module 102 of the present disclosure may further include a communication unit, a time information unit, and other circuit modules, which are all commonly used modules, and will not be described again.
When using a one-dimensional neutron detector, the readout electronics system of the present disclosure may switch to the second signal processing module 102, enabling one-dimensional signal processing.
When the energy spectrum measurement is required, the signal is connected to the analog-digital conversion unit 1021, and when the energy spectrum measurement is not required, the signal is connected to the pulse detector unit 1022, so that the counting and timing functions are realized.
The analog-to-digital conversion unit 1021 of the present disclosure can implement a flexible driving amplification circuit design, so that the detector analog input signal can be a differential signal or a single-ended signal, and the dynamic range of measurement is not affected.
The pulse detector unit 1022 of the present disclosure is designed as a controllably pulse detector, and the detection time range can be flexibly set according to the need.
The second signal processing module can be configured with an FPGA module to independently form a small system to work, and can also be connected to a data processor to realize unified data processing.
Preferably, the first signal processing module 101 and the second signal processing module 102 described above of the present disclosure are each configured as one circuit board.
The two-dimensional neutron detector described above in this disclosure includes, but is not limited to, a GEM-type detector, and a one-dimensional neutron detector includes, but is not limited to, a 3 He-type detector or a lithium glass-type detector.
It should be noted that fig. 1 to 3 of the present disclosure are only for explaining the circuit configuration of the readout electronics system of the present disclosure, and should not be construed as limiting the circuit configuration of the readout electronics system of the present disclosure.
In the description of the present specification, reference to the terms "one embodiment/manner," "some embodiments/manner," "example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/manner or example is included in at least one embodiment/manner or example of the present disclosure. In this specification, the schematic representations of the above terms are not necessarily for the same embodiment/manner or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/modes or examples described in this specification and the features of the various embodiments/modes or examples can be combined and combined by persons skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise.
It will be appreciated by those skilled in the art that the above-described embodiments are merely for clarity of illustration of the disclosure, and are not intended to limit the scope of the disclosure. Other variations or modifications will be apparent to persons skilled in the art from the foregoing disclosure, and such variations or modifications are intended to be within the scope of the present disclosure.
Claims (10)
1. A readout electronics system, comprising:
the front-end signal processing device at least comprises a first signal processing module and a second signal processing module, wherein the first signal processing module is used for processing the electric signals output by the two-dimensional neutron detector so as to obtain two-dimensional digital signal output and single-channel analog signal output; the second signal processing module is used for processing the electric signal output by the one-dimensional neutron detector to obtain pulse signal output or energy signal output; and
a data processor comprising a programmable logic array and a multi-interface circuit, the multi-interface circuit comprising at least a first interface circuit via which a signal output of the first signal processing module can be transferred to the programmable logic array and a second interface circuit via which a signal output of the second signal processing module can be transferred to the programmable logic array;
wherein the first signal processing module and the second signal processing module are independent from each other.
2. The readout electronics system according to claim 1, wherein the first signal processing module comprises a plurality of first signal processing units, each for processing an electrical signal output by one channel of the two-dimensional neutron detector, such that the first signal processing module is capable of obtaining a two-dimensional digital signal output and a single channel analog signal output.
3. The readout electronics system according to claim 2, wherein the first signal processing unit comprises:
the amplifying and shaping circuit is used for amplifying and shaping the electric signal received from the two-dimensional neutron detector;
the signal buffer is used for dividing the signal output by the amplifying and shaping circuit into two paths of signals;
the signal discriminator is used for judging and selecting one of the two paths of signals output by the signal buffer and outputting a high-level signal/a low-level signal;
a signal latch that signal latches the high-level signal/low-level signal to output a digital signal; and
the signal switch is used for controlling the on-off of the other signal in the two paths of signals output by the signal buffer, so that the signal is controllably transmitted to the analog signal output unit of the first signal processing module to output an analog signal.
4. The readout electronics system according to claim 3, wherein the first signal processing module further comprises:
the channel multiplexing unit is used for converting signals output by the signal latches of the plurality of first signal processing units into one-path digital signals and outputting the digital signals.
5. The readout electronics system according to any one of claims 1 to 4, wherein the second signal processing module comprises:
the analog-to-digital conversion unit is used for performing analog-to-digital conversion on the electric signal output by the one-dimensional neutron detector to obtain the energy signal output; and
a pulse detector unit for pulse counting the electric signal output by the one-dimensional neutron detector to obtain the pulse signal output;
wherein the analog-to-digital conversion unit and the pulse detector unit are controllably not operated simultaneously.
6. The readout electronics system according to claim 5, wherein the analog-to-digital conversion unit and the pulse detector unit are controlled by the programmable logic array of the data processor to operate at different times.
7. The readout electronics system according to claim 5, wherein the second signal processing module further comprises:
and the analog-to-digital conversion unit and the pulse detector unit are controlled by the FPGA module to work at different times.
8. The readout electronics system according to claim 5, wherein the second signal processing module further comprises:
and the threshold control unit is used for outputting a direct current level to be used as a comparison threshold value for obtaining the pulse signal output so as to realize the output of the TTL pulse signal.
9. The readout electronics system according to claim 1, wherein the first signal processing module and the second signal processing module are each configured as a circuit board.
10. The readout electronics system of claim 1, wherein the two-dimensional neutron detector comprises a GEM-type detector and the one-dimensional neutron detector comprises a 3 He-type detector or a lithium glass-type detector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321084053.7U CN219657884U (en) | 2023-05-08 | 2023-05-08 | Readout electronics system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321084053.7U CN219657884U (en) | 2023-05-08 | 2023-05-08 | Readout electronics system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219657884U true CN219657884U (en) | 2023-09-08 |
Family
ID=87863030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321084053.7U Active CN219657884U (en) | 2023-05-08 | 2023-05-08 | Readout electronics system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219657884U (en) |
-
2023
- 2023-05-08 CN CN202321084053.7U patent/CN219657884U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Back et al. | The PHOBOS detector at RHIC | |
| Pouthas et al. | The electronics of the INDRA 4π detection array | |
| Frohlich et al. | A general purpose trigger and readout board for HADES and FAIR-experiments | |
| CN103430533A (en) | Single photon counting detector system having improved counter architecture | |
| US20070279037A1 (en) | Spectrometry Diagnostic Electronic Circuit and Associated Counting System | |
| Lupberger et al. | Implementation of the VMM ASIC in the Scalable Readout System | |
| CN219657884U (en) | Readout electronics system | |
| Albrecht et al. | The Outer Tracker detector of the HERA-B experiment. Part II: Front-end electronics | |
| Boiano et al. | A 16-channel programmable antialiasing amplifier | |
| Satoh | Development of a New Exclusive Function for a 2012 Model 6Li Time Analyzer Neutron Detector System | |
| Ackermann et al. | The ICECUBE prototype string in AMANDA | |
| Li et al. | Performance of pad front-end board for small-strip thin gap chamber with cosmic ray muons | |
| Kang et al. | A 128-channel high precision time measurement module | |
| CN115291272A (en) | Miniaturized satellite-borne high-energy particle detection device and method based on silicon detector module | |
| Wintenberg et al. | Monolithic circuits for the WA98 lead class calorimeter | |
| CN214586023U (en) | Gamma dose monitoring devices based on long-range wireless communication | |
| Campagne et al. | PMm2: R&D on triggerless acquisition for next generation neutrino experiments | |
| CN109781841B (en) | Main/auxiliary channel ultrasonic detection system and electronic equipment | |
| Tambave et al. | Qualification of the ALICE SAMPA ASIC with a high-speed continuous DAQ system | |
| Andeen | Development of the ATLAS liquid argon calorimeter readout electronics for the HL-LHC | |
| Wang et al. | Picosecond Timing Electronics for a DIRC-Like Detector at the Super Tau-Charm Facility | |
| Yin et al. | Development of front-end waveform digitizer for filter-fluorescer x-ray diagnostic in Shenguang laser facility | |
| Satoh | Development of a 2012 model for the 6Li time analyzer detector system | |
| CN216083121U (en) | Oblique incidence neutron scintillator detector readout electronics system | |
| Greiner et al. | Sensor development and readout prototyping for the STAR Pixel detector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |