CN219514061U - Low-power-consumption solid-state relay system - Google Patents
Low-power-consumption solid-state relay system Download PDFInfo
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- CN219514061U CN219514061U CN202123395010.4U CN202123395010U CN219514061U CN 219514061 U CN219514061 U CN 219514061U CN 202123395010 U CN202123395010 U CN 202123395010U CN 219514061 U CN219514061 U CN 219514061U
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Abstract
The utility model relates to a low-power-consumption solid-state relay system which comprises a power supply circuit, a control circuit, a power supply chip and a peripheral circuit thereof, a holding switching chip and a peripheral circuit thereof, a driving chip and a peripheral circuit thereof, a relay assembly, an equipment power input assembly and an equipment power output assembly. Compared with the prior art, the utility model has the advantages of low loss, good heat dissipation, quick response time, long service life, small driving power consumption and high safety grade.
Description
Technical Field
The present utility model relates to relay systems, and more particularly to a low power solid state relay system suitable for use in vehicle electrical systems.
Background
The relay is a common electronic control device, and can control a load with larger current by smaller current, so that the relay can play a role in safety protection in a vehicle electrical system. And as the functions of the vehicle-mounted electric and electronic devices are continuously enriched, the relay is increasingly used as a vehicle-mounted network isolation device.
Compared with the requirements of the vehicle electrical system on components, the traditional mechanical relay such as a contact relay has the defects of larger driving power consumption, short service life, slow response time, low safety level and the like, and in order to keep the standby state of the relay in the sleep state, a special chip or an MCU processor is needed for control. The permanent electrification of the chip or MCU means that the whole system cannot achieve very low sleep power consumption.
Fig. 1 shows an exemplary combination of a mechanical relay and an external control chip IC 1. The relay is an electromagnetic relay, namely, the relay is turned on and off by generating and stopping an electromagnetic field. The IC1 as an external control chip is required to be permanently charged, and the power consumption level of the IC1 makes the whole system impossible to achieve very low sleep power consumption.
Fig. 2A shows a packaged appearance of an exemplary mechanical relay, and the circuit diagram of fig. 2B corresponds to the wiring diagram on the external package of fig. 2A. Such relays may be used in vehicle electrical systems, for example, as in-vehicle network isolation devices. However, for the reasons set forth above, it is desirable to have a new type of relay to further reduce the sleep power consumption of the relay system.
Disclosure of Invention
The utility model aims to overcome the defects of the prior art and provide the low-power-consumption solid-state relay.
The Solid State Relay (SSR) according to the utility model uses the MOSFET device as an isolation device, and achieves the purpose of turning on and off the circuit without contact and spark by utilizing the switching characteristic of the MOSFET device. The logic circuit part of the solid state relay adopts a general digital logic chip (trigger) to keep the state of the MOSFET, so that the overall power consumption of the relay can be reduced to within 100 uA.
The aim of the utility model can be achieved by the following technical scheme:
the utility model provides a low-power consumption type solid-state relay, includes power supply circuit, control circuit, power supply chip and peripheral circuit thereof, keeps switching chip and peripheral circuit thereof, driver chip and peripheral circuit thereof, relay assembly, equipment power input subassembly and equipment power output subassembly, power supply chip and peripheral circuit's input port be connected with power supply circuit, power supply chip and peripheral circuit's output port be connected with keeping switching chip and peripheral circuit's power input port, keep switching chip and peripheral circuit's signal input port be connected with control circuit, keep switching chip and peripheral circuit's output port be connected with driver chip and peripheral circuit's input port, driver chip and peripheral circuit's output port be connected with relay assembly's input port, relay assembly's power input port be connected with equipment power input subassembly, relay assembly's power output port be connected with equipment power output subassembly.
Preferably, the driving chip and the peripheral circuit thereof are provided with a first driving output port and a second driving output port.
Preferably, the relay assembly comprises a first relay subassembly and a second relay subassembly, wherein the first relay subassembly and the second relay subassembly comprise a plurality of MOSFET devices, the gates of the MOSFET devices are respectively connected with the first driving output port through resistors, the sources of the MOSFET devices are connected with the second driving output port, the drains of the MOSFET devices of the first relay subassembly are connected with the equipment power input assembly, and the drains of the MOSFET devices of the second relay subassembly are connected with the equipment power output assembly
Preferably, the first relay subassembly and the second relay subassembly each comprise five MOSFET devices.
Preferably, the power supply chip model is MPQ2013AGQ-5-AECQ1-Z.
Preferably, the pin IN of the power supply chip is connected with the power supply circuit, and the pin OUT of the power supply chip is connected with the power supply input port of the hold switch chip and the peripheral circuit thereof.
Preferably, the type of the hold switch chip is SN74LVC1G80 qdctq 1.
Preferably, the control circuit comprises a first control circuit and a second control circuit, the pin CLK of the hold switch chip is connected with the first control circuit, the pin D of the hold switch chip is connected with the second control circuit, and the pin of the hold switch chipIs connected with the input port of the driving chip and the peripheral circuit thereof.
Preferably, the driving chip model is AUIR3242S.
Preferably, the pin IN of the driving chip is connected to the output port of the holding switching chip and its peripheral circuit, and the pin GATE and the pin SOURCE of the driving chip are connected to the relay assembly, respectively.
Preferably, the peripheral circuit of the power supply chip comprises a capacitor C45, C11, C33, C18, a resistor R28 and a voltage stabilizing diode D25, wherein the C45 and the C11 are arranged IN parallel, one side of the C45 and the C11 is grounded, the other side of the C45 and the C11 is connected with a pin IN of the power supply chip, the C33 and the C18 are arranged IN parallel, one side of the C33 and the C18 is connected with a pin OUT, the other side of the C33 and the C18 is connected with GND and EPAD pins of the power supply chip and grounded, the pin IN of the power supply chip is connected with the power supply circuit through the R28, the RN pin of the power supply chip is connected with the pin IN, the pin OUT of the power supply chip is connected with a VCC pin of the holding switch chip, the pin OUT of the power supply chip is grounded through the voltage stabilizing diode D25,
preferably, the peripheral circuit of the hold switch chip includes capacitors C32, C90, resistors R12, R13, R6, R74, R14, the pin CLK of the hold switch chip is connected to the first control circuit through R12, the first control circuit is the pin CLK of the central controller, the pin D of the hold switch chip is connected to the second control circuit through R13, the second control circuit is the pin D of the central controller, the pins CLK are connected in series through R5 and R6, C90 is connected in parallel with R6, the VCC pin of the hold switch chip is grounded through C32, the pin of the hold switch chipIs connected with a pin IN of the driving chip through R14 and is grounded through R74.
Preferably, the peripheral circuit of the driving chip comprises resistors R29, R1, R120, R22, R94, an inductor L1, capacitors C123, C43, C82, and diodes D3, D10, D8, and the pin IN of the driving chip is connected with the pin of the holding switch chip via R29 and the diodesAnd the pins In of the driving chip are connected In series with R1 and R120 and then grounded, the pin RS of the driving chip is connected In series with R22 and then grounded, and the pin SW of the driving chip is connected with the drain electrode of the first relay subassembly through L1 and D3. The pin OUT of the driving chip is connected with the pin VCC through C123, the pin VCC of the driving chip is grounded through C43 and connected with L1 and D3, the pin GATE of the driving chip is connected with the GATE pole of the relay through R94, the pin SOURCE of the driving chip is connected with the SOURCE pole of the relay and grounded through C82 and connected with the GATE pole through D10 and D8.
Preferably, the first relay subassembly includes relays Q1, Q3, Q5, Q7, Q9, the second relay subassembly includes relays Q2, Q4, Q6, Q8, Q10, Q1, Q3, Q5, Q7, Q9, GATEs of the relays are connected to pins GATE of the driving chip through R31, R32, R33, R34, R35, and Q2, Q4, Q6, Q8, Q10 are connected to pins GATE of the driving chip through R23, R24, R25, R27, R30, respectively.
Preferably, the device power input assembly comprises a device input circuit and a diode D2 and a capacitor C113, which are arranged in parallel, wherein one side of the capacitor D2 and the capacitor C113 is connected with the device input circuit, the other side is grounded, and the device input circuit is connected with the drain electrode of the relay in the first relay subassembly.
Preferably, the device power output assembly comprises a device output line and a diode D1 and a capacitor C114 arranged in parallel, wherein one side of the capacitor C114 is connected with the device output line, the other side is grounded, and the device output line is connected with the drain electrode of the relay of the second relay subassembly.
Compared with the prior art, the utility model has the following advantages:
(1) The utility model realizes the effective control of the relay assembly by using the power supply chip and the peripheral circuit thereof, the holding switching chip and the peripheral circuit thereof, and the driving chip and the peripheral circuit thereof, and can keep the state of the MOSFET in the sleeping state, thereby having low power consumption;
(2) The solid-state relay MOSFET is used for replacing the traditional mechanical relay, so that the solid-state relay MOSFET has the advantages of low loss, good heat dissipation, quick response time, long service life, small driving power consumption and high safety level;
(3) The relay subassembly sets up two sets of relay subassemblies, and every relay subassembly includes five relays, and the reliability is strong, improves control effect.
Drawings
Fig. 1 is an exemplary combination of a mechanical relay and an external control chip IC 1.
Fig. 2A is a packaged appearance of an exemplary mechanical relay, and fig. 2B is a wiring diagram corresponding to the printed matter on the external package of fig. 2A.
FIG. 3 is a functional schematic of the solid state relay system of the present utility model;
FIG. 4 is a schematic diagram of the overall structure of the solid state relay system of the present utility model;
FIG. 5 is an exemplary circuit diagram of a power supply chip and its peripheral circuitry, a hold switch chip and its peripheral circuitry in a solid state relay system of the present utility model;
fig. 6 is an exemplary circuit diagram of a drive chip and its peripheral circuitry in a solid state relay system of the present utility model connected to a relay assembly;
FIG. 7 is a partial schematic diagram of a drive chip and its peripheral circuitry in the solid state relay system of the present utility model;
fig. 8 is an exemplary circuit diagram of a relay assembly, a device power input assembly, and a device power output assembly in a solid state relay system of the present utility model.
The power supply circuit comprises a power supply circuit, a control circuit, a power supply chip, a holding switching chip, a driving chip, a relay assembly, a device power input assembly, a device power output assembly, a digital logic chip, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) driving circuit and a 360A and 360B, MOSFET switch array, wherein the power supply circuit, the control circuit, the power supply chip, the holding switching chip, the driving chip, the relay assembly and the device power input assembly are arranged in sequence, and the digital logic chip is arranged in sequence.
Detailed Description
The utility model will now be described in detail with reference to the drawings and specific examples. Note that the following description of the embodiments is merely an example, and the present utility model is not intended to be limited to the applications and uses thereof, and is not intended to be limited to the following embodiments.
Examples
Fig. 3 shows a functional schematic of a low-power solid state relay system. Such a low power solid state relay system includes a digital logic chip 320, a MOSFET drive circuit 350, and an array of MOSFET switches (two groupings, 360A and 360B are shown).
Fig. 4 shows a schematic overall structure of the solid state relay system having the functional architecture of fig. 3. As shown in fig. 4, the low-power solid-state relay system may include a power supply circuit 1, a control circuit 2, a power supply chip 3 and its peripheral circuits, a holding switch chip 4 and its peripheral circuits, a driving chip 5 and its peripheral circuits, a relay assembly 6, a device power input assembly 7 and a device power output assembly 8, the input ports of the power supply chip 3 and its peripheral circuits are connected to the power supply circuit 1, the output ports of the power supply chip 3 and its peripheral circuits are connected to the power input ports of the holding switch chip 4 (optional) and its peripheral circuits, the signal input ports of the holding switch chip 4 and its peripheral circuits are connected to the control circuit 2, the output ports of the holding switch chip 4 and its peripheral circuits are connected to the input ports of the driving chip 5 and its peripheral circuits, the output ports of the driving chip 5 and its peripheral circuits are connected to the input ports of the relay assembly 6, the power input ports of the relay assembly 6 are connected to the device power input assembly 7, and the power output ports of the relay assembly 6 are connected to the device power output assembly 8. The driving chip 5 and the peripheral circuit thereof are provided with a first driving output port and a second driving output port, the relay assembly 6 comprises a first relay subassembly and a second relay subassembly, the first relay subassembly and the second relay subassembly comprise a plurality of MOSFET devices, the gates of the MOSFET devices are respectively connected with the first driving output port through resistors, the sources of the MOSFET devices are connected with the second driving output port, the drains of the MOSFET devices of the first relay subassembly are connected with the equipment power input assembly 7, and the drains of the MOSFET devices of the second relay subassembly are connected with the equipment power output assembly 8.
In this embodiment, the first relay subassembly and the second relay subassembly each include five MOSFET devices. The pin IN of the driving chip 5 is connected to the output port of the holding switching chip 4 and its peripheral circuits, and the pin GATE and the pin SOURCE of the driving chip 5 are connected to the relay assembly 6, respectively.
The driving chip 4 in fig. 4 may correspond to the MOSFET driving circuit 350 of fig. 3, the relay assembly 6 in fig. 4 may correspond to the MOSFET switch arrays 360A and 360B of fig. 3, and the control circuit 2 and the hold switch chip 4 in fig. 4 may correspond to the digital logic chip 320 of fig. 3. For the selection of the chip, in an exemplary implementation manner of this embodiment, the selected chip types are as follows: the model of the power supply chip 3 is MPQ2013AGQ-5-AECQ1-Z; keeping the model number of the switching chip 4 as SN74LVC1G80QDCKTQ1; the model number of the driving chip 5 is AUIR3242S. These chips are all commercially available chips.
In this embodiment, more specific circuits for implementing the relay system are shown in fig. 5 to 8, where U10, U7, and U8 are the power supply chip 3, the hold switch chip 4, and the driving chip 5, respectively.
Specifically, the corresponding chip and peripheral circuit structure may have the following connection relationship:
the pin IN of the power supply chip 3 is connected to the power supply circuit 1, and the pin OUT of the power supply chip 3 is connected to the power supply input ports of the hold switch chip 4 and its peripheral circuits.
The control circuit 2 comprises a first control circuit 2 and a second control circuit 2, wherein a pin CLK of the switching chip 4 is kept connected with the first control circuit 2, a pin D of the switching chip 4 is kept connected with the second control circuit 2, and a pin of the switching chip 4 is keptIs connected with the input port of the driving chip 5 and the peripheral circuit thereof.
The peripheral circuit of the power supply chip 3 comprises capacitors C45, C11, C33, C18, a resistor R28 and a voltage stabilizing diode D25, wherein the capacitors C45 and C11 are arranged IN parallel, one sides of the capacitors C45 and C11 are grounded, the other sides of the capacitors C45 and C11 are connected with a pin IN of the power supply chip 3, the capacitors C33 and C18 are arranged IN parallel, one sides of the capacitors C33 and C18 are connected with a pin OUT, the other sides of the capacitors C33 and C18 are connected with GND and EPAD pins of the power supply chip 3 and grounded, the pin IN of the power supply chip 3 is connected with the power supply circuit 1 through the resistor R28, the RN pin of the power supply chip 3 is connected with the pin IN, the pin OUT of the power supply chip 3 is connected with a VCC pin which keeps switching the chip 4, and the pin OUT of the power supply chip 3 is grounded through the voltage stabilizing diode D25.
The peripheral circuit of the hold switch chip 4 comprises capacitors C32, C90, resistors R12, R13, R6, R74 and R14, a pin CLK of the hold switch chip 4 is connected with the first control circuit 2 through the resistor R12, the first control circuit 2 is a pin CLK of the central controller, a pin D of the hold switch chip 4 is connected with the second control circuit 2 through the resistor R13, the second control circuit 2 is a pin D of the central controller, the pins CLK are connected in series through the resistor R5 and the resistor R6, the resistor C90 is arranged in parallel with the resistor R6, a VCC pin of the hold switch chip 4 is grounded through the resistor C32, and a pin of the hold switch chip 4 is connectedIs connected to pin IN of the driver chip 5 via R14 and is grounded via R74.
The peripheral circuits of the driving chip 5 comprise resistors R29, R1, R120, R22, R94, an inductor L1, capacitors C123, C43, C82, diodes D3, D10 and D8, and the pin IN of the driving chip 5 is connected with the pin of the holding switch chip 4 through the R29 and the diodesThe pins In of the driving chip 5 are connected In series with R1 and R120 and then grounded, the pins RS of the driving chip 5 are connected In series with R22 and then grounded, and the pins SW of the driving chip 5 are connected with the drain electrode of the first relay subassembly through L1 and D3. The pin OUT of the driving chip 5 is connected with the pin VCC through C123, the pin VCC of the driving chip 5 is grounded through C43 and connected with L1 and D3, the pin GATE of the driving chip 5 is connected with the GATE pole of the relay through R94, the pin SOURCE of the driving chip 5 is connected with the SOURCE pole of the relay and grounded through C82 and connected with the GATE pole through D10 and D8.
The first relay subassembly comprises relays Q1, Q3, Q5, Q7 and Q9, the second relay subassembly comprises GATEs of relays Q2, Q4, Q6, Q8, Q10, Q1, Q3, Q5, Q7 and Q9, the GATEs are respectively connected with a pin GATE of the driving chip 5 through R31, R32, R33, R34 and R35, and the GATEs of the relays Q2, Q4, Q6, Q8 and Q10 are respectively connected with a pin GATE of the driving chip 5 through R23, R24, R25, R27 and R30.
The device power input assembly 7 comprises a device input circuit, a diode D2 and a capacitor C113, wherein the diode D2 and the capacitor C113 are arranged in parallel, one side of the capacitor D2 and the capacitor C113 is connected with the device input circuit, the other side of the capacitor D2 and the capacitor C113 is grounded, and the device input circuit is connected with the drain electrode of the relay in the first relay subassembly. The device power output assembly 8 comprises a device output line, a diode D1 and a capacitor C114 which are arranged in parallel, wherein one side of the capacitor C114 is connected with the device output line, the other side of the capacitor C114 is grounded, and the device output line is connected with the drain electrode of the relay of the second relay subassembly.
The above embodiments are merely examples, and do not limit the scope of the present utility model. These embodiments may be implemented in various other ways, and various omissions, substitutions, and changes may be made without departing from the scope of the technical idea of the present utility model.
Claims (10)
1. The low-power consumption type solid-state relay system is characterized by comprising a power supply circuit (1), a control circuit (2), a power supply chip (3) and a peripheral circuit thereof, a holding switching chip (4) and a peripheral circuit thereof, a driving chip (5) and a peripheral circuit thereof, a relay assembly (6), a device power supply input assembly (7) and a device power supply output assembly (8), wherein the input ports of the power supply chip (3) and the peripheral circuit thereof are connected with the power supply circuit (1), the output ports of the power supply chip (3) and the peripheral circuit thereof are connected with the power supply input ports of the holding switching chip (4) and the peripheral circuit thereof, the signal input ports of the holding switching chip (4) and the peripheral circuit thereof are connected with the control circuit (2), the output ports of the holding switching chip (4) and the peripheral circuit thereof are connected with the input ports of the driving chip (5) and the peripheral circuit thereof, the power supply input ports of the relay assembly (6) are connected with the device power supply input assembly (7), the output ports of the relay assembly (6) are connected with the device power supply assembly (8),
the relay assembly comprises a plurality of MOSFET devices as isolation elements, and the control circuit (2) generates control signals for driving the MOSFET devices through a driving chip (5).
2. A low power solid state relay system according to claim 1, wherein the driver chip (5) and its peripheral circuitry are provided with a first driver output port and a second driver output port.
3. A low power solid state relay system according to claim 2, wherein the relay assembly (6) comprises a first relay subassembly and a second relay subassembly, the first relay subassembly and the second relay subassembly each comprise a plurality of MOSFET devices, the gate of each MOSFET device is connected to the first driving output port through a resistor, the source of each MOSFET device is connected to the second driving output port, the drain of each MOSFET device of the first relay subassembly is connected to the device power input assembly (7), and the drain of each MOSFET of the second relay subassembly is connected to the device power output assembly (8).
4. A low power solid state relay system according to claim 3 wherein said first and second relay subassemblies each comprise five MOSFET devices.
5. The low-power solid state relay system according to claim 1, wherein the power supply chip (3) is of the type MPQ2013AGQ-5-AECQ1-Z.
6. The low-power solid state relay system according to claim 1, wherein the pin IN of the power supply chip (3) is connected to the power supply circuit (1), and the pin OUT of the power supply chip (3) is connected to the power input port of the hold switch chip (4) and its peripheral circuits.
7. The low-power solid state relay system according to claim 1, wherein the type of the hold switch chip (4) is SN74LVC1G80 qdcttq 1.
8. The low-power-consumption solid-state relay system according to claim 1, wherein the control circuit (2) comprises a first control circuit (2) and a second control circuit (2), the pin CLK of the hold switch chip (4) is connected with the first control circuit (2), the pin D of the hold switch chip (4) is connected with the second control circuit (2), and the pin Q of the hold switch chip (4) is connected with the input port of the driving chip (5) and its peripheral circuit.
9. The low-power solid state relay system according to claim 1, wherein the driving chip (5) is AUIR3242S.
10. The low-power solid state relay system according to claim 1, wherein the pin IN of the driving chip (5) is connected to the output port of the holding switch chip (4) and its peripheral circuit, and the pin GATE and the pin SOURCE of the driving chip (5) are connected to the relay assembly (6), respectively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2020232737192 | 2020-12-30 | ||
| CN202023273719 | 2020-12-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219514061U true CN219514061U (en) | 2023-08-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123395010.4U Active CN219514061U (en) | 2020-12-30 | 2021-12-30 | Low-power-consumption solid-state relay system |
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|---|---|
| CN (1) | CN219514061U (en) |
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2021
- 2021-12-30 CN CN202123395010.4U patent/CN219514061U/en active Active
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