CN2195114Y

CN2195114Y - Computer IC disc card

Info

Publication number: CN2195114Y
Application number: CN 94205320
Authority: CN
Inventors: 王宇鹏
Original assignee: WANG YUPENG CN); WANG YUPENG CN
Current assignee: WANG YUPENG CN); WANG YUPENG CN
Priority date: 1994-03-26
Filing date: 1994-03-26
Publication date: 1995-04-19
Anticipated expiration: 2004-03-26

Abstract

The utility model relates to a computer IC disk card which is designed to replace floppy disks and hard disks. The utility model is composed of a random access memories RAM, a plurality of ROMs and a read/write circuit which is composed of a low address buffer, a bidirectional data transceiver, a high address latch and an address decoding chip selecting circuit. Various system software, application software, Chinese character libraries, etc. are solidified into the ROMs, the utility model is inserted into a PC bus slot of a computer, and thus the utility model can be read and written; if the generative software of an A disk, a C disk and a virtual disk is solidified into the ROMs of the utility model, the generative software can replace the system A disk and the system C disk and are configured into the virtual disk. The utility model has the advantages of high reliability, long service life, high speed, good security, antivirus, etc.

Description

Computer IC disc card

The utility model relates to a kind of machine element, relates to a kind of IC dish card or rather.

Soft, the hard disc complex structure of computing machine, comprise mechanical part and supporting electric components such as magnetic disc, W head, driver, controller, motor, be subjected to the environmental health condition effect, the read/write operation of disk and life-span all can be affected, thereby reduced reliability, and during disk access, mechanical action is time-consuming, and has influenced operating rate.

The purpose of this utility model is a kind of Computer I C dish of design card, replace soft, hard disc in the general computing machine, promptly adopt RAM-Disk and ROM-Disk technology, use ROM, RAM to realize replacing by mixing, comprise substituting for computer system tape A or C dish, also can be configured to D, E, the F of system ... etc. non-firm offer.

Computer I C of the present utility model dish card is combined into memory by semiconductor memory chip ROM, the RAM of a constant volume, is equipped with read/write circuit again and constitutes.The ROM district of IC dish card is solidificated in various system softwares, application software and Chinese character base etc. among the ROM in advance for selecting plug-in type, and IC dish card inserts in the computer PC bus slot, can be to its any read-write.

If what insert is to solidify to see accompanying drawing 3 with utility software Write A() ROM, then the A dish of start back system is just replaced by this IC dish card, if solidified system software among the ROM, computing machine can also guide the system that enter by IC dish card so;

If what insert is to solidify to see accompanying drawing 3 with utility software Write C() ROM, then the C dish of start back system is just replaced by this IC dish card, if solidified system software among the ROM, computing machine can also guide the system that enter by IC dish card so;

If what insert is to solidify to see accompanying drawing 3 with utility software WriteV() ROM, and in the Config.sys of system root directory, increase delegation's configuration order, device: ［ d: ］［ path ］ icvdisk.sys, after the start, IC dish card has just become the virtual disk of system.This virtual disk is compared with general internal memory RAMVdisk.sys, have not account for the advantage that Installed System Memory, shutdown back file can not be lost, and this non-firm offer also can be with internal memory RAM, Vdisk.sys simultaneously and exist in the system.

The insertion of this IC dish card does not influence that former machine floppy drive is moving, the normal use of hard-drive.

Computer I C dish card of the present utility model, by RAM, the ROM sheet and the ROM of some parallel connections, RAM reads, write circuit is formed, it is characterized in that: described read/write circuit comprises finishes the low order address impact damper of PC bus low order address SA0-SA12 to dish card low order address LA0-LA12 data buffering, finish the bi-directional data receipts/device that PC data bus SD0-SD7 and IC dish card data bus LD0-LD7 bi-directional data transmits, high address data latches that the dish card high address data LA13-LA20 of device output latchs is received/sent out to bi-directional data and to PC bus high address SA14-SA19, dish card high address LA18-LA20, dish card low order address LA2, LA4-LA9, the PC control bus blocks address decoding and generates RAM, each ROM and bidirectional data transceiver, the two-stage decoding chip select circuit of high address data latches chip selection signal.

When PC CPU reads IC dish card, at first translate dish card address and open the decoding chip select circuit by two-stage decoding chip select circuit; Then CPU sends into IC dish card with the high address information of chip select by the PC data bus with the OUT instruction, and the high address data latches will be latched in chip output through the chip select high address information that bidirectional data transceiver transmits; Two-stage decoding chip select circuit produces the chip selection signal of each ROM sheet, RAM sheet to the Senior Three bit address decoding of high address data latches under the control of PC control bus; CPU provides low order address information with the MOV instruction again, promptly chooses certain byte of certain storaging chip; Last CPU reads in the content of this byte in the CPU through bidirectional data transceiver and PC bus under read signal control.

When writing IC dish card, the operating process of chip select, word selection joint is the same, just final step, and CPU will write data and send in the selected storaging chip byte through the bidirectional data transceiver of PC bus and IC dish card.

Describe technology of the present utility model in detail below in conjunction with the embodiment accompanying drawing.

Accompanying drawing 1 is Computer I C dish card logic modular construction schematic diagram.

Accompanying drawing 2 is the enforcement circuit diagram of structure shown in Figure 1.

Accompanying drawing 3 is the generation software main flow block diagram of A dish, C dish and the non-firm offer of Computer I C dish card.

Accompanying drawing 4 is the non-firm offer driver main flow block diagram of Computer I C dish card.

Referring to Fig. 1,300 is the PC bus; 201 is the low order address impact damper, and SA0-SA12 low order address data are cushioned output, and LA0-LA12 dish card low order address is represented with 301.

ROM district 101-104 and a RAM district 105 of four selective insertions have been designed on the present embodiment IC dish card.The design of this IC dish card has the power down protection circuit 400 of RAM.

202 is bidirectional data transceiver, and the bidirectional transmit-receive data are two-way transmission PC data and dish card data under chip selection signal DIR control.Another task of bidirectional data transceiver is the chip select high address data that CPU sends to be sent into to latch in the dish card high address latch 203 be output as LA13-LA20(303), wherein Senior Three bit address LA18-LA20 send the first-level address code translator 204 of two-stage decoding chip select circuit.

Also have high address SA14-SA19 and the dish from the PC bus of sending into first-level address code translator 204 simultaneously block low order address LA4-LA9, LA2.Address, second-level decoding and chip select circuit 205 generate chip selection signal ROM1CS, ROM2CS, ROM3CS, MASKCS, DIR and the IOCS of each ROM sheet, RAM sheet, bidirectional data transceiver 202, high address latch 203.Decoding and sheet select the control of controlled process system bus 304 each signal.

Referring to Fig. 2, JPB connects PC bus and IC dish card among the figure.Low order address impact damper in integrated impact damper U1, the U2 pie graph 1.In integrated chip U5, U6, the U7 difference corresponding diagram 1 101,102,103, capacity 512K, jumper switch JP6-JP8 selects its memory capacity 512K or 256K for the user.104 is corresponding among integrated U8 and Fig. 1, and memory capacity is 256K, and 105 is corresponding among integrated U9 and Fig. 1, and memory capacity is 32K.Sheffer stroke gate U11A, U11C, U11D and peripheral cell E, D2 etc. constitute the power down protection circuit 400 of RAM.

Integrated bi-directional data collector U3 is corresponding with the logical block 202 of Fig. 1.The high address latch of integrated data latch U4 and peripheral resistance pie graph 1 thereof.First-level address code translator 204 in phase inverter U14D, U14E, U14B, U14C, U14F, U14A and Sheffer stroke gate U12, the U13 pie graph 1, whether the access that jumper switch JP1-JP5 is used to select U14A-U14C, U14E, U14F promptly realizes adjusting IC dish card address.Address, second-level decoding and chip select circuit 205 in the programmable logic array GAL chip U10 pie graph 1.Insert U10 have PC control signal AEN, MEMW, MEMR, decoded signal MEMCS, and dish card address LA0, LA1, LA3, LA8, LA18 and the LA19 of IOW, first-level address decoding scheme.Chip selection signal DIR, IOCS, ROM1CS-ROM3CS, MASKCS and RAMCS send the sheet choosing end of respective chip respectively.MEMR signal through low order address impact damper U2 output send corresponding integrated U10, U5-U9.

Referring to Fig. 3, the A that blocks for this IC dish coils, C coils and the generation software of non-firm offer, and each frame meaning is described below among the figure:

A-carries out initialization by the form of A dish or C dish to RAM and ROM dish;

B-analyzes the catalogue file of generation dish;

Does c-have sub-directory?

D-analyzes the sub-directory file;

E-converts the catalogue file of analyzing the binary file of corresponding bibliographic structure to, outputs in the output1 file;

F-converts corresponding file to binary format and outputs to output1;

Has the g-file generated?

h－output1≤512？

The I-respective file converts binary format to and outputs to output2;

Has the J-file generated?

K－output2≤512？

L-closes output2, outputs to output3 after the respective file conversion;

Has the M-file generated?

N－output3≤512？

O-closes output3, outputs to output4 after the respective file conversion;

Has the P-file generated?

Q－output≤256？

The R-demonstration that makes mistakes.

Referring to Fig. 4, be the non-firm offer driver main flow chart of this IC disc, each frame meaning is described below:

A-organization definition, variable-definition;

The definition of b-device head;

The c-strategic process;

The d-interrupt procedure;

The BPB parameter is got in e-reading and writing, medium inspection, writes and the verification command handling procedure;

F-initialization command handling procedure.

The major advantage of this IC dish card is:

1) because of simple structural design, greatly improved reliability and the life of product of product;

2) directly select to control memory cell with cpu address bus, data/address bus and control signal and carry out the data storage because of the read-write of dish card, to the access of dish card namely with respect to the interior memory cell of access main frame, exempted the mechanical action of disk, so access speed is fast;

3) ROM of certain capacity in the dish card such as the memory capacity of embodiment 1.8M, can solidify various systems soft wares, application software, also can be application software newly developed encrypted instruction and interrupt call are provided, and can effectively protect development;

4) the ROM memory cell in the IC dish card can not be rewritten, and therefore any virus can not be revised the program among the ROM and strengthen the anti-virus ability.

The range of application of this IC dish card can comprise solidification software, non-disk workstation, unmanned special machine, reinforcement type microcomputer, special microprocessor system, PC Bus and various strong motion, high dust work environment.

This IC coils card embodiment equities information query system software solidification newly developed is coiled in the card at this IC, has obtained good effect through trying out.

Claims

1, a kind of Computer I C dish card, by RAM, the ROM sheet and the ROM of some parallel connections, RAM reads, write circuit is formed, it is characterized in that: described read/write circuit comprises finishes the low order address impact damper of PC bus low order address SA0-SA12 to dish card low order address LA0-LA12 data buffering, finish the bi-directional data receipts/device that PC data bus SD0-SD7 and IC dish card data bus LD0-LD7 bi-directional data transmits, high address data latches that the dish card high address data LA13-LA20 of device output latchs is received/sent out to bi-directional data and to PC bus high address SA14-SA19, dish card high address LA18-LA20, dish card low order address LA2, LA4-LA9, the PC control bus blocks address decoding and generates RAM, each ROM and bidirectional data transceiver, the two-stage decoding chip select circuit of high address data latches chip selection signal.

2, Computer I C dish card according to claim 1, it is characterized in that: the first-level address code translator of described two-stage address decoding chip select circuit comprises phase inverter U14A-U14F and Sheffer stroke gate U12, U13, U14D, U14E, U14B, U14C, the input end of U14F meets control signal AEN respectively, PC address SA15, SA16, SA17, SA14, its output connects each input end of U13 respectively, the remaining input terminal of U13 meets PC address SA18 respectively, SA19, the input of phase inverter U14A meets dish card address LA4, output connects the input end of U12, and the remaining input terminal of U12 meets dish card address LA9 respectively, LA5-LA7, LA2;

The address, second-level of described two-stage address decoding chip select circuit decoding chip select circuit is a programmable logic array GAL chip, each input end of chip connect respectively control signal AEN, MEMW, MEMR, the output signal of IOW, dish card address LA0, LA1, LA3, LA8, LA18-LA20 and described Sheffer stroke gate U12, U13.

3, Computer I C dish card according to claim 2 is characterized in that: be connected to the jumper switch of selecting phase inverter to insert between the input of described phase inverter U14E, U14B, U14C, U14F and U14A, output terminal.