CN219351689U - Frequency multiplier circuit based on current multiplexing - Google Patents

Abstract

The utility model relates to a current multiplexing-based frequency multiplier circuit, wherein a differential input signal (Vin) is respectively input into grids of a first MOS tube (M1) and a second MOS tube (M2), source stages of the first MOS tube (M1) and the second MOS tube (M2) are grounded, a drain electrode of a third MOS tube (M3) is an output end (Vout), a drain electrode of the third MOS tube (M3) is connected into an RLC network, and drain electrodes of the first MOS tube (M1) and the second MOS tube (M2) are connected to the source stage of the third MOS tube (M3) after passing through a transformer network (T1). The frequency multiplier circuit based on current multiplexing has the advantages of high reliability and high conversion gain.

Description

Frequency multiplier circuit based on current multiplexing

Technical Field

The utility model relates to a frequency multiplier circuit, in particular to a frequency multiplier circuit adopting a current multiplexing mode, and belongs to the technical field of integrated circuits.

Background

The frequency multiplier is a core module in a signal generating circuit (shown in fig. 1-1), and has the function of generating signal output of frequency multiplication of input signal numbers, and can be applied to high-frequency local oscillation signal generation and some simple modulation communication systems. In the wireless receiver of fig. 1-1, the VCO operates at a frequency f _OSC The frequency of the frequency-doubled output signal after passing through the frequency multiplier of N times amplification is N f _OSC As shown in fig. 1-2, the center frequency of the received signal in the corresponding receiver is f _RF If f _RF =N*f _OSC At this time, the analog baseband amplifier BB AMP outputs an analog baseband signal which is subjected to down-conversion demodulation, so that it can be seen that the frequency multiplier functions to convert the local oscillation signal f _OSC And frequency multiplication is carried out to achieve the required central frequency for down-conversion, and N is the frequency multiplication multiple of the frequency multiplier.

FIG. 2 shows a conventional frequency multiplier circuit, in which MOS transistors (M1 and M2) form an input differential pair, V _in The differential signal is input, the working frequency is f1, drain ends (Drain) of MOS tubes (M1 and M2) are output and connected together to an RLC load network formed by a resistor R1, an inductor L1 and a capacitor C1, RLC resonance is carried out at N harmonics (N x f 1), thus the required N times of frequency is selected through the RLC frequency selection network, and the output signal is Vout, wherein N is the multiple of the frequency multiplier.

The problem with this construction is that:

(1) the Conversion Gain of the input to the output is usually determined by the bias voltage of the MOS transistors (M1 and M2), even frequency multiplication is usually biased in a subthreshold region to be even harmonic maximization, and at the moment, the Conversion Gain (CG: conversion Gain) is lower and is determined by the following formula:

CG=gmn*Zout

the conversion gain CG (Conversion Gain) is the conversion gain from the input f1 to the output n f1, gmn is the n-1 derivative of the transconductance of M1 and M2, zout is the parallel impedance value of the load network formed by R1, L1 and C1 and the output impedance of M1 and M2 in parallel at the frequency point of n f 1; under the condition of fixed power consumption, if the conversion gain CG (Conversion Gain) is larger than 0dB, the structure is more ideal, and the conversion gain CG (Conversion Gain) is not too high under the condition that the structure is limited by the output impedance of the MOS transistors (M1 and M2) and the subthreshold bias;

(2) in general, the RLC network impedance value formed by R1, L1, and C1 is higher, firstly, in order to increase the conversion gain CG (Conversion Gain) as much as possible, secondly, in a frequency multiplication link, the signal amplitude is relatively strong, the swing of the Vout signal is under the saturated output condition, the output signal generally uses the power supply voltage (Vdd) as direct current, the peak voltage Vpeak is the output signal of Vdd, under this condition, vds of M1 and M2 is easily caused to be too large (Vpeak reaches 2 x Vdd, even higher), which causes reliability problems, such as reliability problems common to MOS tubes such as HCI or TDDB;

therefore, another improved frequency multiplier scheme with a Cascode transistor is proposed as shown in fig. 3, wherein a MOS transistor (M1 and M2) is also an input differential pair, and a MOS transistor, namely a M3 transistor, is added, so that on one hand, the output impedance at Vout can be raised, and further, the output impedance is raised, meanwhile, due to the addition of a MOS transistor, the withstand voltage of the MOS transistors (M1 and M2) is relieved, and the MOS transistors (M1, M2 and M3) are pressed together, so that the reliability risk of the frequency multiplier structure of fig. 3 is better than that of the structure in fig. 2.

The frequency multiplier structure of fig. 3 still has the following problems:

(1) although the MOS transistor M3 is added to increase the output impedance, the overall conversion gain CG (Conversion Gain) is improved only to a limited extent;

(2) although the MOS tube M3 is added, in practical situations, the voltage swing born by the M3 tube is even larger than that of the MOS tubes (M1 and M2), which is equivalent to that of the MOS tubes (M1 and M2), the voltage withstand of the MOS tube M3 is transferred, and the MOS tube M3 still needs to pay attention to the reliability problem.

In view of the foregoing, there is a need for a frequency multiplier circuit that can solve the above-mentioned problems.

Disclosure of Invention

The utility model aims to overcome the defects and provide a frequency multiplier circuit based on current multiplexing, which has high reliability and high conversion gain.

The purpose of the utility model is realized in the following way:

a frequency multiplier circuit based on current multiplexing is characterized in that differential input signals are respectively input into grids of a first MOS tube and a second MOS tube, source stages of the first MOS tube and the second MOS tube are grounded, drain electrodes of the third MOS tube are output ends, drain electrodes of the third MOS tube are connected to an RLC network, and the first MOS tube and the second MOS tube are connected to the grid electrodes and the source stages of the third MOS tube after passing through a transformer network.

Preferably, the transformer network is composed of a primary inductor, an inductor II and an inductor III, the drains of the MOS tube I and the MOS tube II are divided into two paths after being coupled by the primary inductor, one path is coupled to the source of the MOS tube III after being coupled by the primary inductor II, and the other path is coupled to the grid of the MOS tube III after being coupled by the primary inductor III.

Preferably, the inductor II and the inductor III are formed by winding induction coils, and the coil group formed by the inductor II and the inductor III is mutually coupled with the inductor to form a transformer structure.

Compared with the prior art, the utility model has the beneficial effects that:

the utility model realizes the remarkable improvement of reliability and conversion gain under the condition of not increasing power consumption by adding the transformer network for matching and current multiplexing. Namely, the overall gain is improved through the first-stage frequency doubling circuit and the second-stage amplifying circuit; and through current multiplexing, the performance extrusion of the MOS tube by direct current voltage drop is avoided, and the overall reliability of the circuit system is ensured.

Drawings

Fig. 1-1 is a schematic diagram of a frequency multiplier for use in a wireless receiver.

Fig. 1-2 is a graph of the frequency spectrum of fig. 1-1.

Fig. 2 is a circuit diagram of a conventional frequency multiplier.

Fig. 3 shows a frequency multiplier based on a differential amplifying circuit.

Fig. 4 is a circuit diagram of a current multiplexing-based frequency multiplier circuit according to the present utility model.

Detailed Description

Referring to fig. 4, a differential input signal Vin is input to gates of a first MOS transistor M1 and a second MOS transistor M2 respectively, source stages of the first MOS transistor M1 and the second MOS transistor M2 are grounded, drains of the first MOS transistor M1 and the second MOS transistor M2 are divided into two paths through a primary inductor L0, one path is connected to a source stage of a third MOS transistor M3 through the second inductor L2, the other path is coupled to an ac ground serving as the third MOS transistor M3 through a capacitor C0, a gate of the third MOS transistor M3 is connected to a bias voltage VB through the third inductor L3, the other path is coupled to an ac ground through the second capacitor C2, a drain of the third MOS transistor M3 is connected to a signal output terminal Vout, and a drain of the third MOS transistor M3 is connected to a power supply through an RLC network.

The primary inductor L0, the second inductor L2 and the third inductor L3 form a transformer network T1, that is, the primary inductor L0, the second inductor L2 and the third inductor L3 are all formed by winding induction coils, the second inductor L2 and the third inductor L3 form a coil set equivalent to a coil set with a middle tap, the middle tap is connected with the capacitor C0, and the coil set formed by the second inductor L2 and the third inductor L3 and the primary inductor L0 are mutually coupled to form a transformer structure.

The following analysis is made with respect to the above-described circuit configuration of the present utility model:

from the alternating current, the MOS tube I M1, the MOS tube II M2 and the primary inductor L0 form a first-stage frequency doubling circuit; the second-stage amplifying circuit is formed by the second inductor L2, the third inductor L3, the third MOS transistor M3, the first resistor R1, the first inductor L1 and the first capacitor C1.

In the direct current, the first-stage frequency multiplier and the second-stage amplifier circuit share a power supply voltage, namely share a direct current path, and the direct current power consumption of the scheme is the same as that of the circuits in fig. 2 and 3 mentioned in the background art under the same bias and power supply voltage, namely, the current multiplexing structure is realized. Meanwhile, the power supply voltage value of the first stage is determined by the grid voltage VB of the MOS transistor III M3 and the grid voltages of the MOS transistor I M1 and the MOS transistor II M2.

The working principle of the utility model is as follows:

firstly, MOS tube I M1 and MOS tube II M2 are still used as n-order harmonic generation circuit, vin is fundamental frequency input signal, n-order harmonic current produced by MOS tube I M1 and MOS tube II M2 is input into transformer network T1 (transformer network T1 is formed from primary inductance L0, inductance II L2, inductance III L3 and mutual inductance therebetween), the above-mentioned signals are mutually coupled by transformer network T1 and output into source end and Gate end of MOS tube III M3, if the homonymous ends of inductance II L2 and inductance III L3 are just opposite, the circuit can form a gm multiplication unit, can greatly raise gain of M3, because MOS tube III M3 is not used as cascode tube at this moment, but is used as Common Gate (CG: common Gate) amplification circuit, at this moment the frequency multiplier circuit is actually changed into first stage frequency multiplier formed from MOS tube I M1, MOS tube II M2 and primary inductance L0, inductance II L3, MOS tube III M3, resistance I R1 and C1 form second stage amplification circuit,

the addition of a transformer network T1 as a matching and current multiplexing circuit in the circuit of the utility model, as compared to the circuits of fig. 2 and 3 mentioned in the background art, although consisting of three inductances, can generally be realized by three windings of a stack, only a fraction of the relative increase from an area point of view, but with a significant improvement in reliability and conversion gain.

Specifically, the method comprises the following steps:

for conversion gain, the inventive frequency multiplier circuit is constructed of two stages, the first stage conversion gain is close to the conventional frequency multiplier circuit of fig. 2, but the second stage is an amplifying circuit, so the overall conversion gain of the utility model is much better than the conventional circuits of fig. 2 and 3, i.e., the same output requires less input signal driving.

For reliability, the frequency multiplier circuit of the utility model avoids direct current voltage drop, eliminates the problem of reliability of the conventional frequency converter circuit in fig. 3, and the output amplitude is completely shared by two stages of circuits instead of completely pressing the voltage swing in one stage, thereby reducing the pressure and the requirement on a single device and ensuring the overall reliability of the circuit system.

In addition: it should be noted that the above embodiment is only one of the optimization schemes of this patent, and any modification or improvement made by those skilled in the art according to the above concepts is within the scope of this patent.

Claims (3)

1. The utility model provides a frequency multiplier circuit based on electric current multiplexing, differential input signal (Vin) is input MOS pipe one (M1) respectively and is managed the grid of two (M2) with MOS, and the source ground of MOS pipe one (M1) and MOS pipe two (M2), and the drain electrode of MOS pipe three (M3) is output (Vout), and the drain electrode of MOS pipe three (M3) inserts RLC network, its characterized in that: the drains of the MOS tube I (M1) and the MOS tube II (M2) are connected to the grid electrode and the source stage of the MOS tube III (M3) after passing through the transformer network (T1).

2. The current multiplexing based frequency multiplier circuit of claim 1, wherein: the transformer network (T1) is composed of a primary inductor (L0), an inductor II (L2) and an inductor III (L3), the drains of the MOS tube I (M1) and the MOS tube II (M2) are divided into two paths after being coupled through the primary inductor (L0), one path is coupled to the inductor II (L2) through the primary inductor (L0) and then connected with the source of the MOS tube III (M3), and the other path is coupled to the inductor III (L3) through the primary inductor (L0) and then connected with the grid of the MOS tube III (M3).

3. The current multiplexing based frequency multiplier circuit of claim 2, wherein: the primary inductor (L0), the inductor II (L2) and the inductor III (L3) are formed by winding induction coils, and a coil group formed by the inductor II (L2) and the inductor III (L3) is mutually coupled with the primary inductor (L0) to form a transformer structure.

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