CN219329260U - Packaging structure - Google Patents

Packaging structure Download PDF

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Publication number
CN219329260U
CN219329260U CN202223433523.4U CN202223433523U CN219329260U CN 219329260 U CN219329260 U CN 219329260U CN 202223433523 U CN202223433523 U CN 202223433523U CN 219329260 U CN219329260 U CN 219329260U
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pad
metal layer
layer
dielectric layer
package structure
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CN202223433523.4U
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Chinese (zh)
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谢孟伟
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

The utility model relates to a packaging structure, which comprises a circuit layer. The wiring layer includes a dielectric layer and a pad buried within the dielectric layer, and the pad is exposed by a top surface of the dielectric layer, the top surface of the pad being aligned with the top surface of the dielectric layer. The package structure further includes a metal layer disposed over an interface between the pad and the dielectric layer. According to the technical scheme, the metal layer is arranged above the interface between the dielectric layer and the bonding pad, so that the layering problem at the interface between the dielectric layer and the bonding pad can be avoided.

Description

Packaging structure
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a packaging structure.
Background
Referring to fig. 1A to 1D, the current chip post (chip post) process may include the following steps: referring to fig. 1A, a Fan-out (Fan-out) redistribution layer 20 is formed on a redistribution layer (RDL, redistribution Layer) carrier 10; referring to fig. 1B, electronic device 32 is attached to redistribution layer 20 and electronic device 32 is molded using molding compound 36, and carrier 40 is disposed over molding compound 36 and electronic device 32; referring to fig. 1C, the redistribution layer carrier 10 of fig. 1B is removed, exposing the dielectric layer 22 and the pads 24 of the redistribution layer 20; referring to fig. 1D, the structure shown in fig. 1C is inverted and solder balls 50 are formed on the exposed pads 24 of the redistribution layer 20.
In the above-mentioned current chip post-mounting process, after removing the redistribution layer carrier 10 of the connection pad 24 in fig. 1B, the bonding surface of the pad 24 for connecting the solder ball 50 and the surface of the dielectric layer 22 are nearly flush and do not cover each other (see fig. 1D), so the following two problems may be faced:
(1) As shown in fig. 1E, the surface of the dielectric layer 22 and the bonding surface of the pad 24 are flush, and there is a risk of delamination 55 at the interface between the dielectric layer 22 and the pad 24 due to thermal stress.
(2) As shown in fig. 1F, the bonding surface of the pad 24 is in a non-bowl shape, and during reflow after ball drop, the solder ball 50 may risk slipping, causing the solder ball 50 to be not connected to the pad 24, or may cause the solder ball 50 to bridge (ball bridge). The existing solder ball formation yield rate is estimated to be 80%, and the reliability risk is high.
As shown in fig. 2, although the delamination problem shown in fig. 1E can be solved by covering the interface between the dielectric layer 22 and the pad 24 of the redistribution layer 20 with another dielectric layer 62, and the risk of solder ball sliding can be solved by forming a bowl-shaped structure by exposing the pad 24 to the openings in the dielectric layer 22, the dielectric layer 62 will cover a portion of the pad 24, thereby affecting the electrical performance.
Disclosure of Invention
In view of the above-mentioned problems in the related art, the present utility model provides a packaging structure, which can at least solve the delamination problem at the interface between the bonding pad and the dielectric layer.
According to an embodiment of the present utility model, there is provided a package structure. The packaging structure comprises a circuit layer. The wiring layer includes a dielectric layer and a pad buried within the dielectric layer, and the pad is exposed by a top surface of the dielectric layer, the top surface of the pad being aligned with the top surface of the dielectric layer. The package structure further includes a metal layer disposed over an interface between the pad and the dielectric layer.
In some embodiments, the package structure further includes an electrical connector, the metal layer having an opening exposing the pad, the electrical connector being connected to the pad through the opening such that the electrical connector is located over the pad.
In some embodiments, the metal layer is a ring-shaped structure and exposes a portion of the upper surface of the pad.
In some embodiments, the package structure further includes an electrical connector contacting the metal layer and a portion of the upper surface of the pad.
In some embodiments, the package structure further includes a seed layer located between the interface and the metal layer.
In some embodiments, a portion of the lower surface of the metal layer contacts the top surface of the dielectric layer and another portion of the lower surface of the metal layer contacts the upper surface of the pad.
In some embodiments, the upper surface of the pad is a first upper surface, the pad further has a second upper surface lower than the first upper surface, and the metal layer extends from the first upper surface onto the second upper surface.
In some embodiments, the first upper surface surrounds the second upper surface, and the metal layer exposes a portion of the second upper surface of the pad.
In some embodiments, the package structure further includes an electrical connector contacting the metal layer and a portion of the second upper surface of the pad.
In some embodiments, the electrical connection is separated from the top surface of the dielectric layer by a metal layer.
According to the packaging structure, the metal layer is arranged above the interface between the dielectric layer and the bonding pad, so that the layering problem at the interface between the dielectric layer and the bonding pad can be avoided; the electrical connector can be limited on the metal layer and the bonding pad, so that the position deviation of the electrical connector relative to the bonding pad is reduced, and the sliding risk when the upper surface of the bonding pad is level with the top surface of the dielectric layer can be solved. In addition, compared with the existing method that the layering problem and the sliding risk can influence the electrical performance by covering part of the bonding pads with the dielectric layer, the packaging structure can avoid adverse effects on the electrical performance.
Drawings
The various aspects of the utility model are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A to 1D are schematic cross-sectional views of stages of forming a package structure in the prior art.
Fig. 1E and 1F are schematic structural diagrams of the risk of delamination and the risk of solder ball slipping, respectively, generated in the prior art.
Fig. 2 is a schematic cross-sectional view of another package structure in the prior art.
Fig. 3A is a schematic cross-sectional view of a package structure according to one embodiment of the present application.
Fig. 3B is a schematic top view of the metal layer shown in fig. 3A.
Fig. 4 is a schematic cross-sectional view of a package structure according to another embodiment of the present application.
Fig. 5 is a schematic cross-sectional view of a package structure according to another embodiment of the present application.
Fig. 6A-6E are cross-sectional schematic views of stages of forming a package structure according to embodiments of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the utility model. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
A package structure is provided according to an embodiment of the present application. Fig. 3A is a schematic cross-sectional view of a package structure 100 according to one embodiment of the present application. Referring to fig. 3A, the package structure 100 includes a wiring layer 120. In some embodiments, the wiring layer 120 is a redistribution layer. The wiring layer 120 may include a dielectric layer 121 and a pad 126 buried within the dielectric layer 121. The wiring layer 120 may further comprise further dielectric layers 122, 123, 124 located under the dielectric layer 121. The wiring layer 120 is shown in fig. 3A as comprising a total of four stacked dielectric layers 121, 122, 123, 124, but may comprise other numbers of dielectric layers. The dielectric layer 121 is the uppermost dielectric layer among the dielectric layers 121, 122, 123, 124 of the wiring layer 120.
An upper surface 126u of the pad 126 is exposed by the top surface 121t of the dielectric layer 121. The upper surface 126u of the pad 126 is aligned, i.e., coplanar, with the top surface 121t of the dielectric layer 121. There is an interface 125 between the pad 126 and the dielectric layer 121. The package structure 100 further includes a metal layer 130, the metal layer 130 being disposed over the interface 125 between the pad 126 and the dielectric layer 121. By disposing the metal layer 130 over the interface 125 between the dielectric layer 121 and the pad 126, delamination problems at the interface 125 between the dielectric layer 121 and the pad 126 may be avoided. Since delamination problems are avoided, all sides of the pad 126 may be in contact with the dielectric layer 121 to form the interface 125.
The metal layer 130 extends from the top surface 121t of the dielectric layer 121 across the interface 125 onto the upper surface 126u of the pad 126. Thus, a portion 130b1 of the lower surface 130b of the metal layer 130 contacts the top surface 121t of the dielectric layer 121, and another portion 130b2 of the lower surface 130b of the metal layer 130 contacts the upper surface 126u of the pad 126. The package structure 100 further includes electrical connectors 150 that connect the pads 126. Electrical connections 150 are located on pads 126 and metal layer 130. In some embodiments, the electrical connector 150 may be a solder ball or the like for electrical connection. The electrical connection 150 is not in contact with the dielectric layer 121, and the electrical connection 150 is separated from the top surface 121t of the dielectric layer 121 by the metal layer 130.
The metal layer 130 may be formed of any suitable metal material. A material that can form a eutectic with the electrical connection 150 can be used to form the metal layer 130. In some embodiments, the material of the metal layer 130 may be copper, i.e., the metal layer 130 is a copper layer. In other embodiments, the material of the metal layer 130 may include nickel and gold, and in such embodiments, the metal layer 130 includes a nickel layer formed by an electroless nickel gold (ENIG) process and a gold layer on the nickel layer. In some embodiments, the metal layer 130 and the pad 126 may be formed of the same material, e.g., the material of the metal layer 130 and the pad 126 may both be copper. In other embodiments, the metal layer 130 and the pad 126 may be formed of different materials.
Fig. 3B is a schematic top view of the metal layer 130 shown in fig. 3A. For simplicity, the top view shown in fig. 3B corresponds to the top view of metal layer 130 and pads 126 without electrical connections 150 (see fig. 3A) formed thereon. Referring to fig. 3B, the metal layer 130 has a ring structure. As shown in connection with fig. 3A and 3B, the metal layer 130 of the ring-shaped structure may have an opening 132 exposing the pad 126, the opening 132 exposing a portion of the upper surface 126u of the pad 126. The electrical connector 150 contacts the metal layer 130 and a portion of the upper surface 126u of the pad 126 exposed by the metal layer 130. The electrical connector 150 is connected to the pad 126 through the opening 132 defined by the metal layer 130 such that the electrical connector 150 is located over the pad 126.
According to embodiments of the present application, the metal layer 130 is configured to reduce positional offset of the electrical connection 150. Since the metal layer 130 protrudes from the upper surface 126u of the pad 126 and the top surface 121t of the dielectric layer 121, the metal layer 130 and the pad 126 may be configured in a bowl-shaped structure with a high edge and a low center. Because the metal layer 130 and the bonding pad 126 form a bowl-shaped structure with high edges and low centers, when the electric connector 150 is formed on the bonding pad 126, the electric connector 150 can be limited at the positions of the metal layer 130 and the bonding pad 126, so that the sliding risk when the upper surface 126u of the bonding pad 126 is level with the top surface 121t of the dielectric layer can be solved, the position offset of the electric connector 150 relative to the bonding pad 126 is reduced, the process yield is improved, the structural reliability is improved under the condition that the thickness of the circuit layer 120 is not increased, the solder ball formation yield can be higher than 99.9%, and the detection failure rate of the reliability can reach nearly 0%. In addition, compared to the method of fig. 2 in which the layering problem and the sliding risk are solved by covering the partial pad 24 with the dielectric layer 62, the embodiment of the present application can avoid the adverse effect on the electrical performance by providing the conductive metal layer 130 covering the partial pad 126.
In addition, a side of the wiring layer 120 opposite to the electrical connector 150 may be connected to the electronic device 110. The electronic device 110 may be, for example, a chip or the like. The electronic device 110 is encapsulated by a molding compound 115. The electronic device 110 is connected to pads 129 exposed by the lowermost dielectric layer 124 in the wiring layer 120.
Fig. 4 is a schematic cross-sectional view of a package structure 100' according to another embodiment of the present application. As shown with reference to fig. 4, a seed layer 127 may be provided between the interface 125 between the pad 126 and the dielectric layer 121 and the metal layer 130. The sides of seed layer 127 may be vertically aligned with the corresponding sides of metal layer 130.
Fig. 5 is a schematic cross-sectional view of a package structure 200 according to another embodiment of the present application. In the package structure 200 shown in fig. 5, the upper surface 126u of the pad 126 includes a first upper surface 126u1 and a second upper surface 126u2 lower than the first upper surface 126u1. The first upper surface 126u1 corresponds to an edge region of the pad 126, and the second upper surface 126u2 corresponds to a central region of the pad 126. The first upper surface 126u1 surrounds the second upper surface 126u2. The metal layer 230 covers the first upper surface 126u1 of the pad 126. The metal layer 230 exposes a portion of the second upper surface 126u2 of the pad 126. The electrical connector 150 contacts the metal layer 230 and a portion of the second upper surface 126u2 of the pad 126 exposed by the metal layer 230.
The metal layer 230 extends from the first upper surface 126u1 onto the second upper surface 126u2. A groove may be formed on the pad 126 by removing a portion of the pad 126, thereby defining a first upper surface 126u1 and a second upper surface 126u2 of the pad 126. The metal layer 230 extends from the top surface 121t of the dielectric layer 121 across the interface 125 between the dielectric layer 121 and the pad 126, extends past the first upper surface 126u1 of the pad 126, and then extends down onto the second upper surface 126u2 of the pad 126. The electrical connection 150 is not in contact with the dielectric layer 121, and the electrical connection 150 is separated from the top surface 121t of the dielectric layer 121 by the metal layer 230.
The shape of the metal layer 230 shown in fig. 5 can increase the contact area between the metal layer 230 and the pad 126, so that the dielectric layer 121 and the pad 126 can be buckled together, further delamination between the dielectric layer 121 and the pad 126 is avoided, and in addition, the shape of the metal layer 230 shown in fig. 5 can also increase the contact area between the metal layer 230 and the electrical connector 150, so as to ensure the fixing effect of the electrical connector 150.
Other aspects of the package structure 200 shown in fig. 5 may be similar to those described above with reference to fig. 3A and 4, and will not be described again here.
Fig. 6A-6E are cross-sectional schematic views of stages of forming a package structure according to embodiments of the present application. Referring first to fig. 6A, a wiring layer carrier 610 and a wiring layer 120 formed on the wiring layer carrier 610 are provided. In this embodiment, the wiring layer 120 may include four dielectric layers 121, 122, 123, 124 formed in sequence. At this stage, the pad 126 is buried in the dielectric layer 121 in contact with the wiring layer carrier 610, and the pad 126 is exposed by the dielectric layer 121 and in contact with the wiring layer carrier 610. A pad 129 is provided in the dielectric layer 124 on the opposite side of the wiring layer 120 from the wiring layer carrier 610, the pad 129 being exposed by the dielectric layer 124.
Referring to fig. 6B, the electronic device 110 is connected to the pad 129 of the wiring layer 120, for example, using an SMT (Surface Mounted Technology, surface mount technology) process. The electronic device 110 is molded using a molding compound 115. The molding compound 115 may be flush with the surface of the electronic device 110 by a polishing process. Then, a carrier 620 is attached over the molding compound 115 and the electronic device 110.
Referring to fig. 6C, the wiring layer carrier 610 of fig. 6B is removed, exposing the dielectric layer 121 and the pads 126 of the wiring layer 120.
Referring to fig. 6D, the structure shown in fig. 6C is inverted. At this time, the top surface 121t of the dielectric layer 121 and the upper surface 126u of the pad 126 are flush. An interface 125 is provided between the dielectric layer 121 and the pad 126. A metal layer 130 is then formed that is disposed over the interface 125. The metal layer 130 may be similar to the metal layer 130 described above with reference to fig. 3A-3B. In some embodiments, as described with reference to fig. 4, first seed layer 127 may be formed prior to forming metal layer 130, and then metal layer 130 may be formed on seed layer 127.
Referring to fig. 6E, solder balls 150 are formed on the metal layer 130 and on the pads 126. Because the metal layer 130 is disposed above the interface 125, the electrical connector 150 can be limited on the pad 126 when the solder ball 150 is formed, so that the positional offset of the electrical connector 150 relative to the pad 126 is reduced, and the sliding risk when the upper surface 126u of the pad 126 is level with the top surface 121t of the dielectric layer 121 can be solved. In some embodiments, after the solder balls 150 are formed, the carrier 620 may be removed, resulting in the package structure 100 shown in fig. 3A.
The upper surface 160u of the pad 126 formed in fig. 6E is a flat surface. In another embodiment, after the stage shown in fig. 6C, a portion of the pad 126 may be removed to form a recess at the upper surface of the pad 126, and then a metal layer 230 extending into the recess may be formed to obtain the package structure 200 shown in fig. 5.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that the utility model may readily be utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the utility model, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the utility model.

Claims (10)

1. A package structure, comprising:
a wiring layer, the wiring layer comprising:
a dielectric layer;
a pad buried within the dielectric layer and exposed by a top surface of the dielectric layer, an upper surface of the pad being aligned with the top surface of the dielectric layer;
and a metal layer disposed over an interface between the pad and the dielectric layer.
2. The package structure of claim 1, further comprising:
an electrical connector, the metal layer having an opening exposing the pad, the electrical connector being connected to the pad through the opening such that the electrical connector is located over the pad.
3. The package structure of claim 1, wherein,
the metal layer is of a ring-shaped structure and exposes a portion of the upper surface of the bonding pad.
4. The package structure of claim 3, further comprising:
an electrical connection contacting the metal layer and the portion of the upper surface of the pad.
5. The package structure of claim 1, further comprising:
a seed layer located between the interface and the metal layer.
6. The package structure of claim 1, wherein,
a portion of a lower surface of the metal layer contacts the top surface of the dielectric layer and another portion of the lower surface of the metal layer contacts the upper surface of the pad.
7. The package structure of claim 1, wherein,
the upper surface of the pad is a first upper surface, the pad further has a second upper surface lower than the first upper surface, and the metal layer extends from the first upper surface onto the second upper surface.
8. The package structure of claim 7, wherein,
the first upper surface surrounds the second upper surface, and the metal layer exposes a portion of the second upper surface of the pad.
9. The package structure of claim 8, further comprising:
an electrical connection contacting the metal layer and the portion of the second upper surface of the pad.
10. The package structure of claim 2, wherein,
the electrical connection is separated from the top surface of the dielectric layer by the metal layer.
CN202223433523.4U 2022-12-21 2022-12-21 Packaging structure Active CN219329260U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202223433523.4U CN219329260U (en) 2022-12-21 2022-12-21 Packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202223433523.4U CN219329260U (en) 2022-12-21 2022-12-21 Packaging structure

Publications (1)

Publication Number Publication Date
CN219329260U true CN219329260U (en) 2023-07-11

Family

ID=87061383

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202223433523.4U Active CN219329260U (en) 2022-12-21 2022-12-21 Packaging structure

Country Status (1)

Country Link
CN (1) CN219329260U (en)

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