CN219303660U - Optoelectronic package, chip and electronic equipment - Google Patents

Abstract

The embodiment of the utility model discloses an optoelectronic package, a chip and electronic equipment, and relates to the technical field of semiconductor packaging. The utility model aims to solve the problems of signal transmission delay and larger energy consumption between chips in optoelectronic packaging. The optoelectronic package comprises a package substrate and a first interconnection substrate, wherein a first groove is formed in the package substrate, and the first interconnection substrate is arranged in the first groove; the first chip, the second chip and the third chip are positioned on the packaging substrate and are respectively and electrically connected with the packaging substrate; wherein a portion of the first chip and a portion of the second chip are electrically connected to the first interconnection substrate, respectively, the second chip includes one of an electrical chip and an optical chip, and the third chip includes the other of the electrical chip and the optical chip. The method is suitable for application scenes in which the delay and the energy consumption of signal transmission between chips in optoelectronic packaging are required to be reduced.

Description

Optoelectronic package, chip and electronic equipment

Technical Field

The utility model relates to the technical field of semiconductor packaging. And more particularly to an optoelectronic package, chip and electronic device.

Background

At present, the energy consumption of a data center is larger and larger, the energy consumption of electronic components is required to be reduced, however, the integrated circuit units in the electronic components on the market are generally electrically connected with the computing units through conversion circuits, for example, the integrated circuit units are electrically connected with the computing units through connectors, signals in the integrated circuit units can be sent to the computing units through the conversion circuits, so that the delay of signal transmission between the integrated circuit units and the computing units is longer, and the energy consumption of the electronic components is larger.

Disclosure of Invention

In view of the above, the embodiments of the present utility model provide an optoelectronic package, a chip and an electronic device, which can reduce the delay and the energy consumption of the signal transmission between the first integrated circuit unit and the computing unit.

In order to achieve the above purpose, the embodiment of the present utility model adopts the following technical scheme:

in a first aspect, an embodiment of the present utility model provides an optoelectronic package comprising: the packaging structure comprises a packaging substrate and a first interconnection substrate, wherein a first groove is formed in the packaging substrate, and the first interconnection substrate is arranged in the first groove; the first chip, the second chip and the third chip are positioned on the packaging substrate and are respectively and electrically connected with the packaging substrate; wherein a portion of the first chip and a portion of the second chip are electrically connected to the first interconnection substrate, respectively, the second chip includes one of an electrical chip and an optical chip, and the third chip includes the other of the electrical chip and the optical chip.

According to a specific implementation manner of the embodiment of the utility model, the method further comprises a second interconnection substrate; the packaging substrate is also provided with a second groove which is arranged at intervals with the first groove, and the second interconnection substrate is embedded in the second groove; wherein a portion of the third chip is electrically connected to the second interconnect substrate.

According to a specific implementation manner of the embodiment of the present utility model, the first chip, the second chip and the third chip are arranged at intervals.

According to a specific implementation manner of the embodiment of the present utility model, any two of the first chip, the second chip and the third chip are integrated into one single chip. According to a specific implementation manner of the embodiment of the present utility model, the package substrate includes: the first groove is formed in the first interconnection layer, and the first interconnection layer comprises first metal connecting wire layers and first dielectric layers which are alternately stacked; the first interconnect substrate includes: and the second interconnection layer comprises second metal wire layers and second dielectric layers which are alternately stacked, wherein the second dielectric layers comprise organic materials, and the arrangement density of the second metal wire layers is greater than that of the first metal wire layers.

According to a specific implementation of an embodiment of the present utility model, the organic material comprises polyimide.

According to a specific implementation manner of the embodiment of the present utility model, the package substrate further includes: the first connecting bumps are positioned on the upper surface of the first interconnection layer, and the first chip, the second chip and the third chip are electrically connected with the packaging substrate through the first connecting bumps; the first interconnect substrate further includes: and the second connecting bumps are positioned on the upper surface of the second interconnection layer, and the part of the first chip and the part of the second chip are electrically connected with the first interconnection substrate through the second connecting bumps.

According to a specific implementation manner of the embodiment of the present utility model, at least one of the following is satisfied between the second connection bump and the first connection bump: the width of the second connecting convex block is smaller than that of the first connecting convex block; and a distance between adjacent second connection bumps is smaller than a distance between adjacent first connection bumps.

According to a specific implementation manner of the embodiment of the utility model, the packaging substrate further comprises a metal heat dissipation piece, wherein the metal heat dissipation piece is positioned on the packaging substrate and corresponds to the first chip, the second chip and the third chip respectively; and an opening is arranged on the metal heat dissipation piece and is used for enabling the optical fiber to pass through the opening and be electrically connected with the second chip or the third chip.

According to a specific implementation manner of the embodiment of the utility model, the metal heat dissipation piece comprises a heat dissipation plate and a side wall, wherein the side wall and one side of the heat dissipation plate are fixed and supported on the packaging substrate, a cavity is defined by the heat dissipation plate, the side wall and the packaging substrate, and the first chip, the second chip and the third chip are positioned in the cavity; the side wall is provided with the opening; and a heat conducting material is arranged between the heat radiating plate and the first chip, between the heat radiating plate and the second chip, and between the heat radiating plate and the third chip, and the heat conducting material is in contact with the upper surfaces of the first chip, the second chip and the third chip and the inner surface of the heat radiating plate.

In a second aspect, an embodiment of the present utility model provides a chip comprising an optoelectronic package as claimed in any one of the first aspects; and a housing for housing the optoelectronic package.

In a third aspect, an embodiment of the present utility model provides an electronic device, including a chip as described in the second aspect, and a motherboard coupled to the chip.

Drawings

In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an optoelectronic package in some embodiments of the utility model;

FIG. 2 is a schematic diagram of a package substrate according to some embodiments of the utility model;

FIG. 3 is a schematic view of a first interconnect substrate in some embodiments of the utility model;

FIG. 4 is a schematic diagram of a metal heat spreader on a package substrate according to some embodiments of the present utility model;

FIG. 5 is a schematic diagram of an optoelectronic package with optical fibers attached in some embodiments of the utility model;

FIG. 6 is a top view of an optoelectronic package in some embodiments of the utility model (with the walls on top of the metal heatsink omitted);

FIG. 7 is a schematic diagram of an optoelectronic package in further embodiments of the present utility model.

Detailed Description

Embodiments of the present utility model will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

FIG. 1 is a schematic view of an optoelectronic package 1 in some embodiments of the utility model, referring to FIG. 1, an optoelectronic package 1 provided in an embodiment of the utility model includes: a package substrate 2 and a first interconnection substrate 3, wherein a first groove 21 is formed on the package substrate 2, and the first interconnection substrate 3 is arranged in the first groove 21; and a first chip 4, a second chip 5 and a third chip 6, which are located on the package substrate 2 and are electrically connected with the package substrate 2, respectively; wherein a part of the first chip 4 and a part of the second chip 5 are electrically connected to the first interconnection substrate 3, respectively, the second chip 5 includes one of an electric chip and an optical chip, and the third chip 6 includes the other of the electric chip and the optical chip.

The first chip 4, the second chip 5 and the third chip 6 are respectively and electrically connected with the packaging substrate 2, so that the first chip 4 and the second chip 5, and the second chip 5 and the third chip 6 can be respectively and electrically connected with the packaging substrate 2, namely, the first chip 4 and the second chip 5, and the second chip 5 and the third chip 6 are adjacently arranged, a separation device can be prevented from being adopted on a main board, and delay and energy consumption of signal transmission between the chips are reduced. And signals and power sources which need to be led out on the first chip 4, the second chip 5 and the third chip 6 can be led out through the packaging substrate 2.

Moreover, the first chip 4, the second chip 5 including one of the electric chip and the optical chip, and the third chip 6 including the other of the electric chip and the optical chip are packaged in one package, and the first chip 4 and the second chip 5 can be electrically connected both through the package substrate 2 and through the first interconnection substrate 3, so that different functions between the first chip 4 and the second chip 5 can be respectively realized through the first interconnection substrate 3 and the package substrate 2, and at the same time, the first interconnection substrate 3 is provided in the groove of the package substrate 2, so that the structure of the electronic package can be made more compact.

In some examples, the package substrate 2 is a carrier for semiconductor chip packaging, and is capable of amplifying the small pitch between solder balls on a semiconductor chip to a pitch between solder balls acceptable by a motherboard, so that the chip can be electrically connected to the motherboard through the package substrate 2, while providing some protection, support, heat dissipation, assembly, etc. Where pitch refers to the distance between the centers of adjacent solder balls.

In some examples, the package substrate 2 may be a resin substrate (Ajinomoto Build-up Film substrate), ABF substrate for short in english and ABF substrate for short in chinese. The first groove 21 may be provided on a first surface (e.g., an upper surface) of the package substrate 2 by a photolithography, laser grooving, or the like process, the first interconnect substrate 3 may be formed in the first groove 21, or the formed first interconnect substrate 3 may be embedded in the first groove 21. Further, the package substrate 2 may include an adhesive layer, and the adhesive layer may be located between the first interconnection substrate 3 and the bottom of the first groove 21, and specifically, the material of the adhesive layer may be a double-sided adhesive film.

In some examples, the first chip 4 comprises a computing unit, which may specifically be a central processing unit (Central Processing Unit, CPU for short), a depth calculator, or a field-editable logic gate array (Field Programmable Gate Array, FPGA for short), or the like. The electrical chip may be a microstructure with predetermined circuit functions integrated with electronic devices such as transistors, capacitors, resistors, etc. The optical chip may be a microstructure with a predetermined circuit function integrated with an optical device such as a laser, an electro-optical modulator, a photodetector, or the like, or an electro-optical device.

In some embodiments, a portion of the third chip 6 is electrically connected to the first interconnection substrate 3, i.e. the first chip 4, the second chip 5 and the third chip 6 may also be electrically connected to the first interconnection substrate 3 by a common electrical connection to achieve an electrical connection between the first chip 4 and the second chip 5, and an electrical connection between the second chip 5 and the third chip 6.

In other embodiments, the electronic package further includes a second interconnect substrate (not shown); the package substrate 2 further has a second groove (not shown) spaced apart from the first groove 21, in which the second interconnection substrate is embedded; wherein a portion of the third chip 6 is electrically connected to the second interconnect substrate.

In some examples, a portion of the second chip 5 is electrically connected to the second interconnect substrate, i.e. the second chip 5 and the third chip 6 are electrically connected through the second interconnect substrate.

Since the second chip 5 and the third chip 6 can be electrically connected through the first interconnection substrate 3 or can be electrically connected through the second interconnection substrate, different functions between the third chip 6 and the second chip 5 can be realized through the first interconnection substrate 3 or the second interconnection substrate and the package substrate 2, and meanwhile, the first interconnection substrate 3 and the second interconnection substrate are arranged in the groove of the package substrate 2, so that the structure of the electronic package can be more compact.

In addition, the first interconnection substrate is used for realizing the electrical connection between the first chip 4 and the second chip 5, and when the second interconnection substrate is used for realizing the electrical connection between the second chip 5 and the third chip 6, the troubleshooting of the optoelectronic package 1 during the overhaul is convenient.

Fig. 2 is a schematic view of a package substrate 2 in some embodiments of the utility model, referring to fig. 2, in some embodiments, the package substrate 2 comprises: the first interconnect layer 22, the first recess 21 is provided in the first interconnect layer 22, and the first interconnect layer 22 includes first metal wiring layers 221 and first dielectric layers 222 alternately stacked.

Fig. 3 is a schematic view of a first interconnect substrate 3 in some embodiments of the utility model, referring to fig. 3, the first interconnect substrate 3 includes: the second interconnection layer 31 includes a second metal wiring layer 311 and a second dielectric layer 312 alternately stacked.

The second dielectric layer 312 includes an organic material, and the arrangement density of the second metal wiring layer 311 is greater than that of the first metal wiring layer 221.

The arrangement density refers to the line distance between two adjacent metal wires. Therefore, the wiring on the first interconnection substrate 3 is denser than the wiring on the packaging substrate 2, so that high-density interconnection of signal wires between the first chip 4 and the second chip 5 can be realized, the bandwidth of signal transmission is conveniently increased, the delay of signal transmission between the first chip 4 and the second chip 5 is reduced, and the overall energy consumption is reduced.

In some examples, the line width and line spacing of the metal lines in the first metal wiring layer 221 may be 12um, the width of a single metal trace in the second metal wiring layer 311 may be 0.5um-5um, and the interval between two adjacent metal traces may be 0.5um-5um.

In some embodiments, the organic material includes polyimide, so that the processing equipment and processing environment do not need to use a conventional silicon process when processing the first interconnect substrate 3, which can reduce production costs.

In some examples, the first interconnect substrate 3 further includes a substrate 32, and the second interconnect layer 31 is disposed on the substrate 32. The material of the substrate 32 may be silicon, glass, ceramic, or the like, and the second interconnect layer 31 is easily deformed, so that the second interconnect layer 31 is provided on the substrate 32 to facilitate mounting of the first interconnect substrate 3 on the package substrate 2.

The structure of the second interconnection substrate is the same as that of the first interconnection substrate 3, and has the same advantageous effects as those of the first interconnection substrate 3, and will not be described again here.

Referring to fig. 2, in some embodiments, the package substrate 2 further comprises: the first connection bumps 23 are located on the upper surface of the first interconnection layer 22, and the first chip 4, the second chip 5 and the third chip 6 are electrically connected to the package substrate 2 through the first connection bumps 23.

Referring to fig. 3, the first interconnect substrate 3 further includes: a plurality of second connection bumps 33 are located on the upper surface of the second interconnection layer 31, and a portion of the first chip 4 and a portion of the second chip 5 are electrically connected to the first interconnection substrate 3 through the second connection bumps 33.

In some examples, the first and second connection bumps 23 and 33 may be spherical connection bumps. The first connection bump 23 may include a first copper pillar electrically connected with the first interconnection layer 22 on the package substrate 2 and a first solder ball provided at an end of the first copper pillar. The second connection bump 33 may include a second copper pillar electrically connected with the second interconnection layer 31 on the first interconnection substrate 3 and a second solder ball provided at an end of the second copper pillar.

In some examples, the first chip 4 may include a third connection bump (not shown) corresponding to the first connection bump 23, and the third connection bump may include a third copper pillar and a third solder ball provided at an end of the third copper pillar, and the first chip 4 may be electrically connected to the package substrate 2 by soldering the third solder ball to the first solder ball one by one. The first chip 4 may further include fourth connection bumps (not shown) corresponding to the second connection bumps 33, the fourth connection bumps and the third connection bumps being located at different areas on the same surface of the first chip 4, the fourth connection bumps may include fourth copper pillars and fourth solder balls provided at ends of the fourth copper pillars, and the first chip 4 and the first interconnection substrate 3 may be electrically connected by soldering the fourth solder balls and the second solder balls one by one.

In some examples, the second chip 5 may include fifth connection bumps (not shown) corresponding to the first connection bumps 23, and the fifth connection bumps may include fifth copper pillars and fifth solder balls provided at ends of the fifth copper pillars, and the second chip 5 may be electrically connected to the package substrate 2 by soldering the fifth solder balls to the first solder balls one by one. The second chip 5 may further include a sixth connection bump (not shown) corresponding to the second connection bump 33, the sixth connection bump and the third connection bump being located at different areas on the same surface of the first chip 4, the sixth connection bump may include a sixth copper pillar and a sixth solder ball provided at an end of the sixth copper pillar, and the second chip 5 and the first interconnection substrate 3 may be electrically connected by soldering the sixth solder ball and the second solder ball one by one.

In some examples, the third chip 6 may include a seventh connection bump (not shown) corresponding to the first connection bump 23, and the seventh connection bump may include a seventh copper pillar and a seventh solder ball provided at an end of the seventh copper pillar, and the third chip 6 may be electrically connected with the package substrate 2 by soldering the seventh solder ball with the first solder ball one by one.

In some embodiments, at least one of the following is satisfied between the second connection bump 33 and the first connection bump 23: the width of the second connection bump 33 (refer to the width in the direction parallel to the interconnect substrate) is smaller than the width of the first connection bump 23; and the distance between the adjacent second connection bumps 33 is smaller than the distance between the adjacent first connection bumps 23.

In some examples, the width of the second connection bump 33 is smaller than the width of the first connection bump 23, and the diameter of the second connection bump 33 may be smaller than the diameter of the first connection bump 23.

In this embodiment, the distance between the adjacent connection bumps on the first interconnection substrate 3 is smaller than the distance between the adjacent connection bumps on the package substrate 2, and accordingly, the wiring on the first interconnection substrate 3 is denser than the wiring on the package substrate 2, so that high-density interconnection of the signal lines between the first chip 4 and the second chip 5 can be realized, and the bandwidth of signal transmission can be increased conveniently.

Currently, the existing silicon photofabrication is limited by the silicon photofabrication process, and the existing silicon photofabrication chip can only generally use a large process node, such as several tens of nm. In this embodiment, the data processing section and the light conversion section in the conventional silicon optical chip are separated and manufactured into different units, i.e., an electrical chip and an optical chip, respectively. The electrical chip may include a number of data processing modules such as amplifiers, timing and data recovery devices, drivers, etc.; the optical chip may include optical or optoelectronic devices such as lasers, electro-optic modulators, and the like.

Larger process nodes may be employed for the optical chips therein. And aiming at the chip in the circuit, smaller process nodes such as about 10nm can be adopted, so that high-density interconnection of signal lines between the electric chip and the first chip 4 (comprising a computing unit) is realized through the first interconnection substrate 3, the bandwidth of signal transmission is increased, and the delay increase caused by changing the narrow bit width into the high bit width for many times under the condition of insufficient bit width is avoided.

For the first chip 4 and the second chip 5, a region requiring high-density interconnection (such as a signal transmission portion having a high bandwidth requirement) may be interconnected by the first interconnection substrate 3, and a region not requiring high-density interconnection (such as a power supply or a signal transmission portion having a relatively low bandwidth requirement) may be led out through the package substrate 2. For the area needing high-density interconnection, a precise process can be adopted; for areas where high density interconnects are not required, common processes may be used. Compared with the whole precise process, in the embodiment, under the condition of realizing high-density interconnection, the precise process is combined with the common process, so that the cost in the process can be reduced.

Fig. 4 is a schematic view of a metal heat spreader 8 on a package substrate 2 according to some embodiments of the present utility model, referring to fig. 4, in an embodiment, the electronic package further includes a metal heat spreader 8 on the package substrate 2, where the metal heat spreader 8 corresponds to the first chip 4, the second chip 5, and the third chip 6, respectively; an opening is provided in the metal heat sink 8, and fig. 5 is a schematic diagram of an electronic package with an optical fiber 9 connected thereto in some embodiments of the present utility model, for electrically connecting the optical fiber 9 to the second chip 5 or the third chip 6 through the opening.

Fig. 6 is a top view of an electronic package with optical fibers 9 attached (walls on top of metal heat sink 8 omitted) in some embodiments of the utility model, see fig. 5 and 6, where in some examples an opening is used for optical fibers 9 to electrically connect with a third chip 6 through the opening, where the second chip comprises an electrical chip and the third chip comprises an optical chip.

The metal heat sink 8, which may also be referred to as a metal heat sink cover, a heat sink, etc., is used to discharge heat generated on the first chip 4, the second chip 5, and the third chip 6, so as to ensure stable performance of the first chip 4, the second chip 5, and the third chip 6. The material of the metal heat sink 8 may be copper, aluminum alloy, or the like.

Referring to fig. 4, the metal heat dissipation element 8 may include a heat dissipation plate 81 and a side wall 82, wherein the side wall 82 and one side (e.g. lower side) of the heat dissipation plate 81 are fixed and supported on the package substrate 2, and the heat dissipation plate 81, the side wall 82 and the package substrate 2 define a cavity, and the first chip 4, the second chip 5 and the third chip 6 are located in the cavity; the opening is provided at the side wall 82.

In some embodiments, the metal heat sink 8 may be a sheet metal part. The metal heat spreader 8 is supported on the package substrate 2 by a side wall 82.

In some examples, a first end (e.g., top end) end surface of the side wall 82 is integrally connected with an edge of one side of the heat dissipation plate 81, and a second end (e.g., bottom end) end surface of the side wall 82 abuts against the package substrate 2. Glue is arranged on the packaging substrate 2 at a position opposite to the side wall 82, and the side wall 82 is fixed on the packaging substrate 2 to provide support for the fastening force required by the system radiator. The optical fiber 9 may be damaged under high temperature conditions, and the soldering of the electronic package on the motherboard by reflow soldering requires high temperature conditions, so that the optical fiber 9 is electrically connected to the second chip 5 or the third chip 6 by a connector after reflow soldering.

There may be an incomplete contact between the heat dissipation plate 81 and the first, second and third chips 4, 5 and 6, and when there is a certain gap between the heat dissipation plate 81 and the first, second and third chips 4, 5 and 6, there is a large thermal resistance. In some embodiments, a heat conductive material is provided between the heat dissipation plate 81 and the first, second and third chips 4, 5 and 6, and is in contact with upper surfaces of the first, second and third chips 4, 5 and 6 and inner surfaces of the heat dissipation plate 81.

A heat conductive material, which may also be referred to as a thermal interface material or the like, is used to reduce the contact thermal resistance between the heat spreader 81 and the first, second and third chips 4, 5 and 6. The heat conducting material can be heat conducting silicone grease, heat conducting paste, etc.

In this embodiment, by disposing the heat conducting material between the heat dissipating plate 81 and the first chip 4, the second chip 5 and the third chip 6, the thermal resistance between the heat dissipating plate 81 and the first chip 4, the second chip 5 and the third chip 6 can be effectively reduced, so that the heat generated by the first chip 4, the second chip 5 and the third chip 6 can be rapidly transferred to the heat dissipating plate 81.

In some embodiments, any two of the first chip 4, the second chip 5, and the third chip 6 are integrated into one single piece.

FIG. 7 is a schematic diagram of an optoelectronic package in some embodiments of the utility model, referring to FIG. 7, in some examples, the first chip 4 and the second chip 5 are integrated into one single piece 7.

In this way, by integrating the first chip 4, the second chip 5 and the third chip 6 into one single chip, the signal transmission conversion link between any two of the first chip 4, the second chip 5 and the third chip 6 can be further reduced, so that the signal transmission delay between any two of the first chip 4, the second chip 5 and the third chip 6 can be reduced, the signal transmission delay can be further reduced, and meanwhile, the whole energy consumption can be reduced due to the reduction of the conversion link.

The embodiment of the utility model also provides a chip, which comprises a packaging shell, wherein the optoelectronic package 1 of any embodiment is packaged in the packaging shell. The chip of this embodiment has the same advantages as the packaged optoelectronic package 1, and will not be described in detail herein.

The embodiment of the utility model also provides electronic equipment, which comprises a main board, wherein a chip is arranged on the main board, and the chip is the chip in the embodiment. The electronic device of the present embodiment has the same advantages as the encapsulated optoelectronic package 1, and will not be described herein.

It should be noted that, in this document, emphasis on the solutions described between the embodiments is different, but there is a certain interrelation between the embodiments, and when understanding the solution of the present utility model, the embodiments may refer to each other; additionally, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing is merely illustrative of the present utility model, and the present utility model is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present utility model should be included in the present utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.

Claims (12)

1. An optoelectronic package, comprising: the packaging structure comprises a packaging substrate and a first interconnection substrate, wherein a first groove is formed in the packaging substrate, and the first interconnection substrate is arranged in the first groove; and

the first chip, the second chip and the third chip are positioned on the packaging substrate and are respectively and electrically connected with the packaging substrate;

wherein a portion of the first chip and a portion of the second chip are electrically connected to the first interconnection substrate, respectively, the second chip includes one of an electrical chip and an optical chip, and the third chip includes the other of the electrical chip and the optical chip.

2. The optoelectronic package of claim 1, further comprising a second interconnect substrate; the packaging substrate is also provided with a second groove which is arranged at intervals with the first groove, and the second interconnection substrate is embedded in the second groove; wherein a portion of the third chip is electrically connected to the second interconnect substrate.

3. The optoelectronic package of claim 1, wherein the first chip, the second chip, and the third chip are spaced apart.

4. The electronic package of claim 1, wherein any two of the first chip, the second chip, and the third chip are integrated into a single piece.

5. The optoelectronic package of claim 1 wherein,

the package substrate includes:

the first groove is formed in the first interconnection layer, and the first interconnection layer comprises first metal connecting wire layers and first dielectric layers which are alternately stacked;

the first interconnect substrate includes:

and the second interconnection layer comprises second metal wire layers and second dielectric layers which are alternately stacked, wherein the second dielectric layers comprise organic materials, and the arrangement density of the second metal wire layers is greater than that of the first metal wire layers.

6. The optoelectronic package of claim 5, wherein the organic material comprises polyimide.

7. The optoelectronic package of claim 5, wherein the package substrate further comprises:

the first connecting bumps are positioned on the upper surface of the first interconnection layer, and the first chip, the second chip and the third chip are electrically connected with the packaging substrate through the first connecting bumps;

the first interconnect substrate further includes: and the second connecting bumps are positioned on the upper surface of the second interconnection layer, and the part of the first chip and the part of the second chip are electrically connected with the first interconnection substrate through the second connecting bumps.

8. The optoelectronic package of claim 7, wherein at least one of the following is satisfied between the second connection bump and the first connection bump:

the width of the second connecting convex block is smaller than that of the first connecting convex block; and a distance between adjacent second connection bumps is smaller than a distance between adjacent first connection bumps.

9. The optoelectronic package of claim 1, further comprising a metal heat spreader on the package substrate, the metal heat spreader corresponding to the first chip, the second chip, and the third chip, respectively;

and an opening is arranged on the metal heat dissipation piece and is used for enabling the optical fiber to pass through the opening and be electrically connected with the second chip or the third chip.

10. The optoelectronic package of claim 9, wherein the metal heat spreader comprises a heat spreader plate and a side wall, the side wall being fixed to one side of the heat spreader plate and supported on the package substrate, the heat spreader plate, the side wall, and the package substrate defining a cavity within which the first chip, the second chip, and the third chip are located; the side wall is provided with the opening;

and a heat conducting material is arranged between the heat radiating plate and the first chip, between the heat radiating plate and the second chip, and between the heat radiating plate and the third chip, and the heat conducting material is in contact with the upper surfaces of the first chip, the second chip and the third chip and the inner surface of the heat radiating plate.

11. A chip comprising an optoelectronic package according to any one of claims 1 to 10; and a housing for housing the optoelectronic package.

12. An electronic device comprising the chip of claim 11, and a motherboard coupled to the chip.

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