CN219203166U

CN219203166U - Power semiconductor device and switching power supply

Info

Publication number: CN219203166U
Application number: CN202320070530.8U
Authority: CN
Inventors: 张邵华
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2023-01-10
Filing date: 2023-01-10
Publication date: 2023-06-16
Anticipated expiration: 2033-01-10

Abstract

Disclosed are a power semiconductor device and a switching power supply, the power semiconductor device including: a silicon carbide substrate having a first doping type; an epitaxial layer on the silicon carbide substrate having a first doping type; an accumulation-type channel structure and an inversion-type channel structure, wherein the accumulation-type channel structure and the inversion-type channel structure are arranged at intervals, part of the accumulation-type channel structure and the inversion-type channel structure are positioned in the epitaxial layer, and part of the accumulation-type channel structure and the inversion-type channel structure are positioned on the epitaxial layer; and an isolation structure isolating the accumulation-type channel structure and the inversion-type channel structure from each other. The utility model adopts transistors with different channel types to be integrated on the same chip, has simple process and reduces the complexity and cost of the chip.

Description

Power semiconductor device and switching power supply

Technical Field

The present utility model relates to the field of semiconductor manufacturing technologies, and in particular, to a power semiconductor device and a switching power supply.

Background

Silicon carbide (SiC) material has excellent physical and electrical characteristics, and is an ideal semiconductor material for manufacturing high-power, high-frequency, high-voltage, high-temperature-resistant and radiation-resistant devices by the unique advantages of wide forbidden band, high thermal conductivity, high saturation drift speed, high critical breakdown electric field and the like. The silicon carbide MOSFET device has the advantages of high switching speed, small on-resistance and the like, can realize higher breakdown voltage level at smaller thickness of the drift layer, reduces the volume of the power switch module, reduces energy consumption, and has obvious advantages in the application fields of power switches, converters and the like.

Fig. 1 is a schematic circuit diagram of a prior art high voltage switching power supply. As shown in fig. 1, the high-voltage switching power supply 100 includes a voltage stabilizing circuit 101, a driving control circuit 102, and a high-voltage power device 103, and is typically zero potential with reference to ground. When the high-voltage switching power supply 100 starts to operate, the high-voltage power supply supplies an operating voltage and current to the drive control circuit 102 through the voltage stabilizing circuit 101. The first terminal HV of the high voltage power device 103 is connected to the high voltage power supply, the second terminal LV is connected to the reference ground, and the control terminal DR receives the driving signal. When the drive control circuit 102 starts to operate, the high-voltage power device 103 is controlled to be turned on to perform power conversion. The high-voltage power device 103 is a MOS device or an IGBT device, wherein a first end of the MOS device is a drain electrode, a second end of the MOS device is a source electrode, and a control end of the MOS device is a grid electrode; the first end of the IGBT device is a collector electrode, the second end of the IGBT device is an emitter electrode, and the control end of the IGBT device is a base electrode. Of course, the high voltage power device 103 may also be other types of devices, not to be limiting.

The voltage stabilizing circuit 101 steps down the high voltage power supply through a high voltage resistor, thereby supplying the drive control circuit 102 with an operating voltage and current. One end of the high-voltage resistor is connected to the high-voltage power supply, and the other end is connected to the drive control circuit 102. Because the current on the high-voltage resistor always exists, the starting time and the power consumption cannot be simultaneously considered, and especially when the voltage of the high-voltage power supply is very high, the power consumption on the high-voltage resistor can be further increased.

In the prior art, a low-voltage control circuit, a high-voltage MOS device and a voltage stabilizing circuit are integrated on the same silicon substrate, and the switching power supply is realized by adopting a high-voltage BCD (binary coded decimal) process, so that the starting time and the power consumption can be simultaneously considered.

However, the switching power supply adopts a high-voltage BCD technology, so that the technology of the whole system chip is complex and the cost is high, and the power consumption of the MOS device in the high-voltage BCD technology cannot be increased due to the limitation of the high-temperature characteristic of the silicon material, so that the high-power application cannot be expanded; meanwhile, the BCD process cannot be realized on the silicon carbide material, and the application and popularization of the technology are not facilitated.

Disclosure of Invention

In view of the above problems, the present utility model aims to provide a power semiconductor device and a switching power supply, which adopt transistors with different channel types to be integrated on the same chip, and have simple process and reduced complexity and cost of the chip.

According to a first aspect of the present utility model, there is provided a power semiconductor device comprising: a silicon carbide substrate having a first doping type; an epitaxial layer on the silicon carbide substrate having a first doping type; an accumulation-type channel structure and an inversion-type channel structure, wherein the accumulation-type channel structure and the inversion-type channel structure are arranged at intervals, part of the accumulation-type channel structure and the inversion-type channel structure are positioned in the epitaxial layer, and part of the accumulation-type channel structure and the inversion-type channel structure are positioned on the epitaxial layer; and an isolation structure isolating the accumulation-type channel structure and the inversion-type channel structure from each other.

Preferably, the accumulation-type channel structure includes at least one accumulation-type cell structure, each accumulation-type cell structure including: the first well region is positioned in the epitaxial layer and is provided with a second doping type; an accumulation channel layer, which is positioned on the surface of the first well region and has a first doping type; a first ohmic contact region in the first well region and extending from a surface of the first well region toward an interior of the first well region, the first ohmic contact region having a second doping type; the first source region is positioned on the surface of the first well region, has a certain distance from the outer edge of the first well region, has a first doping type and is in contact with the first ohmic contact region; and the first grid structure is positioned on the epitaxial layer and covers the accumulation channel layer and part of the first source region.

Preferably, the inversion channel structure comprises at least one inversion cell structure, each inversion cell structure comprising: the second well region is positioned in the epitaxial layer and is provided with a second doping type; a second ohmic contact region in the second well region and extending from a surface of the second well region toward an interior of the second well region, the second ohmic contact region having a second doping type; the second source region is positioned on the surface of the second well region and has a certain distance from the outer edge of the second well region, has a first doping type and is in contact with the second ohmic contact region; and the second grid structure is positioned on the epitaxial layer and covers part of the second well region and part of the second source region.

Preferably, the first gate structure includes a first gate oxide layer and a first gate poly, the first gate oxide layer being located on a portion of the epitaxial layer, the accumulation channel layer, and a portion of the first source region, the first gate poly being located on the first gate oxide layer; the second gate structure comprises a second gate oxide layer and a second gate polycrystal, the second gate oxide layer is located on a part of the epitaxial layer, a part of the second well region and a part of the second source region, and the second gate polycrystal is located on the second gate oxide layer.

Preferably, the power semiconductor device further includes: the dielectric layer is positioned on the epitaxial layer and covers the surface of the first gate polycrystal, the first gate oxide layer and the side wall of the first gate polycrystal, the surface of the second gate polycrystal and the side wall of the second gate oxide layer and the side wall of the second gate polycrystal; the first source electrode is positioned on the dielectric layer and connected with the first ohmic contact area and the first source area; the second source electrode is positioned on the dielectric layer and connected with the second ohmic contact region and the second source region; a drain electrode located on a surface of the silicon carbide substrate remote from the epitaxial layer; wherein the drain of the accumulation-mode channel structure and the drain of the inversion-mode channel structure are common.

Preferably, the isolation structure comprises: a third well region located in the epitaxial layer; a third gate structure on the epitaxial layer covering a portion of the third well region and adjacent the accumulation channel layer and a portion of the first source region; the fourth grid structure is positioned on the epitaxial layer and covers part of the third well region, part of the second well region and part of the second source region which are adjacent to the third well region; wherein the third well region is positioned between the third gate structure and the fourth gate structure, and the third well region floats; the third grid structure is connected with the first source electrode; the fourth grid structure is connected with the second source electrode; the junction depths of the first well region, the second well region and the third well region in the epitaxial layer are the same.

Preferably, the isolation structure comprises: a first doped region in the epitaxial layer; a third gate structure on the epitaxial layer covering a portion of the first doped region and adjacent the accumulation channel layer and a portion of the first source region; the fourth grid structure is positioned on the epitaxial layer and covers part of the first doped region, part of the second well region and part of the second source region which are adjacent to the first doped region; wherein the first doped region is located between the third gate structure and the fourth gate structure, and the first doped region floats; the third grid structure is connected with the first source electrode; the fourth grid structure is connected with the second source electrode; the junction depth of the first doped region in the epitaxial layer is different from the junction depths of the first well region and the second well region in the epitaxial layer.

Preferably, the isolation structure comprises: a second doped region in the epitaxial layer; a first field oxide layer and a second field oxide layer on the epitaxial layer, wherein the first field oxide layer covers part of the second doped region and part of the second well region and part of the second source region of the adjacent accumulation channel structure; the second doped region is positioned between the first field oxide layer and the second field oxide layer, and the second doped region floats; the junction depth of the second doped region in the epitaxial layer is the same as or different from the junction depths of the first well region and the second well region in the epitaxial layer.

Preferably, the isolation structure comprises: a third doped region in the epitaxial layer; a third gate structure on the epitaxial layer covering a portion of the third doped region and adjacent the accumulation channel layer and a portion of the first source region; the fourth grid structure is positioned on the epitaxial layer and covers part of the third doped region, part of the second well region and part of the second source region which are adjacent to the third doped region; wherein the third doped region is located between the third gate structure and the fourth gate structure, and the third doped region is floating; the third grid structure is connected with the first source electrode; the fourth grid structure is connected with the second grid structure; wherein the junction depth of the third doped region in the epitaxial layer is the same as or different from the junction depths of the first well region and the second well region in the epitaxial layer.

Preferably, the accumulation-type channel structure includes at least one accumulation-type cell structure, each accumulation-type cell structure including: a first trench in the epitaxial layer extending from a surface of the epitaxial layer into the epitaxial layer; a first gate structure located within the first trench; the first well region is positioned in the epitaxial layer, positioned at two sides of the first groove and provided with a second doping type; a first source region located in the first well region and extending from a surface of the first well region toward an interior of the first well region, having a first doping type; the first ohmic contact region is positioned on the surface of the first well region between the adjacent first grooves, has a certain distance from the adjacent first grooves, has a second doping type and is in contact with the first source region; and an accumulation channel layer which is positioned in the first well region below the first source region and positioned at two sides of the first groove and has a first doping type.

Preferably, the inversion channel structure comprises at least one inversion cell structure, each inversion cell structure comprising: a second trench in the epitaxial layer extending from a surface of the epitaxial layer into the epitaxial layer; a second gate structure located within the second trench; the second well region is positioned in the epitaxial layer, positioned at two sides of the second groove and provided with a second doping type; a second source region located in the second well region and extending from a surface of the second well region toward an interior of the second well region, having a first doping type; and the second ohmic contact region is positioned on the surface of the second well region between the adjacent second trenches and has a certain distance from the adjacent second trenches, has a second doping type and is in contact with the second source region.

Preferably, the first gate structure includes a first gate oxide layer and a first gate poly, the first gate oxide layer covers an inner wall of the first trench, and the first gate poly is located on the first gate oxide layer; the second gate structure comprises a second gate oxide layer and a second gate polycrystal, the second gate oxide layer covers the inner wall of the second groove, and the second gate polycrystal is located on the second gate oxide layer.

Preferably, the power semiconductor device further includes: the dielectric layer is positioned on the epitaxial layer and covers part of the first source region, the first grid structure, part of the second source region and the second grid structure; the first source electrode is positioned on the dielectric layer and connected with the first ohmic contact area and the first source area; the second source electrode is positioned on the dielectric layer and connected with the second ohmic contact region and the second source region; a drain electrode located on a surface of the silicon carbide substrate remote from the epitaxial layer; wherein the drain of the accumulation-mode channel structure and the drain of the inversion-mode channel structure are common.

Preferably, the isolation structure comprises: a fourth doped region located in the epitaxial layer; a third gate structure located in the first trench in the epitaxial layer and in contact with the fourth doped region and the adjacent first source region and accumulation channel layer; a fourth gate structure located in the second trench in the epitaxial layer and in contact with the fourth doped region and the adjacent second well region and second source region; the fourth doped region is positioned between the third gate structure and the fourth gate structure, and the fourth doped region floats; the third grid structure is connected with the first source electrode; the fourth grid structure is connected with the second source electrode; and the junction depth of the fourth doped region in the epitaxial layer is the same as or different from the junction depth of the first well region and the second well region in the epitaxial layer.

Preferably, the threshold value of the electrical parameter of the accumulation-type channel structure is lower than the threshold value of the electrical parameter of the inversion-type channel structure.

Preferably, the power semiconductor device further includes: and the high-voltage ring is positioned at the edge of the power semiconductor device, surrounds the accumulation type channel structure, the inversion type channel structure and the isolation structure and has a second doping type.

Preferably, the power semiconductor device is a MOS device or an IGBT device.

Preferably, the power semiconductor device comprises at least one accumulation channel structure, at least one inversion channel structure, and at least one isolation structure.

According to another aspect of the present utility model, there is provided a switching power supply comprising: the voltage stabilizing circuit is used for converting the high-voltage power supply into working voltage; the driving control circuit is connected with the voltage stabilizing circuit and used for generating a driving signal and a control signal according to the working voltage; the high-voltage power device is connected with the drive control circuit and is used for being turned on and off according to the drive signal; the high-voltage power device comprises a first transistor, the structure of the high-voltage power device is an inverse channel structure, the voltage stabilizing circuit comprises a second transistor, the structure of the voltage stabilizing circuit is an accumulation channel structure, the voltage stabilizing circuit and the high-voltage power device are integrated on the same substrate to form a power semiconductor device, and the structure of the power semiconductor device is as described above.

Preferably, a first end of the first transistor is connected with a high-voltage power supply, a second end of the first transistor is connected with a reference ground, and a control end of the first transistor is connected with a driving end of a driving control circuit to receive the driving signal; the first end of the second transistor is connected with the high-voltage power supply, the second end of the second transistor is connected with the power supply end of the drive control circuit, the working voltage is provided for the drive control circuit, and the control end of the second transistor is connected with the control end of the drive control circuit; when the switching power supply is just started, the control end and the power supply end of the driving control circuit are both in zero potential, the second transistor is conducted, working voltage is provided for the driving control circuit to enable the driving control circuit to work, and a driving signal output by the driving control circuit controls the first transistor to be conducted; after the starting stage of the switching power supply is completed, the driving control circuit sets the control end of the second transistor to zero potential through the control end of the driving control circuit to turn off the second transistor, and when the potential of the power end of the driving control circuit drops to a certain level, the driving signal output by the driving end of the driving control circuit controls the first transistor to turn off.

The power semiconductor device and the switching power supply provided by the embodiment of the utility model adopt transistors with different channel types to be integrated on the same chip, have simple process and reduce the complexity and cost of the chip.

Further, the power semiconductor device comprises a transistor with an accumulation type channel structure and a transistor with an inversion type channel structure, and the accumulation type channel structure and the inversion type channel structure can apply different control voltages to respectively control the on and off of different structures.

Furthermore, the inversion channel structure and the accumulation channel structure are basically the same, and share the same substrate and epitaxial layer, but the formation steps of the well regions of the inversion channel structure and the accumulation channel structure are different, and the rest process steps are completely the same, so that the processing complexity and cost of the chip are reduced.

Further, the doping concentrations of the first well region, the accumulation channel layer and the second well region are different, and the concentration of the accumulation channel layer can be adjusted so that the threshold value of the accumulation channel structure is low.

Further, the isolation structure comprises a third gate structure, a fourth gate structure and a third well region floating between the third gate structure and the fourth gate structure, the third gate structure covers the adjacent accumulation channel layer and is connected with the first source electrode, and the fourth gate structure covers the adjacent second well region and is connected with the second source electrode, so that isolation withstand voltage between the accumulation channel structure and the inversion channel structure can be improved.

Further, the isolation structure comprises a third gate structure, a fourth gate structure and a floating doped region arranged between the third gate structure and the fourth gate structure, the doped region is formed independently, and the junction depth of the first doped region in the epitaxial layer can be adjusted to adjust the size of the isolation withstand voltage.

Further, the accumulation type channel structure and the inversion type channel structure can be integrated in the same high-voltage ring, and the area of at least one high-voltage ring is reduced by adopting the structure in the patent because the area of the high-voltage ring of the high-voltage device is large, so that the area of a chip is reduced.

Drawings

The above and other objects, features and advantages of the present utility model will become more apparent from the following description of embodiments of the present utility model with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a prior art switching power supply;

fig. 2 shows a schematic circuit structure of a switching power supply according to an embodiment of the present utility model;

fig. 3 shows a schematic cross-sectional view of a power semiconductor device provided by a first embodiment of the present utility model;

fig. 4 is a schematic view showing impurity concentration distribution of a first well region and a second well region according to a first embodiment of the present utility model;

fig. 5a shows a schematic layout of a power semiconductor device according to a first embodiment of the present utility model;

Fig. 5b shows a schematic layout of a power semiconductor device according to a second embodiment of the present utility model;

fig. 6a to 6f are schematic cross-sectional views showing different stages of a method of manufacturing a power semiconductor device according to a first embodiment of the present utility model;

fig. 7 is a schematic cross-sectional view showing a power semiconductor device according to a third embodiment of the present utility model;

fig. 8 shows a schematic cross-sectional view of a power semiconductor device provided by a fourth embodiment of the present utility model;

fig. 9 shows a schematic cross-sectional view of a power semiconductor device provided by a fifth embodiment of the present utility model;

fig. 10 shows a schematic cross-sectional view of a power semiconductor device provided by a sixth embodiment of the present utility model.

Detailed Description

Various embodiments of the present utility model will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.

The following describes in further detail the embodiments of the present utility model with reference to the drawings and examples.

Fig. 2 shows a schematic circuit structure of a switching power supply according to an embodiment of the present utility model. Referring to fig. 2, the high voltage switching power supply 200 includes a voltage stabilizing circuit 201, a driving control circuit 202, and a high voltage power device 203, and is typically zero potential with reference to ground. When the high-voltage switching power supply 200 starts to operate, the high-voltage power supply supplies an operating voltage and current to the drive control circuit 202 through the voltage stabilizing circuit 201. The first terminal HV of the high-voltage power device 203 is connected to the high-voltage power supply, the second terminal LV is connected to the reference ground, and the control terminal DR receives the driving signal. When the drive control circuit 202 starts to operate, the high-voltage power device 203 is controlled to be turned on to perform power conversion. The voltage stabilizing circuit 201 and the high-voltage power device 203 are transistor devices, for example, a MOS device or an IGBT device, where a first end of the MOS device is a drain electrode, a second end is a source electrode, and a control end is a gate electrode; the first end of the IGBT device is a collector electrode, the second end of the IGBT device is an emitter electrode, and the control end of the IGBT device is a base electrode.

In this embodiment, the high-voltage power device 203 is a first transistor M1, and the voltage stabilizing circuit 201 uses a second transistor M2 to step down the high-voltage power.

The first transistor M1 adopts an inversion channel structure, the second transistor M2 adopts an accumulation channel structure, and the high-voltage power device 203 and the voltage stabilizing circuit 201 are integrated on the same substrate to form the power semiconductor device 300 of the present application.

The first end HV of the first transistor M1 is connected to the high voltage power supply, the second end LV of the first transistor M1 is connected to the reference ground, and the control end DR of the first transistor M1 is connected to the driving end DR of the driving control circuit 202; the first terminal HV of the second transistor M2 is connected to the high voltage power supply, the second terminal of the second transistor M2 is output to the power supply terminal Vcc of the drive control circuit 202, and the drive control circuit 202 is provided with an operating voltage and current, and the control terminal Ctrl of the second transistor M2 is connected to the control terminal Ctrl of the drive control circuit 202.

When the switching power supply system is just started, the drive control circuit 202 does not work, the circuit outputs are all at zero potential, and the control terminal Ctrl and the power supply terminal Vcc of the drive control circuit 202 are both at zero potential. The gate and the source of the second transistor M2 are at zero potential, the second transistor M2 is turned on, and a current flows from the drain to the source of the second transistor M2, that is, from the first terminal HV to the power supply terminal Vcc of the drive control circuit 202; at the same time, the source potential of the second transistor M2 starts to rise, providing the drive control circuit 202 with an operating voltage and current. The driving control circuit 202 starts to operate, the driving end DR outputs a driving voltage of 10V to 15V, and the first transistor M1 is turned on. And the switching power supply system completes starting, works normally and performs power conversion.

After the start-up phase is completed, the gate and source of the second transistor M2 reach a high level. At this time, the driving control circuit 202 sets the gate of the second transistor M2 to zero potential through the control terminal Ctr1, and generates a negative voltage between the gate and the source of the second transistor M2, thereby turning off the accumulation channel type device, i.e., turning off the second transistor M2. After the system is operating normally, the power supply Vcc is continuously lowered by the drive control circuit 202 due to power consumption. When the power supply terminal Vcc drops to a certain level, the driving terminal DR of the driving control circuit 202 outputs a low level to turn off the first transistor M1. The control terminal Ctrl of the driving control circuit 202 sets the gate of the second transistor M2 to a high level, and the second transistor M2 is turned on to restart the start-up process.

Through the above description of the operation process, in the whole operation process, the first transistor M1 and the second transistor M2 may have voltage differences between the source electrodes and the gate electrodes of the two devices, and a certain isolation withstand voltage is required between the source electrodes and the gate electrodes of the two devices, otherwise, the system may not work normally.

The power semiconductor device provided by the utility model integrates the first transistor M1 and the second transistor M2 on the same chip, and the first transistor and the second transistor adopt different types of channel structures, so that the first transistor and the second transistor can be formed on the same silicon carbide substrate at the same time, the process is simple, and the complexity and the cost of the chip are reduced.

In the utility model, when the first doping type is N type, the second doping type is P type; when the first doping type is P type, the second doping type is N type.

It should be noted that the manufacturing process in the embodiments may be modified or sequentially adjusted according to the actual situation. Meanwhile, for convenience of description, the embodiment is described only with an N-type MOSFET; the same applies for P-type MOSFETs.

Fig. 3 shows a schematic cross-sectional view of a power semiconductor device according to a first embodiment of the utility model; fig. 5A shows a schematic layout of the power semiconductor device according to the first embodiment of the present utility model in fig. 3, wherein fig. 3 is a schematic cross-sectional view taken along the line 5A-5B in fig. 5A, and fig. 5B shows a schematic layout of the power semiconductor device according to the second embodiment of the present utility model. In this embodiment, the power semiconductor device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Hereinafter, an N-type MOSFET is exemplified, however, the present utility model is not limited thereto.

Referring to fig. 3, the power semiconductor device 300 includes a silicon carbide substrate 301, an epitaxial layer 302 on the silicon carbide substrate 301, an accumulation-type channel structure 310 and an inversion-type channel structure 320, and an isolation structure 330, a portion of the accumulation-type channel structure 310 and the inversion-type channel structure 320 being located in the epitaxial layer 302, and a portion of the accumulation-type channel structure 310 and the inversion-type channel structure 320 being located on the epitaxial layer 302.

In this embodiment, the silicon carbide substrate 301 and the epitaxial layer 302 have a first doping type.

The accumulation-mode channel structure 310 includes at least one accumulation-mode cell structure, each accumulation-mode cell structure including a first well region 311, a first ohmic contact region 312, a first source region 313, an accumulation channel layer 314, and a first gate structure.

In this embodiment, the first well region 311 is located in the epitaxial layer 302 and has a second doping type, and the second doping type is opposite to the first doping type. A first ohmic contact region 312 is located in the first well region 311 and has a second doping type. The first source region 313 is located on the surface of the first well region 311 and has a certain distance from the outer edge of the first well region 311, and has a first doping type, and the first source region 313 is in contact with the first ohmic contact region 312. The first source region 313 and the first ohmic contact region 312 each extend from the surface of the first well region 311 toward the inside of the first well region 311. An accumulation channel layer 314 is located on the surface of the first well region 311, and has a first doping type. Specifically, the accumulation channel layer 314 is located on the surface of the first well region 311 except for the first source region 313 and the first ohmic contact region 312. A first gate structure is located on the epitaxial layer 302 and covers the accumulation channel layer 314 and a portion of the first source region 313.

The first gate structure includes a first gate oxide 315 and a first gate poly 316, the first gate oxide 315 being located on a portion of the epitaxial layer 302, the accumulation channel layer 314, and a portion of the first source region 313, the first gate poly 316 being located on the first gate oxide 315.

The inversion channel structure 320 includes at least one inversion cell structure, each of which includes a second well 321, a second ohmic contact 322, a second source 323, and a second gate structure.

In this embodiment, the second well 321 is located in the epitaxial layer 302 and has a second doping type, where the second doping type is opposite to the second doping type. A second ohmic contact region 322 is located in the second well region 321 having a second doping type. The second source region 323 is located in the second well region 321 and has a certain distance from an outer edge of the second well region 321, and has the first doping type. The second source region 323 is in contact with the second ohmic contact region 322. The second source region 323 and the second ohmic contact region 322 each extend from the surface of the second well region 321 toward the inside of the second well region 321. A second gate structure is located on the epitaxial layer 302 and covers the second well region 321 and a portion of the second source region 323.

The second gate structure includes a second gate oxide 325 and a second gate poly 326, the second gate oxide 325 is located on a portion of the epitaxial layer 302, a portion of the second well region 321, and a portion of the second source region 323, and the second gate poly 326 is located on the second gate oxide 325.

In a preferred embodiment, the power semiconductor device 300 further comprises JFET regions 305 located between adjacent well regions in the epitaxial layer 302.

The power semiconductor device 300 further includes a dielectric layer 303, a first source 317, a second source 327, and a drain 304.

A dielectric layer 303 is located on the epitaxial layer 302 and covers the surface of the first gate poly 316, the first gate oxide 315 and the sidewalls of the first gate poly 316, the surface of the second gate poly 326, and the sidewalls of the second gate oxide 325 and the second gate poly 326.

A first source 317 is located on the dielectric layer 303 and is connected to the first ohmic contact region 312 and the first source region 313; a second source 317 is located on the dielectric layer 303 and is connected to the second ohmic contact region 322 and the second source region 323; the drain 304 is located on the lower surface (the surface of the side away from the epitaxial layer 302) of the silicon carbide substrate 301. The drains of the accumulation mode channel structure 310 and the inversion mode channel structure 320 are in common. Dielectric layer 303 isolates first source 317 from the first gate structure and second source 327 from the second gate structure.

In this embodiment, the accumulation channel structure 310 is increased by only one accumulation channel layer 314 and the impurity concentration distribution of the two well regions is different from that of the inversion channel structure 320. The same portions of the accumulation mode channel structure 310 and the inversion mode channel structure 320 may be formed at the same time.

Referring to fig. 4, the abscissa is the junction depth, the junction depth is the direction from the surface of the well region to the epitaxial layer from left to right, the ordinate is the impurity concentration, wherein curve a is the impurity concentration distribution of the second well region 321, curve B is the impurity concentration distribution of the accumulation channel layer 314, and curve C is the impurity concentration distribution of the first well region 311. As can be seen from fig. 4, the impurity concentration in the second well region 321 increases and decreases with increasing junction depth; the impurity concentration in the accumulation channel layer 314 remains unchanged and decreases as the junction depth increases; the impurity concentration in the first well region 311 increases and then decreases as the junction depth increases. The doping concentrations of the first well region 311, the accumulation channel layer 314, and the second well region 321 are different, and the concentration of the accumulation channel layer 314 may be adjusted so that the threshold of the accumulation channel structure 310 is low.

The threshold (Vth) of the electrical parameter of the accumulation-mode channel structure 310 is lower than the threshold (Vth) of the electrical parameter of the inversion-mode channel structure 320, e.g., the threshold voltage of the accumulation-mode channel structure 310 is less than 1V and the threshold voltage of the inversion-mode channel structure 320 is greater than 1V.

The accumulation channel structure 310 operates on the principle that: because the accumulation channel layer 314 is formed on the surface of the first well region 311, when a small positive voltage (generally less than 1V) or zero voltage is applied between the first gate structure and the first source 317, a conductive channel can be formed, and when a voltage difference exists between the drain 304 and the first source 317, a current is formed, and the accumulation channel structure 310 is turned on; when a negative voltage is applied between the first gate structure and the first source 317, the channel is turned off and the accumulation channel structure 310 is turned off.

The inversion channel structure 320 operates on the principle that: applying a positive voltage between the second gate structure and the second source 327, which is greater than a threshold voltage (typically greater than 1V), inversely forming a conductive channel on the surface of the second well 321, and creating a current when a voltage difference exists between the drain 304 and the second source 327, the inversely formed channel structure 320 being conductive; when a positive voltage is applied between the second gate structure and the second source 327 and below a threshold voltage, the channel is turned off and the inversion channel structure 320 is turned off.

Isolation structure 330 is located between accumulation channel structure 310 and inversion channel structure 320 to isolate the two. The isolation structure 330 includes a third gate structure, a fourth gate structure, and a third well region 331, wherein the third well region 331 is located in the epitaxial layer 302 and between the third gate structure and the fourth gate structure, and the third well region 331 is floating; a third gate structure is located on the epitaxial layer 302, covering a portion of the third well region 331 and the accumulation channel layer 314 and a portion of the first source region 313 in the adjacent accumulation channel structure 310; the fourth gate structure is located on the epitaxial layer 302 and covers a portion of the third well region 331 and a portion of the second well region 321 and a portion of the second source region 323 in the adjacent inversion channel structure 320. The third gate structure is connected to the first source electrode 317; the fourth gate structure is connected to the second source 327; the junction depths of the first well region 311, the second well region 321 and the third well region 331 in the epitaxial layer 302 are the same. The third well region 331 in this embodiment floats, which means floating in the potential sense.

The third gate structure includes a first gate oxide 315 and a first gate poly 316, the first gate oxide 315 is located on a portion of the third well region 331, a portion of the epitaxial layer 302, an adjacent accumulation channel layer 314, and a portion of the first source region 313, and the first gate poly 316 is located on the first gate oxide 315. The fourth gate structure includes a second gate oxide layer 325 and a second gate poly 326, the second gate oxide layer 325 is located on a portion of the third well region 331, a portion of the epitaxial layer 302, an adjacent portion of the second well region 321, and a portion of the second source region 323, and the second gate poly 326 is located on the second gate oxide layer 325.

The third well region 331 and the second well region 321 may be identical or different, and are connected to the drain electrode 304 through the silicon carbide substrate 301.

When the semiconductor power device 300 works, the first gate polycrystal 316 and the second gate polycrystal 326 are mutually independent, and the isolation withstand voltage between the gates and the sources of the accumulation channel structure 310 and the inversion channel structure 320 is respectively determined by the withstand voltage of the first gate oxide layer 315 and the second gate oxide layer 325, which can reach more than 20V; because the first well region 311 and the second well region 321 are also independent of each other, the distance between the first well region 311 and the second well region 321 is increased by the third well region 331, so that the isolation withstand voltage between the accumulation channel structure 310 and the inversion channel structure 320 is greatly improved, that is, the isolation voltage between the first well region 311 and the second well region 321 can reach more than 40V, and the requirement of a switching power supply control system is completely met.

Referring to fig. 5a, a high voltage ring 340 having a second doping type is further provided at an edge region of the semiconductor power device 300. The high-voltage ring 340 is located around the edge of the semiconductor power device 300 and surrounds the accumulation-type channel structure 310, the inversion-type channel structure 320 and the isolation structure 330, so as to expand the depletion layer and relieve the electric field, so that the semiconductor power device 300 has higher reverse breakdown voltage and good reliability. It will be appreciated that the accumulation channel structure 310 and the inversion channel structure 320 can be sized and positioned according to the desired product, with the isolation structure 330 positioned therebetween to isolate the two. The S1 region and the S2 region are surface metals of the first source 317 and the second source 327, respectively. The G1 region and the G2 region are the surface metals of the first gate 318 and the second gate 328, respectively. The S1 region, S2 region, G1 region, and G2 region are regions where wires are routed when the semiconductor power device 300 is packaged.

In other embodiments, the semiconductor power device 300 may include at least one accumulation channel structure 310, at least one inversion channel structure 320, and at least one isolation structure 330. Specifically, as shown in fig. 5b, the semiconductor power device 300 includes two accumulation-type channel structures 310, one inversion-type channel structure 320, and two isolation structures 330, each isolation structure 330 separating adjacent accumulation-type channel structures 310 and inversion-type channel structures 320.

The power semiconductor device provided by the embodiment of the utility model adopts transistors with different channel types to be integrated together, has simple process and reduces the complexity and cost of the chip.

Fig. 6a to 6f show schematic cross-sectional views of a power semiconductor device according to a first embodiment of the present utility model at different stages of a method of manufacturing the same. The manufacturing method of the power semiconductor device comprises the following steps:

in step S01, an epitaxial layer 302 and JFET region 305 are formed on a silicon carbide substrate 301 (see fig. 6 a).

The method comprises the following specific steps: forming an epitaxial layer 302 on the silicon carbide substrate 301, the silicon carbide substrate 301 and the epitaxial layer 302 each having a first doping type; silicon dioxide or polysilicon or a multilayer structure of silicon dioxide and polysilicon is deposited on the epitaxial layer 302 to form a first hard mask material (not shown), which is then subjected to photolithography and etching to form a first hard mask, and first doping type impurities are implanted to form the JFET region 305.

In this embodiment, the doping concentration of the epitaxial layer 302 is selected according to the withstand voltage of the power semiconductor device.

In this embodiment, the epitaxial layer 302 is formed by multiple epitaxial growth and selective implantation of ions of a second conductivity type (e.g., al ions).

In step S02, a first well region 311, a second well region 321, and a third well region 331 are formed in the epitaxial layer 302 (see fig. 6 b).

In this embodiment, the first hard mask is removed, a second hard mask material is deposited and formed, the second hard mask 306 is formed by photolithography and etching, and the first well region 311, the second well region 321 and the third well region 331 are formed by implanting impurities of the second doping type. The first well region 311, the second well region 321, and the third well region 331 each have a second doping type, and are formed by implanting a plurality of impurity implants of the second doping type with different energies and doses. The different doping concentrations of the first well region 311 in the accumulation channel structure 310 and the second well region 321 in the inversion channel structure 320 may be formed by two sets of completely different second doping type impurity implants.

In a preferred embodiment, the first well region 311 in the accumulation-type channel structure 310 and the second well region 321 in the inversion-type channel structure 320 are formed by simultaneous implantation. The second well region 321 in the inversion channel structure 320 is formed by a set of multiple second doping type impurity implants, and the first well region 311 in the accumulation channel structure 310 is formed by only a certain number of the set of multiple second doping type impurity implants, thereby forming the accumulation channel layer 314 of the first doping type at the surface of the first well region 311. Preferably, the doping of the third well region 331 of the isolation structure 330 and the second well region 321 in the inversion channel structure 320 is the same.

In step S03, a first source region 313 and a second source region 323 are formed in the first well region 311 and the second well region 321, respectively (see fig. 6 c).

In this embodiment, the second hard mask 306 is removed, a third hard mask material is deposited and formed, the third hard mask 307 is formed by photolithography and etching, and the first doping type impurities are respectively implanted into the first well region 311 and the second well region 321, thereby forming the first source region 313 and the second source region 323. The first source region 313 and the second source region 323 each have a first doping type.

In step S04, a first ohmic contact region 312 and a second ohmic contact region 322 are formed in the first well region 311 and the second well region 321, respectively (see fig. 6 d).

In this embodiment, the third hard mask 307 is removed, a fourth hard mask material is deposited and formed, the fourth hard mask 308 is formed by photolithography and etching, and the second doping type impurities are respectively implanted into the first well region 311 and the second well region 321, thereby forming the first ohmic contact region 312 and the second ohmic contact region 322. The fourth hard mask 308 is then removed and the implanted defects are fully repaired and the implanted impurities activated by an annealing process at a high temperature of 1600-1700 c. The first source region 313 is located on the surface of the first well region 311 at a distance from the outer edge of the first well region 311 and contacts the first ohmic contact region 312. The second source region 323 is located on the surface of the second well region 321 with a certain distance from the outer edge of the second well region 321 and contacts the second ohmic contact region 322.

In a preferred embodiment, a high voltage ring (not shown) is formed at the edge of the power semiconductor device 300, and surrounds the accumulation type channel structure 310, the inversion type channel structure 320 and the isolation structure 330, so as to expand the depletion layer and relieve the electric field, so that the semiconductor power device 300 has a high reverse breakdown voltage and good reliability. The high voltage ring is preferably formed simultaneously with the first ohmic contact region 312 and the second ohmic contact region 322, the high voltage ring having the second doping type.

In step S05, a first gate structure, a second gate structure, a third gate structure and a fourth gate structure are formed on the epitaxial layer 302 (see fig. 6 e).

In this embodiment, after cleaning, deposition

Is not shown in the figures). And photoetching and etching field oxide to form an active region. After cleaningGrowth or deposition->

Etching the silicon dioxide to form a gate oxide layer; and depositing and etching polysilicon to form gate polycrystal, so as to form a first gate structure of an accumulation type channel structure, a second gate structure of an inversion type channel structure, a third gate structure and a fourth gate structure of an isolation structure.

Wherein a first gate structure is located on the epitaxial layer 302 and covers the accumulation channel layer 314 and a portion of the first source region 313. The first gate structure includes a first gate oxide 315 and a first gate poly 316, the first gate oxide 315 being located on a portion of the epitaxial layer 302, the accumulation channel layer 314, and a portion of the first source region 313, the first gate poly 316 being located on the first gate oxide 315.

A second gate structure is located on the epitaxial layer 302 and covers a portion of the second well region 321 and a portion of the second source region 323. The second gate structure includes a second gate oxide 325 and a second gate poly 326, the second gate oxide 325 is located on a portion of the epitaxial layer 302, a portion of the second well region 321, and a portion of the second source region 323, and the second gate poly 326 is located on the second gate oxide 325.

A third gate structure is located on the epitaxial layer 302 and covers a portion of the third well region 331, the adjacent accumulation channel layer 314 and a portion of the first source region 313; the fourth gate structure is located on the epitaxial layer 302 and covers a part of the third well region 331, an adjacent part of the second well region 321 and a part of the second source region 323; a third well region 331 is located in the epitaxial layer 302 and between the third gate structure and the fourth gate structure, the third well region 331 being floating.

In step S06, the dielectric layer 303, the gate electrode (not shown in the drawing), the first source electrode 317, the second source electrode 327, and the drain electrode 304 are formed (see fig. 6 f).

In this embodiment, the dielectric layer 303 is covered on the first gate structure and the second gate structure, and the third gate structure and the fourth gate structure, and the lead hole is formed by photolithography and etching, and the ohmic contact is formed by depositing metal; the etched metal forms a gate electrode (not shown), a first source 317, a second source 327, wherein the first source 317 is connected to a first source region 313 in the accumulation channel structure 310 and the second source 327 is connected to a second source region 323 in the inversion channel structure 320; the third gate structure is connected to the first source electrode 317; the fourth gate structure is connected to the second source 327.

A drain 304 of the power semiconductor device is formed by depositing metal on the lower surface (the surface of the side remote from the epitaxial layer 302) of the silicon carbide substrate 301.

The material of the dielectric layer 303 may be silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, etc.

The manufacturing method of the power semiconductor device provided by the embodiment of the utility model adopts the transistors with different channel types to be integrated together, has simple process and reduces the complexity and cost of the chip.

Fig. 7 shows a schematic cross-sectional view of a power semiconductor device provided by a third embodiment of the present utility model. In comparison with the first embodiment, the isolation structure 430 includes a third gate structure, a fourth gate structure, and a first doped region 431.

Wherein a third gate structure is located on the epitaxial layer 402 and covers a portion of the first doped region 431, the adjacent accumulation channel layer 414 and a portion of the first source region 413; the fourth gate structure is located on the epitaxial layer 402 and covers a portion of the first doped region 431, an adjacent portion of the second well region 421 and a portion of the second source region 423; the first doped region 431 is located in the epitaxial layer 402 and between the third gate structure and the fourth gate structure, and the first doped region 431 is floating.

In this embodiment, the third gate structure is connected to the first source 417; the fourth gate structure is connected to the second source 427.

The junction depth of the first doped region 431 in the epitaxial layer 402 is different from the junction depths of the first well region 411 and the second well region 421 in the epitaxial layer 402.

The first doped region 431 has a second doping type, the first doped region 431 and the first well region 411 and the second well region 421 are not formed by simultaneous implantation, but are formed by separate implantation, and different isolation voltages can be realized by adjusting the ion implantation depth of the first doped region 431 to obtain first doped regions 431 with different junction depths.

The remaining aspects of the present embodiment are the same as those of the first embodiment, and will not be described again here.

Fig. 8 shows a schematic cross-sectional view of a power semiconductor device provided by a fourth embodiment of the present utility model. Compared to the first embodiment, the isolation structure 530 includes a first field oxide layer 532, a second field oxide layer 533, and a second doped region 531.

Wherein the first field oxide layer 532 covers part of the second doped region 531, part of the accumulation channel layer 514 of the adjacent accumulation channel structure 510 and part of the first source region 513, and the second field oxide layer 533 covers part of the second doped region 531, part of the second well region 521 of the adjacent inversion channel structure 520 and part of the second source region 523.

The second doped region 531 is located in the epitaxial layer 502 between the first field oxide layer 532 and the second field oxide layer 533, and the second doped region 531 is floating.

The junction depth of the second doped region 531 in the epitaxial layer 502 is the same as or different from the junction depths of the first well region 511 and the second well region 521 in the epitaxial layer 502.

The second doped region 531 has a second doping type, and the second doped region 531, the first well region 511 and the second well region 521 may be formed by simultaneous implantation, or may be formed by separate implantation, and the second doped region 531 with different junction depths may be obtained by adjusting the ion implantation depth of the second doped region 531, so as to achieve different isolation voltages.

Fig. 9 shows a schematic cross-sectional view of a power semiconductor device provided by a fifth embodiment of the present utility model. In comparison to the first embodiment, the isolation structure 630 includes a third gate structure, a fourth gate structure, and a third doped region 631.

Wherein a third gate structure is located on the epitaxial layer 602, covering a portion of the third doped region 631, the adjacent accumulation channel layer 614 and a portion of the first source region 613; the fourth gate structure is located on the epitaxial layer 402 and covers a part of the third doped region 631, an adjacent part of the second well region 621 and a part of the second source region 623; a third doped region 631 is located in the epitaxial layer 602 and between the third gate structure and the fourth gate structure, the third doped region 631 being floating.

In this embodiment, the third gate structure is connected to the first source 617; the fourth gate structure is connected with the second gate structure.

The junction depth of the third doped region 631 in the epitaxial layer 602 is the same as or different from the junction depth of the first well region 611 and the second well region 621 in the epitaxial layer 602.

The third doped region 631 has the second doping type, the third doped region 631 and the first well region 611 and the second well region 621 may be formed by simultaneous implantation, or may be formed by separate implantation, and different isolation voltages may be achieved by adjusting the ion implantation depth of the third doped region 631 to obtain the third doped region 631 with different junction depths.

Fig. 10 shows a schematic cross-sectional view of a power semiconductor device provided by a sixth embodiment of the present utility model. Compared with the first embodiment, the gate structures of the accumulation-type channel structure and the inversion-type channel structure both adopt trench-type gate structures.

In this embodiment, the accumulation-mode channel structure 710 includes at least one accumulation-mode cell structure, and each accumulation-mode cell structure includes a first trench, a first gate structure, a first well region 711, a first source region 713, a first ohmic contact region 712, and an accumulation channel layer 714.

Wherein a first trench is located in the epitaxial layer 702, extending from a surface of the epitaxial layer 702 into the epitaxial layer 702. A first gate structure is located within the first trench.

The first gate structure includes a first gate oxide layer 715 and a first gate poly 716, the first gate oxide layer 715 covers an inner wall of the first trench, and the first gate poly 716 is located on the first gate oxide layer 715.

A first well region 711 is located in the epitaxial layer 702, on both sides of the first trench, having a second doping type. A first source region 713 is located in the first well region 711 and extends from the surface of the first well region 711 towards the inside of the first well region 711, having a first doping type. The first ohmic contact region 712 is located on the surface of the first well region 711 between the adjacent first trenches and has a certain distance from the adjacent first trenches, has the second doping type, and is in contact with the first source region 713. An accumulation channel layer 714 is located in the first well region 711 below the first source region 713 and on both sides of the first trench, having a first doping type.

In this embodiment, the inversion channel structure 720 includes at least one inversion cell structure, each of which includes a second trench, a second gate structure, a second well region 721, a second source region 723, and a second ohmic contact region 722.

Wherein a second trench is located in the epitaxial layer 702, extending from the surface of the epitaxial layer 702 into the epitaxial layer 702; a second gate structure is located within the second trench.

The second gate structure includes a second gate oxide 725 and a second gate poly 726, the second gate oxide 725 covers an inner wall of the second trench, and the second gate poly 726 is located on the second gate oxide 725.

A second well region 721 is located in the epitaxial layer 702, on both sides of the second trench, having a second doping type. The second source region 723 is located in the second well region 721 and extends from the surface of the second well region 721 toward the inside of the second well region 721, having the first doping type. A second ohmic contact region 722 is located on the surface of the second well region 721 between the adjacent second trenches and has a certain distance from the adjacent second trenches, and has a second doping type, and the second ohmic contact region 722 is in contact with the second source region 723.

A dielectric layer 703 is located on the epitaxial layer 702 and covers a portion of the first source region 713, the first gate structure, and a portion of the second source region 723 and the second gate structure. A first source 717 is located on the dielectric layer 703 and connected to the first ohmic contact region 712 and the first source region 713; a second source 727 is located on the dielectric layer 703 and is connected to the second ohmic contact region 722 and the second source region 723.

The isolation structure 730 includes a third gate structure, a fourth gate structure, and a fourth doped region 731. Wherein the third gate structure is located in the third trench in the epitaxial layer 702 and is respectively in contact with the fourth doped region 731 and the adjacent first source region 713 and the accumulation channel layer 714; the fourth gate structure is located in a fourth trench in the epitaxial layer 702 and is in contact with the fourth doped region 731 and the adjacent second well region 721 and second source region 723, respectively.

A fourth doped region 731 is in the epitaxial layer 702 and between the third gate structure and the fourth gate structure, the fourth doped region 731 being floating. Wherein the third gate structure is connected to the first source 717; the fourth gate structure is connected to the second source 727.

The junction depth of the fourth doped region 731 in the epitaxial layer 702 is the same or different from the junction depth of the first well region 711 and the second well region 721 in the epitaxial layer 702.

The fourth doped region 731 has the second doping type, and the fourth doped region 731 and the first well region 711 and the second well region 721 may be formed by simultaneous implantation or may be formed by separate implantation, and the ion implantation depth of the fourth doped region 731 may be adjusted to obtain fourth doped regions 731 with different junction depths, thereby realizing different isolation voltages.

Embodiments in accordance with the present utility model, as described above, are not intended to be exhaustive or to limit the utility model to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model and various modifications as are suited to the particular use contemplated. The utility model is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A power semiconductor device, comprising:

a silicon carbide substrate having a first doping type;

an epitaxial layer on the silicon carbide substrate having a first doping type;

an accumulation-type channel structure and an inversion-type channel structure, wherein the accumulation-type channel structure and the inversion-type channel structure are arranged at intervals, part of the accumulation-type channel structure and the inversion-type channel structure are positioned in the epitaxial layer, and part of the accumulation-type channel structure and the inversion-type channel structure are positioned on the epitaxial layer;

And an isolation structure isolating the accumulation-type channel structure and the inversion-type channel structure from each other so that the accumulation-type channel structure and the inversion-type channel structure are arranged at intervals.

2. The power semiconductor device of claim 1, wherein the accumulation-type channel structure comprises at least one accumulation-type cell structure, each accumulation-type cell structure comprising:

the first well region is positioned in the epitaxial layer and is provided with a second doping type;

an accumulation channel layer, which is positioned on the surface of the first well region and has a first doping type;

a first ohmic contact region in the first well region and extending from a surface of the first well region toward an interior of the first well region, the first ohmic contact region having a second doping type;

the first source region is positioned on the surface of the first well region, has a certain distance from the outer edge of the first well region, has a first doping type and is in contact with the first ohmic contact region;

and the first grid structure is positioned on the epitaxial layer and covers the accumulation channel layer and part of the first source region.

3. The power semiconductor device of claim 2, wherein the inversion channel structure comprises at least one inversion cell structure, each inversion cell structure comprising:

The second well region is positioned in the epitaxial layer and is provided with a second doping type;

a second ohmic contact region in the second well region and extending from a surface of the second well region toward an interior of the second well region, the second ohmic contact region having a second doping type;

the second source region is positioned on the surface of the second well region and has a certain distance from the outer edge of the second well region, has a first doping type and is in contact with the second ohmic contact region;

and the second grid structure is positioned on the epitaxial layer and covers part of the second well region and part of the second source region.

4. The power semiconductor device of claim 3, wherein the first gate structure comprises a first gate oxide layer and a first gate poly, the first gate oxide layer being located on a portion of the epitaxial layer, the accumulation channel layer, and a portion of the first source region, the first gate poly being located on the first gate oxide layer;

the second gate structure comprises a second gate oxide layer and a second gate polycrystal, the second gate oxide layer is located on a part of the epitaxial layer, a part of the second well region and a part of the second source region, and the second gate polycrystal is located on the second gate oxide layer.

5. The power semiconductor device of claim 4, further comprising:

the dielectric layer is positioned on the epitaxial layer and covers the surface of the first gate polycrystal, the first gate oxide layer and the side wall of the first gate polycrystal, the surface of the second gate polycrystal and the side wall of the second gate oxide layer and the side wall of the second gate polycrystal;

the first source electrode is positioned on the dielectric layer and connected with the first ohmic contact area and the first source area;

the second source electrode is positioned on the dielectric layer and connected with the second ohmic contact region and the second source region;

a drain electrode located on a surface of the silicon carbide substrate remote from the epitaxial layer;

wherein the drain of the accumulation-mode channel structure and the drain of the inversion-mode channel structure are common.

6. The power semiconductor device of claim 5, wherein the isolation structure comprises:

a third well region located in the epitaxial layer;

a third gate structure on the epitaxial layer covering a portion of the third well region and adjacent the accumulation channel layer and a portion of the first source region;

the fourth grid structure is positioned on the epitaxial layer and covers part of the third well region, part of the second well region and part of the second source region which are adjacent to the third well region;

Wherein the third well region is positioned between the third gate structure and the fourth gate structure, and the third well region floats; the third grid structure is connected with the first source electrode; the fourth grid structure is connected with the second source electrode; the junction depths of the first well region, the second well region and the third well region in the epitaxial layer are the same.

7. The power semiconductor device of claim 5, wherein the isolation structure comprises:

a first doped region in the epitaxial layer;

a third gate structure on the epitaxial layer covering a portion of the first doped region and adjacent the accumulation channel layer and a portion of the first source region;

the fourth grid structure is positioned on the epitaxial layer and covers part of the first doped region, part of the second well region and part of the second source region which are adjacent to the first doped region;

wherein the first doped region is located between the third gate structure and the fourth gate structure, and the first doped region floats; the third grid structure is connected with the first source electrode; the fourth grid structure is connected with the second source electrode; the junction depth of the first doped region in the epitaxial layer is different from the junction depths of the first well region and the second well region in the epitaxial layer.

8. The power semiconductor device of claim 5, wherein the isolation structure comprises:

a second doped region in the epitaxial layer;

a first field oxide layer and a second field oxide layer on the epitaxial layer, wherein the first field oxide layer covers part of the second doped region and part of the second well region and part of the second source region of the adjacent accumulation channel structure;

the second doped region is positioned between the first field oxide layer and the second field oxide layer, and the second doped region floats; the junction depth of the second doped region in the epitaxial layer is the same as or different from the junction depths of the first well region and the second well region in the epitaxial layer.

9. The power semiconductor device of claim 5, wherein the isolation structure comprises:

a third doped region in the epitaxial layer;

a third gate structure on the epitaxial layer covering a portion of the third doped region and adjacent the accumulation channel layer and a portion of the first source region;

The fourth grid structure is positioned on the epitaxial layer and covers part of the third doped region, part of the second well region and part of the second source region which are adjacent to the third doped region;

wherein the third doped region is located between the third gate structure and the fourth gate structure, and the third doped region is floating; the third grid structure is connected with the first source electrode; the fourth grid structure is connected with the second grid structure;

wherein the junction depth of the third doped region in the epitaxial layer is the same as or different from the junction depths of the first well region and the second well region in the epitaxial layer.

10. The power semiconductor device of claim 1, wherein the accumulation-type channel structure comprises at least one accumulation-type cell structure, each accumulation-type cell structure comprising:

a first trench in the epitaxial layer extending from a surface of the epitaxial layer into the epitaxial layer;

a first gate structure located within the first trench;

the first well region is positioned in the epitaxial layer, positioned at two sides of the first groove and provided with a second doping type;

a first source region located in the first well region and extending from a surface of the first well region toward an interior of the first well region, having a first doping type;

The first ohmic contact region is positioned on the surface of the first well region between the adjacent first grooves, has a certain distance from the adjacent first grooves, has a second doping type and is in contact with the first source region;

and an accumulation channel layer which is positioned in the first well region below the first source region and positioned at two sides of the first groove and has a first doping type.

11. The power semiconductor device of claim 10, wherein the inversion channel structure comprises at least one inversion cell structure, each inversion cell structure comprising:

a second trench in the epitaxial layer extending from a surface of the epitaxial layer into the epitaxial layer;

a second gate structure located within the second trench;

the second well region is positioned in the epitaxial layer, positioned at two sides of the second groove and provided with a second doping type;

a second source region located in the second well region and extending from a surface of the second well region toward an interior of the second well region, having a first doping type;

and the second ohmic contact region is positioned on the surface of the second well region between the adjacent second trenches and has a certain distance from the adjacent second trenches, has a second doping type and is in contact with the second source region.

12. The power semiconductor device of claim 11, wherein the first gate structure comprises a first gate oxide layer and a first gate poly, the first gate oxide layer covering an inner wall of the first trench, the first gate poly being located on the first gate oxide layer;

the second gate structure comprises a second gate oxide layer and a second gate polycrystal, the second gate oxide layer covers the inner wall of the second groove, and the second gate polycrystal is located on the second gate oxide layer.

13. The power semiconductor device of claim 12, further comprising:

the dielectric layer is positioned on the epitaxial layer and covers part of the first source region, the first grid structure, part of the second source region and the second grid structure;

a first source electrode on the dielectric layer and connected to the first ohmic contact region and the first source region,

14. The power semiconductor device of claim 13, wherein the isolation structure comprises:

a fourth doped region located in the epitaxial layer;

a third gate structure located in the first trench in the epitaxial layer and in contact with the fourth doped region and the adjacent first source region and accumulation channel layer;

a fourth gate structure located in the second trench in the epitaxial layer and in contact with the fourth doped region and the adjacent second well region and second source region;

the fourth doped region is positioned between the third gate structure and the fourth gate structure, and the fourth doped region floats; the third grid structure is connected with the first source electrode; the fourth grid structure is connected with the second source electrode;

and the junction depth of the fourth doped region in the epitaxial layer is the same as or different from the junction depth of the first well region and the second well region in the epitaxial layer.

15. The power semiconductor device of claim 1, wherein the threshold value of the electrical parameter of the accumulation channel structure is lower than the threshold value of the electrical parameter of the inversion channel structure.

16. The power semiconductor device of claim 1, further comprising:

And the high-voltage ring is positioned at the edge of the power semiconductor device, surrounds the accumulation type channel structure, the inversion type channel structure and the isolation structure and has a second doping type.

17. The power semiconductor device of claim 1, wherein the power semiconductor device is a MOS device or an IGBT device.

18. The power semiconductor device of claim 1, wherein the power semiconductor device comprises at least one accumulation channel structure, at least one inversion channel structure, and at least one isolation structure.

19. A switching power supply, comprising:

the voltage stabilizing circuit is used for converting the high-voltage power supply into working voltage;

the driving control circuit is connected with the voltage stabilizing circuit and used for generating a driving signal and a control signal according to the working voltage;

the high-voltage power device is connected with the drive control circuit and is used for being turned on and off according to the drive signal;

the high-voltage power device comprises a first transistor, the structure of the high-voltage power device is an inverse channel structure, the voltage stabilizing circuit comprises a second transistor, the structure of the voltage stabilizing circuit is an accumulation channel structure, the voltage stabilizing circuit and the high-voltage power device are integrated on the same substrate to form a power semiconductor device, and the structure of the power semiconductor device is as claimed in any one of claims 1-18.

20. The switching power supply of claim 19 wherein a first terminal of the first transistor is connected to a high voltage power supply, a second terminal of the first transistor is connected to a reference ground, and a control terminal of the first transistor is connected to a drive terminal of a drive control circuit to receive the drive signal; the first end of the second transistor is connected with the high-voltage power supply, the second end of the second transistor is connected with the power supply end of the drive control circuit, the working voltage is provided for the drive control circuit, and the control end of the second transistor is connected with the control end of the drive control circuit;

when the switching power supply is just started, the control end and the power supply end of the driving control circuit are both in zero potential, the second transistor is conducted, working voltage is provided for the driving control circuit to enable the driving control circuit to work, and a driving signal output by the driving control circuit controls the first transistor to be conducted;

after the starting stage of the switching power supply is completed, the driving control circuit sets the control end of the second transistor to zero potential through the control end of the driving control circuit to turn off the second transistor, and when the potential of the power end of the driving control circuit drops to a certain level, the driving signal output by the driving end of the driving control circuit controls the first transistor to turn off.