CN219123213U - Semiconductor package device - Google Patents

Abstract

The embodiment of the utility model discloses a semiconductor packaging device, relates to the technical field of semiconductors, and is convenient for reducing power consumption loss on a power supply link. Comprising the following steps: packaging a substrate; the packaging substrate is provided with an interconnection wire and a rewiring layer substrate; the rewiring layer substrate is arranged on the packaging substrate; a die unit; a part of the die unit is connected to the rewiring layer substrate, and the other part of the die unit is connected to the packaging substrate; a power module; the power module is positioned at the periphery of the grain unit and is electrically connected with the grain unit through the interconnection wire. The utility model is suitable for the packaging scenes of devices such as chips and the like.

Description

Semiconductor package device

Technical Field

The present utility model relates to the field of semiconductor technology, and in particular, to a semiconductor package device.

Background

Currently, semiconductor devices that perform high-density inter-Die (Die), also referred to as wafer, interconnection for Fan-out (Fan out) packaging processes are typically high-performance high-power chips. On one hand, the chip needs low-voltage power supply because of small process and low pressure resistance; on one hand, the chip needs large current due to performance requirements; for this reason, a large low-voltage current is supplied through an external power module, and a large amount of power consumption is lost on a link.

Disclosure of Invention

In view of the above, the embodiments of the present utility model provide a semiconductor package device, which is convenient for reducing the power consumption loss on the power supply link.

In order to achieve the aim of the utility model, the following technical scheme is adopted:

according to a first aspect of an embodiment of the present utility model, there is provided a semiconductor package device including: packaging a substrate; the packaging substrate is provided with an interconnection wire; a rewiring layer substrate; the rewiring layer substrate is arranged on the packaging substrate; a die unit; a part of the die unit is connected to the rewiring layer substrate, and the other part of the die unit is connected to the packaging substrate; a power module; the power module is positioned at the periphery of the grain unit and is electrically connected with the grain unit through the interconnection wire.

Optionally, at least one of the power modules is used for installing a heat dissipation module.

Optionally, the power module includes: and the power supply circuit is packaged in the shell.

Optionally, one or more power modules are provided.

Optionally, the power module includes: the circuit comprises a printed circuit board, a switch driving circuit, an inductor and a capacitor, wherein the switch driving circuit, the inductor and the capacitor are respectively and electrically connected to the printed circuit board, the output end of the switch driving circuit is electrically connected with the input end of the inductor, the output end of the inductor is electrically connected with the input end of the capacitor, and the output end of the capacitor is electrically connected to a power supply pin of the grain unit.

Optionally, the power module further includes: and the decoupling capacitor is arranged on a node between the output end of the capacitor and the power supply pin of the grain unit.

Optionally, a metal layer is plated on at least a surface of the housing, corresponding to the heat sink, of the power module exterior package.

Optionally, the die unit includes: a first die and a second die;

the packaging substrate is provided with a rewiring layer substrate, a first part of the first crystal grain and a first part of the second crystal grain are respectively and electrically connected to the rewiring layer substrate, a second part of the first crystal grain and a second part of the second crystal grain are respectively and electrically connected to the packaging substrate, the first crystal grain and the second crystal grain are arranged at intervals, and the first crystal grain and the second crystal grain are connected through an interconnection line on the rewiring layer substrate.

Optionally, the first die and the second die are arranged at intervals side by side, and the first die and the second die are respectively arranged at two sides of a first center line of the rerouting layer substrate, and when the rerouting layer substrate is rectangular, the first center line is a center line of a long side of the rerouting layer substrate.

Optionally, at least a part of the structure of the rerouting layer substrate is embedded on the packaging substrate, and the top of the rerouting layer substrate is exposed.

Optionally, the package substrate has at least one accommodating cavity, at least one accommodating cavity exposes at least one surface of the package substrate, and the redistribution layer substrate is disposed in the accommodating cavity and is located on the surface.

Optionally, when the upper parts of the power module and the die unit support and are provided with the heat dissipation module, the heat dissipation surfaces of the heat dissipation module are respectively contacted with the tops of the power module and the die unit.

Optionally, the semiconductor package device is a chip.

Drawings

In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a semiconductor package according to an embodiment of the present utility model;

FIG. 2 is a top view of one embodiment of the semiconductor package of FIG. 1;

FIG. 3 is a schematic diagram illustrating a power module in a semiconductor package according to an embodiment of the present utility model;

FIG. 4 is a schematic diagram of a semiconductor package according to another embodiment of the present utility model;

fig. 5 is a schematic structural view of another embodiment of the semiconductor package device of the present utility model

FIG. 6 is a schematic circuit topology of a power module according to another embodiment of the present utility model;

FIG. 7 is a schematic diagram illustrating a redistribution layer formation stage of a semiconductor package according to an embodiment of the present utility model;

FIG. 8 is a schematic diagram of an embodiment of one or more stages in a semiconductor package formation process in accordance with an embodiment of the present utility model;

FIG. 9 is a process flow diagram of a semiconductor packaging method according to an embodiment of the utility model;

fig. 10 is a schematic structural diagram of an embodiment of one or more stages in a power module formation process in a semiconductor package device according to the present utility model.

Detailed Description

Embodiments of the present utility model will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Example 1

FIG. 1 is a schematic diagram of a semiconductor package according to an embodiment of the present utility model; referring to fig. 1, the semiconductor package device provided in the embodiment of the present utility model may be applied to a package scene of an electronic device, and may be specifically applied to a package of a chip, etc., including: a package substrate 100; the package substrate 100 has interconnection wires thereon;

a rewiring Layer substrate (RDL, reDistribution Layer) 200; the redistribution layer substrate is disposed on the package substrate 100; the redistribution layer substrate 200, which plays a role of XY plane electrical extension and interconnection, is currently used in Fan-out package (Fan-out package) structure, mainly for realizing interconnection between high-density dies (Die).

The basis of the improvement innovation in the present application is the improvement of chips based on fan-out package structure, and a brief introduction of fan-out package is inserted here to help understanding: as with many concepts in the semiconductor arts, fan-out packages have broad and narrow meanings, and this application primarily describes a narrow fan-out package. Fan-out packages have been developed to accommodate the high performance development requirements of chips, which are essentially pursuing chip I/O density. The fan-out package supports the multi-Die package by interconnecting the Die units on the RDL substrate (sometimes also referred to as RDL) with higher wiring density, so that the original single Die can be changed into multiple dies, and the multiple dies can realize communication among multiple dies in the same package without relying on the package substrate for interconnection communication, but relying on the RDL substrate.

It should be noted that, the fan-out package may have various modifications according to the layout of the RDL, but the essence is that at least one RDL substrate is required, and at least a portion of Die needs to be interconnected to the RDL substrate, and the description of the layout of the RDL substrate will be further developed, and more details will be required, and reference will be made to the description of the relevant portions below.

A die unit 120; a part of the die unit 120 is connected to the redistribution layer substrate 200, another part of the die unit 120 is connected to the package substrate 100, and the signal leads and the power leads to be led out are led out of the package substrate 100, so that after packaging, related signals can be transferred and exchanged with external devices.

The power supply module is used for supplying power to the die unit and other power consumption elements; the power module is positioned at the periphery of the grain unit and is electrically connected with the grain unit through the interconnection wire.

The package Substrate 100 (SUB) can provide functions of electrical connection, protection, support, heat dissipation, assembly, etc. for the chip as required, so as to achieve the purposes of multi-pin, reduced package product volume, improved electrical performance and heat dissipation, ultra-high density, or multi-chip modularization. The package substrate 100 may be made of an organic material or an inorganic material, depending on the materials used.

The types of the above-mentioned substrates may be classified into flexible thin film substrates, hard substrates, and the like according to the materials of the package substrate 100, and the specific type of the substrate selected as the package substrate 100 may be considered according to environmental factors such as temperature, operating frequency, and the like of the semiconductor package device application, in combination with the dimensional stability, high frequency characteristics, heat resistance, thermal conductivity, and the like of the substrates of different materials.

With continued reference to fig. 1, it can be appreciated that, in order to interconnect the die unit 120 with the package substrate 100, through-silicon vias (TSVs, through Silicon Via) 101a and 101b are formed on the package substrate 100, wherein vertical electrical interconnection of the through-silicon vias is achieved by filling with a conductive substance. Through the silicon through hole interconnection mode, the interconnection length can be reduced through vertical interconnection, signal delay is reduced, capacitance/inductance is reduced, low power consumption and high-speed communication among chips are realized, broadband is increased, and miniaturization of device integration is realized.

In some embodiments, the package substrate 100 is a hard package substrate, and may be a substrate made of BT material, ABF material, or MIS material. The package substrate 100 is preferably a resin substrate, that is, an ABF substrate (Ajinomoto Build-up Film substrate), which can make IC (Integrate circuit) thinner, more pins, and higher transmission rate.

In the related art, the power module 140 is generally disposed outside the package substrate 100, for example, on a printed circuit board (PCB, printed circuit board), and since the low-voltage high-current power supply transmission path is generally adopted outside the package substrate 100, the low-voltage high-current power supply transmission path is then transferred to the package substrate 100 to be converted into high-voltage low-current for supplying power to the chip, a large amount of loss is generated on the external high-current power supply link.

In this embodiment, by integrating the power module 140 and the die unit 120 together on the package substrate 100, a high voltage low current can be input from the outside, typically about 12 v or 48 v, and the current is about tens of amperes, and the power supply link from the power module 140 to the die unit 120 is greatly shortened, so that the power consumption loss on the power supply link can be reduced.

It will be appreciated that heat is generated during use of the chip, and therefore, in order to ensure heat dissipation, a heat sink is typically provided outside the chip.

In some embodiments, at least one of the power modules 140 is configured to mount a heat dissipation module (the heat dissipation module is generally a part other than the package device, and may be regarded as an environmental feature defined in the patent, and is not illustrated in the drawings).

In fig. 1, one or more power modules 140 may be provided according to the power supply requirement, or may be provided in combination with the supporting heat conducting member 160.

In order to facilitate understanding of the technical effects of the structural arrangement of the present embodiment, the following description is made on the related art: in the current chip package heat dissipation scheme, because the power consumption of the chip is large, an external heat sink is generally used for heat dissipation, and in order to ensure the heat dissipation effect, a metal Ring (Ring) or a metal Cover (Cover) or the like is generally required to be disposed on the package substrate 100 to support the heat conducting element 160, so as to contact with the external heat sink to assist in heat dissipation protection. However, such a special arrangement of the supporting heat conducting element increases the area occupied by the package substrate 100; alternatively, the original supporting heat conducting element 160 is reserved, and the power module 140 is added, which certainly increases the area of the package substrate 100.

Therefore, in the present embodiment, the power module 140 is used as the supporting and heat conducting element of the heat sink while the power module 140 achieves the intended power supply purpose, and the heat sink is disposed on the power module 140, so that the heat dissipation supporting and the power supply can be combined into one, the power module 140 is prevented from occupying the additional area of the package substrate 100, and the area of the package substrate 100 is saved.

Further, the power module 140 is used for supporting the heat sink in place of the supporting heat conducting member 160, and the heat sink arranged thereon can be used for radiating power consumption elements such as driving and switching tube chips and inductors inside the power module 140 in turn, so that the cost of adding an additional heat sink can be avoided, and the cost of the semiconductor packaging device can be reduced to a certain extent.

Referring to fig. 3, in some implementations, the power module 140 includes: the power circuit is encapsulated in the housing 141, so as to increase the supporting strength of the power module 140 and improve the stability of the heat sink arranged at the top of the power module 140.

The power module 140 may be packaged in a plastic package manner, or a glass package manner, a partial metal package manner, or the like, to implement package reinforcement of the power module 140.

In order to further improve the supporting strength and the heat dissipation effect, specifically, a metal layer is plated on at least the surface (generally, the upper surface, of course, may be changed according to the orientation of the heat sink) corresponding to the heat sink, of the housing 141 packaged outside the power module 140. The heat dissipation performance of the metal is better, so that the heat dissipation effect of the semiconductor packaging device is improved conveniently.

For better heat conduction, in some embodiments, it is preferable to perform an electroplating process on the surface of the power module 140, such as gold, silver, copper, or an alloy.

Referring to fig. 1, 4 and 5, the power module 140 may be provided with one or more. According to the current value provided by the power module 140, when the current has satisfied the power supply requirement of the package substrate 100, the supporting heat conducting member 160 such as stainless steel or copper supporting sheet may be used to replace the power module 140, i.e. the number of the power modules 140 may be reduced appropriately, and the power module 140 and the supporting heat conducting element may be mixed for use.

In addition, if multiple voltage demands exist, different power supply modules can be used for combination, so that power supply with different power supply voltages can be realized; if the individual module current is insufficient, the current supply may be increased in parallel to meet the power requirements of die unit 120 and other power devices.

Referring to fig. 1, in some embodiments, the power module 140 includes: the circuit comprises a printed circuit board 142, a switch driving circuit 143, an inductor 144 and a capacitor 145, wherein the switch driving circuit 143, the inductor 144 and the capacitor 145 are respectively and electrically connected to the printed circuit board 142, the output end of the switch driving circuit 143 is electrically connected with the input end of the inductor 144, the output end of the inductor 144 is electrically connected with the input end of the capacitor 145, and the output end of the capacitor 145 is electrically connected to a power supply pin of the die unit 120.

The power module 140 may be fixedly connected to the package substrate 100 by soldering. The power supply module 140 supplies power to the die unit 120 by: the externally input high-voltage small current, generally about 12 volts or 48 volts, with the current being about tens of amperes, is output to the power supply pin of the die unit 120 through the printed circuit of the power module 140, the switch driving circuit 143, the inductor 144 and the capacitor 145 to supply power to the die unit 120; the supply voltage of the input die unit 120, typically below 1 volt, is several hundred amperes, which can meet the power requirements of the chip.

The switch driving circuit 143 may be an integrated chip, for example, the switch driving chip 1431 and the switch tube 1432 are integrated into one chip, as shown in fig. 6; of course, the switch driving and the switch tube 1432 may be separately disposed, the switch driving chip is disposed outside, and the switch tube 1432 and the switch driving chip are separately disposed on the printed circuit board, as shown in fig. 3.

The switching transistor 1432 may be a MOS (MOSFET, metal Oxide Semiconductor Field Effect Transistor) transistor, or a triode, or other transistor, etc.

In some embodiments, the power module 140 further comprises: and the decoupling capacitor 146 is arranged on a node between the output end of the capacitor 145 and the power supply pin of the die unit 120. In this way, by adding the decoupling capacitor 146 between the output terminal of the power module 140 and the power-using terminal of the die unit 120, as shown in fig. 2, the output electrical signal can be filtered, so as to improve the output power quality, and further prevent the power noise from affecting the performance of the die unit 120.

The decoupling capacitor 146 may be called a filter capacitor 145 depending on the viewing angle of the observer, and has the same nature and function.

The advantages of fan-out packages are described above, and therefore, in some embodiments, the die unit 120 may employ a fan-out package structure.

Because the chip with high-density inter-chip interconnection is adopted, and is usually a high-performance high-power-consumption chip, on one hand, the chip needs low-voltage power supply because of smaller process and low withstand voltage; on the one hand, such chips require large currents due to performance requirements. For this reason, a large low-voltage current is supplied through the external power module 140, and a large amount of power consumption loss is incurred on the link. In the embodiment, in the semiconductor package device adopting the fan-out package structure, by integrating the power module 140 on the package substrate 100, since the link distance between the power module 140 and the die unit 120 is shortened, and the high-voltage low-current power supply from the outside can be realized, the power consumption loss on the transmission link can be effectively reduced.

Among these, in the fan-out packaging technique, there is a low density (or, what is called standard density) in addition to the high density described in the present embodiment; wherein low density generally refers to package types with an I/O count of less than 500, RDL layer linewidths, and pitches greater than 8 μm. The high density is then a package type with an I/O number exceeding 500, RDL layer linewidth and pitch less than 8 μm, and multiple Die can be integrated. Of course, the above-mentioned division is not absolutely constant, and may vary from time to time, for example, depending on the level of the processing conditions, etc.

With continued reference to fig. 1, in particular, the die unit 120 includes: a first die 121 and a second die 122;

the first portion of the first die 121 and the first portion of the second die 122 are electrically connected to the redistribution layer substrate 200, the second portion of the first die 121 and the second portion of the second die 122 are electrically connected to the package substrate 100, the first die 121 and the second die 122 are disposed at intervals, and the first die 121 and the second die 122 are connected through an interconnection line on the redistribution layer substrate 200.

In this embodiment, the base material medium of the redistribution layer substrate may be: the substrate 200 of the re-wiring layer formed by the base material medium is preferably a flexible thin film substrate, and comprises a plurality of medium layers and metal layers which are alternately stacked up and down, wherein the medium layers are formed by Polyimide (PI), benzocyclobutene, a combination thereof or the like, and the metal layers can be formed by silver, copper, nickel, titanium or a combination thereof or the like and are formed by an electroplating process. Wherein, the polyimide film is a film insulating material which is formed by polycondensation, tape casting, film forming and imidization of pyromellitic dianhydride and diamine diphenyl ether in a strong polar solvent. In this embodiment, the PI film is used to manufacture the dielectric layer of the redistribution layer substrate 200, so that the dielectric layer has excellent high temperature resistance, mechanical properties and chemical stability, thereby improving the performance of the semiconductor package device.

Referring to fig. 1, 4 and 5, in some embodiments, the first die 121 and the second die 122 are arranged side by side at intervals, and the first die 121 and the second die 122 are disposed on two sides of a first center line of the redistribution layer substrate 200, where the first center line is a center line of a long side of the redistribution layer substrate 200 when the redistribution layer substrate 200 is rectangular (including square, square is also a special rectangle).

When two different crystal grains are adopted, one part of the two crystal grains are welded on the local high-density interconnection RDL substrate, and the two chips are communicated through the local high-density interconnection RDL substrate; part of the power supply is welded on the packaging substrate 100, and signals and power supplies needing to be led out are led out of the packaging substrate 100 so as to be interconnected with the outside, so that fan-out type packaging is realized.

Of course, in the embodiment of the present utility model, a case of two dies is illustrated, and interconnection of two or more dies may be further provided based on the technical idea of the embodiment of the present utility model.

Although the nature of the fan-out package is not changed, the layout of the redistribution layer substrate may be varied, for example, the redistribution layer substrate may be directly disposed on the upper surface of the package substrate and fully exposed to the package substrate, however, this arrangement may at least make the entire package structure thicker and disadvantageous to the package.

As shown in fig. 1, the redistribution layer substrate may be at least partially embedded on the package substrate, and the top of the redistribution layer substrate is exposed. Therefore, the whole thickness of the packaging structure can be reduced, the size of the packaging structure is small, and the performance is stronger.

Since one of the main functions of the package substrate 100 is to support and position, in order to facilitate the mounting of the die unit 120 and to reduce the thickness of the semiconductor package device, as shown in fig. 7, in some embodiments, the package substrate 100 has at least one accommodating cavity 102, at least one accommodating cavity 102 exposes at least one surface of the package substrate 100, and the redistribution layer substrate 200 is disposed in the accommodating cavity 102 and on the surface.

The redistribution layer substrate 200 is provided with pads (pads, which may also be referred to as contacts) 201 for interconnection with the die units 120 on the upper portion in the vertical direction.

The connecting pad can be a bump, a ball point, a columnar structure or a combination shape structure thereof. Of course, with the development of packaging technology in the future, the pad may also directly remove the bump of the physical entity, and may be almost planar.

In some embodiments, when the power module and the upper support of the die unit are provided with heat dissipation modules, the heat dissipation surfaces of the heat dissipation modules are respectively in contact with the power module 140 and the top of the die unit 120. By providing the heat dissipation module on the top surfaces of the power module 140 and the die unit 120, the semiconductor package device can be entirely heat-dissipated.

It should be understood that, during packaging, the heat dissipation module is generally located outside the package housing, and the heights of the die unit 120 and the power module 140 on the package substrate 100 are not necessarily the same, so that the contact surfaces between the heat dissipation module and the die unit 120 and the contact surfaces between the heat dissipation module and the power module 140 can be stepped, i.e. have a height, so as to achieve contact between the heat dissipation module and the top of the die unit 120, thereby ensuring the heat dissipation effect.

According to the above description, in the semiconductor package device provided by the embodiment of the present utility model, by integrating the power module 140 on the package substrate 100, the power supply link between the power module 140 and the die unit 120 is shortened, and the power can be supplied to the power module 140 by the high-voltage low current, and then the low-voltage high current is supplied to the die unit 120 by the power module 140, so that the power consumption loss on the power supply link is reduced due to the shortened high-current transmission link. Further, since the heat sink is disposed on all or part of the power module 140, the power module 140 replaces the original metal supporting and heat conducting member of the heat sink while realizing the predetermined power supply function, so that only part or no special metal supporting and heat conducting member of the heat sink can be disposed on the package substrate 100, thereby saving the area of the package substrate 100.

Still another embodiment of the present utility model provides a semiconductor packaging method, which can be used for packaging various electronic devices including chips, referring to fig. 8 and 9, the method S200 includes the steps of:

s210, providing a packaging substrate 100 with interconnection wires, and forming a rewiring layer substrate 200 on at least one surface of the packaging substrate 100;

s220, connecting a part of the die unit 120 to the redistribution layer substrate 200, and connecting another part of the die unit to the package substrate 100, specifically, at a second predetermined area b on the package substrate 100 and the redistribution layer substrate 200 in fig. 8; wherein the die unit 120 is located above the redistribution layer substrate 200 and the package substrate 100;

s230, mounting a power module 140 on the surface of the package substrate 100 at a position outside the redistribution layer substrate 200, wherein the power module 140 is located at the periphery of the die unit 120; illustratively, as shown in fig. 8, the power module 140 is mounted on a first predetermined area a on the package substrate 100.

S240, the power module and the die unit 120 are encapsulated by an encapsulation shell.

In some embodiments, the forming the redistribution layer substrate 200 on at least one surface of the package substrate 100 includes:

exposing, developing and etching at least one accommodating cavity on at least one surface of the packaging substrate 100, wherein the bottom surface of at least one accommodating cavity is exposed;

the rerouting layer substrate 200 composed of dielectric layers and metal layers alternately stacked is formed in the accommodating chamber with the bottom surface thereof upward; wherein, each metal layer is mutually coupled, and the dielectric layer is an insulating material.

Specifically, the rerouting layer substrate 200 formed by alternately stacking dielectric layers and metal layers in the accommodating cavity and formed by upward forming on the bottom surface thereof includes;

forming a rewiring layer substrate 200 with interconnection wires on a base material medium embedded in the cavity by adopting a double-sided coating; the base material medium comprises the medium layer and a metal layer;

copper pillars and solder balls are electroplated on the upper surface of the redistribution layer substrate 200 to form conductive bumps for interconnection with the die units 120.

In some embodiments, attaching a portion of die unit 120 to the redistribution layer substrate 200 and another portion of the die unit to the package substrate 100 includes: the die unit 120 is attached to the redistribution layer substrate 200 and the package substrate 100 in a flip-chip manner, and the signal leads and the power leads of the die unit 120 are led out of the package substrate 100.

Referring to fig. 1 again, the die unit 120 includes at least a first die 121 and a second die 122;

connecting a portion of die unit 120 to the redistribution layer substrate 200 and connecting another portion of the die unit to the package substrate 100 includes: connecting the metal bonding surface of the first die 121 to the first side region m of the upper surfaces of the package substrate 100 and the redistribution layer substrate 200, and connecting the metal bonding surface of the second die 122 to the second side region n of the upper surfaces of the package substrate 100 and the redistribution layer substrate 200; when the redistribution layer substrate 200 is in an axisymmetric pattern, the first side region m and the second side region n are symmetric about the symmetry axis of the redistribution layer substrate 200.

The axisymmetric pattern includes: square and rectangular.

Referring again to fig. 8, in some embodiments, a semiconductor packaging method is provided, comprising:

s110, a first preset area a and a second preset area b are arranged on the packaging substrate 100 with the interconnection wires; wherein the first predetermined area a and the second predetermined area b are connected by the interconnection wire.

The package substrate 100 may be processed by feeding materials or purchasing finished materials, and the package substrate 100 adopts an ABF substrate. In order to realize the packaging of the semiconductor device, it is necessary to provide a region for mounting the power module 140, i.e., a first predetermined region a, on the package substrate 100 according to design requirements; and, an area for accommodating the die unit 120, i.e., a second predetermined area b, is provided.

The conductive bump (also referred to as bump) is disposed at least in the first predetermined area a, and may be formed by electroplating copper pillars and solder balls, where the pitch of the copper pillars in the first predetermined area a may be about 130um and the diameter of the copper pillars may be about 70 um. The first predetermined area a may also be pre-coated with solder paste to assist in the soldering process. The second predetermined area b may be provided with different connection structures according to the packaging manners of the die units 120. For example, if the package is surface-mounted, the conductive bumps may be disposed to be connected by solder bonding, similar to the processing of the first predetermined area a.

In the embodiment shown in fig. 8, at least one of the first predetermined areas may be provided, but of course, two or more may be provided according to the number of power modules, as shown in fig. 9.

With continued reference to fig. 1, in some embodiments, the die unit 120 is assembled in a fan-out package structure, and the second predetermined area b is provided with a portion of the conductive bumps.

S120, connecting the power module 140 to the first predetermined area a, and correspondingly connecting the die unit 120 to the second predetermined area b.

In some embodiments, the connecting the power module 140 to the first predetermined area a and the die unit 120 to the second predetermined area b correspondingly includes: forming a first conductive bump in a first predetermined region a on the package substrate 100, and forming a second conductive bump in a second predetermined region b on the package substrate 100; the power module 140 is correspondingly connected to the package substrate 100 through the first conductive bump, and the die unit 120 is correspondingly connected to the package substrate 100 through the second conductive bump.

The first conductive bump and the second conductive bump may be formed by electroplating copper pillars and solder balls on the surface of the package substrate 100.

S130, encapsulating the power module 140 and the die unit 120 with an encapsulation housing.

The power module 140 and the die unit 120 may be packaged separately or together. In addition to the basic power supply function, at least one power supply module 140 is used for supporting and installing the heat dissipation module above the power supply module 140 when the external heat dissipation module is installed. In this way, not only the substrate area required for supporting the heat conducting member can be saved, but also the heat dissipation module can dissipate heat for the power module 140 in turn, without providing an additional heat sink, and the configuration cost of the heat dissipation module can be reduced.

In order to improve the heat dissipation performance of the semiconductor package device, in some embodiments, the surface of the package case may be partially provided with a metal region to improve the heat dissipation effect thereof as much as possible without shorting the internal circuit.

Of course, the package case may be made of plexiglass or the like.

With continued reference to fig. 7 and 8, the forming the second conductive bump in the second predetermined area b on the package substrate 100 includes: forming a containing cavity in a second preset area b of the packaging substrate 100 through exposure, development and etching; forming a rewiring layer substrate 200 with interconnection wires on a base material medium embedded in the cavity by adopting a double-sided coating; copper pillars and solder balls are electroplated on the upper surface of the redistribution layer substrate 200 to form the conductive bumps.

In this embodiment, a high-precision accommodating cavity is formed on the package substrate 100 by exposure, development and etching, and is used for disposing a redistribution layer (RDL) therein, polyimide is embedded in the cavity through a double-sided coating as a dielectric layer, so as to form a RDL FANOUT local high-density interconnection substrate, that is, a redistribution layer substrate 200, and copper pillars and solder balls are electroplated on the upper surface of the redistribution layer substrate 200, so as to form conductive bumps for interconnection in the vertical direction. The double-sided film may be adhered to the bottom surface of the cavity and the lower surface of the redistribution layer substrate 200 by means of an adhesive film.

Welding part of two different crystal grains (Die) on the local high-density interconnection substrate in a flip-chip welding mode, wherein the two crystal grains are communicated through the local high-density interconnection substrate; a part of the lead-out wires are soldered on the package substrate 100, and the signals and the power to be led out are led out of the package substrate 100 to be interconnected with the outside.

In some embodiments, the redistribution layer substrate 200 is formed in the accommodating cavity on the package substrate 100, and the upper surface of the redistribution layer substrate 200 is electrically connected to the first die 121 mounted in a flip-chip manner, and the lower surface of the redistribution layer substrate 200 is electrically connected to the through-silicon via TSV on the package substrate 100. The rerouting layer substrate 200 may include a plurality of dielectric layers and a plurality of metal layers alternately stacked. The embodiment of the utility model does not limit the number of the dielectric layers or the metal layers, and can be set according to the needs.

Specifically, the dielectric layers and the metal layers are alternately arranged, and different metal layers are interconnected up and down and pass through the dielectric layers, and in some embodiments, the lower surface of the redistribution layer substrate 200 is provided with conductive bumps for electrically connecting to through-silicon vias of the package substrate 100.

Copper pillars and solder balls are soldered on a metal layer on Top of the redistribution layer (Top) for solder mounting. The dielectric layer may be formed of polyimide, benzocyclobutene, a combination thereof or the like, and preferably the base material dielectric layer is polyimide. The metal layer may be formed using silver, copper, nickel, titanium, a combination thereof, or the like, and may be formed specifically by an electroplating process.

In some embodiments, the first conductive bump and the second conductive bump may be made of a conductive material with low resistance, such as tin, lead, silver, nickel, bismuth or alloys thereof, and may be formed by a suitable process, such as evaporation, electroplating, ball drop (ball drop), screen printing, or the like, in addition to the copper pillars.

In some embodiments, the correspondingly connecting the die unit 120 to the package substrate 100 through the second conductive bump includes: the die unit 120 is attached to the second conductive block in a flip-chip manner, so as to implement circuit interconnection with the package substrate 100.

In the flip-chip process, soldering flux may be sprayed or coated on the package substrate 100 and the redistribution layer substrate 200, and the flip-chip device is used to flip-chip a part of the active surface of the die down onto the package substrate 100 and a part of the die down onto the redistribution layer substrate 200; reflow soldering is performed on the connection points of the package substrate 100 and the rewiring layer substrate 200 and the die unit 120 respectively; then, cleaning the package substrate 100, the re-wiring layer substrate 200 and the die unit 120; finally, a plastic packaging process can be adopted, and after solidification, the packaging shell is formed.

In some embodiments, the pitch of two adjacent first conductive bumps is 120-140 μm, and the diameter of the first conductive bumps is 50-85 μm; and/or, the pitch of two adjacent second conductive bumps is 40-60 μm, and the diameter of each second conductive bump is 10-40 μm.

In addition, the power module 140 may be produced in a foundry, or may be directly purchased as a semi-finished product or a finished product, and manufactured by itself. Referring to fig. 10, in some embodiments, during the packaging process, the power module 140 is also prepared in parallel, which includes the following specific steps: preparing a printed wiring board 142 of the power module 140, on which an input terminal 147, a wire, a ground point 148, an output terminal 149 are prepared; after the preparation of the printed circuit board 142 of the power module 140 is completed, the switch driving circuit 143, the inductor 144, the capacitor 145, and the like are soldered on the printed circuit board 142 of the power module 140 according to a circuit topology.

After the power module 140 is soldered to the printed circuit board 142 and the corresponding devices, the whole package is performed, and gold plating is performed on the upper surface (the surface contacting with the external heat dissipation module), which may be other metals, so as to facilitate heat dissipation. Referring to fig. 10, if a plurality of power modules 140 are prepared on a large printed circuit board at a time, the power modules 140 are cut into individual pieces after the preparation is completed, thereby forming a single power module 140.

Finally, the die unit 120 and the power module 140 are soldered at the corresponding positions of the package substrate 100 and the redistribution layer substrate 200, wherein the die unit 120 corresponds to the package substrate 100 and the redistribution layer substrate 200, and is also copper pillars and solder balls with two pitches, the pitch of the copper pillars is about 130um and the diameter is about 70um in the area corresponding to the package substrate 100; the pitch of copper pillars 302 of the redistribution layer substrate 200 is about 50um, the diameter is about 25um, and the heights are uniform. After the soldering is completed, the power module 140 may supply power to the die unit 120 through the package substrate 100.

On the one hand, on the basis of Fan-Out packaging, the semiconductor device provided by the embodiment of the utility model has the advantages that the power module 140 is arranged on the packaging substrate 100, power is supplied to the power module 140 through high-voltage small current, and then low-voltage large current is supplied to the chip through the power module 140, so that a large-current transmission path can be reduced, and the power loss on the transmission path is reduced; on the other hand, by replacing the power module 140 with the supporting and heat dissipating function of the supporting and heat-conducting member such as the heat dissipating ring, the occupation of the additional package substrate 100 area can be avoided; further, while supporting the radiator, the radiator is also utilized to radiate heat of the switching tube chip and the inductor 144 of the power module 140, so that the radiator of devices such as additional switching tube chips is avoided, and the cost is reduced.

Further, by embedding a low-cost RDL fan out substrate (re-wiring layer fan out substrate) in the accommodating cavity formed on the package substrate 100, a RDL layer layout scheme of a specific form of fan-out package structure is provided, and the embedded fan-out package structure is realized, so that high-density inter-die interconnection can be completed at a lower cost, the thickness of the whole package device is reduced, and the performance of the semiconductor package device is improved.

One or more of the embodiments are described by way of reference or cross-reference to one another.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and the same or similar parts of each embodiment are referred to each other, where each embodiment mainly describes differences from other embodiments.

The foregoing is merely illustrative of the present utility model, and the present utility model is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present utility model should be included in the present utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.

Claims (13)

1. A semiconductor package device, comprising: packaging a substrate; the packaging substrate is provided with an interconnection wire;

a rewiring layer substrate; the rewiring layer substrate is arranged on the packaging substrate;

a die unit; a part of the die unit is connected to the rewiring layer substrate, and the other part of the die unit is connected to the packaging substrate;

a power module; the power module is positioned at the periphery of the grain unit and is electrically connected with the grain unit through the interconnection wire.

2. The semiconductor package according to claim 1, wherein at least one of the power modules is provided with a heat dissipation module.

3. The semiconductor package device according to claim 1, wherein the power supply module comprises: and the power supply circuit is packaged in the shell.

4. A semiconductor package according to claim 3, wherein the power supply module is provided with one or more.

5. The semiconductor package device according to claim 2, wherein the power supply module includes: the circuit comprises a printed circuit board, a switch driving circuit, an inductor and a capacitor, wherein the switch driving circuit, the inductor and the capacitor are respectively and electrically connected to the printed circuit board, the output end of the switch driving circuit is electrically connected with the input end of the inductor, the output end of the inductor is electrically connected with the input end of the capacitor, and the output end of the capacitor is electrically connected to a power supply pin of the grain unit.

6. The semiconductor package device according to claim 4, wherein the power module further comprises: and the decoupling capacitor is arranged on a node between the output end of the capacitor and the power supply pin of the grain unit.

7. The semiconductor package device according to claim 3 or 4, wherein a metal layer is plated on at least a surface of the housing of the power module external package corresponding to the heat sink.

8. The semiconductor package device according to claim 1, wherein the die unit includes: a first die and a second die;

the first part of the first crystal grain and the first part of the second crystal grain are respectively and electrically connected to the rewiring layer substrate, the second part of the first crystal grain and the second part of the second crystal grain are respectively and electrically connected to the packaging substrate, the first crystal grain and the second crystal grain are arranged at intervals, and the first crystal grain and the second crystal grain are connected through an interconnection line on the rewiring layer substrate.

9. The semiconductor package according to claim 8, wherein the first die and the second die are arranged side by side with a spacing therebetween, and the first die and the second die are disposed on both sides of a first center line of the rerouting layer substrate, the first center line being a center line of a long side of the rerouting layer substrate when the rerouting layer substrate is rectangular.

10. The semiconductor package according to claim 1 or 8, wherein the redistribution layer substrate has at least a portion of its structure embedded on the package substrate, and a top portion of the redistribution layer substrate is exposed.

11. The semiconductor package according to claim 10, wherein the package substrate has at least one receiving cavity, at least one of the receiving cavities exposing at least one surface of the package substrate, the redistribution layer substrate being disposed within the receiving cavity and on the surface.

12. The semiconductor package according to claim 1, wherein when the heat dissipation module is installed on the upper support of the power module and the die unit, the heat dissipation surfaces of the heat dissipation module are respectively in contact with the tops of the power module and the die unit.

13. The semiconductor package device according to claim 1, wherein the semiconductor package device is a chip.

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