CN219122579U - High-count-rate time-to-digital converter applied to single-photon laser radar - Google Patents
High-count-rate time-to-digital converter applied to single-photon laser radar Download PDFInfo
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Abstract
The utility model provides a high count rate time-to-digital converter for single photon laser radar application, comprising: the storage module is used for storing a time distribution histogram of the laser radar echo signals, wherein the address of the storage module corresponds to photon flight time, and the data of the storage module represents photon total count; the accumulation module is used for reading photon counting data in a certain counted time interval, adding the number of the photon signals newly arrived in the period to the photon counting data in a certain time interval to obtain a new photon total count, and writing the new photon total count back to the storage module; an address generation module for outputting memory address values corresponding to time intervals in the time distribution histogram during operation of the time-to-digital converter.
Description
Technical Field
The utility model belongs to the technical field of time-to-digital conversion, and particularly relates to a high-count-rate time-to-digital converter based on a field programmable gate array applied to single-photon laser radar.
Background
The single-photon laser radar has wide application prospect in the fields of environmental monitoring, atmosphere remote sensing, three-dimensional imaging and the like. The echo signal intensity of the lidar is affected by an exponential decay term of atmospheric dissipation while being inversely proportional to the square of the detection distance, and thus has a very large dynamic range. The multichannel single photon detector can not only effectively receive weak echo signals at the far field, but also increase the saturation count rate of a receiving system and avoid signal distortion at the near field. The large number of detection signals generated by the multi-channel detector also presents a significant challenge for the acquisition and transmission of photon time-of-flight information.
The single-photon laser radar extracts effective information from a statistical histogram of the arrival time of the detection signals, and is insensitive to the arrival time of the single detection signals. The universal Time-to-digital Converter (TDC) needs to output the Time information of each detection event, and when the count rate of the signal is high, massive redundant data will be generated, which consumes longer transmission Time, and reduces the working efficiency of the lidar, thereby limiting the expansion of the lidar receiving system to more channels.
Disclosure of Invention
In view of the foregoing, the present utility model provides a high count rate time-to-digital converter for single photon lidar applications, in order to solve at least one of the foregoing problems.
According to an embodiment of the present utility model, there is provided a high count rate time-to-digital converter for single photon lidar applications, comprising:
the storage module is used for storing a time distribution histogram of the laser radar echo signals, wherein the address of the storage module corresponds to photon flight time, and the data of the storage module represents photon total count;
the accumulation module is used for reading photon counting data in a certain counted time interval, adding the number of the photon signals newly arrived in the period to the photon counting data in a certain time interval to obtain a new photon total count, and writing the new photon total count back to the storage module;
an address generation module for outputting memory address values corresponding to time intervals in the time distribution histogram during operation of the time-to-digital converter.
According to an embodiment of the present utility model, the memory module uses an on-chip memory of a field programmable gate array;
the storage module can store photon total counts in a plurality of continuous time intervals in the time distribution histogram in each address, so that the photon count data in the plurality of time intervals can be updated by one-time read-write operation of the storage module.
According to an embodiment of the present utility model, the accumulation module includes a first adder, a second adder, and a plurality of channel shapers.
According to an embodiment of the present utility model, the channel shaper is configured to process a received probe signal and output a shaped signal;
wherein, the channel shaper is used for processing the received detection signal and outputting the shaped signal, and comprises:
the channel shaper receives the detection signal and initializes the shaped signal to a low level;
the channel shaper changes the low level to the high level at the first clock falling edge after the corresponding rising edge of the detection signal;
the channel shaper changes the high level back to the low level at the second clock falling edge after the corresponding rising edge of the detection signal;
the channel shaper outputs the shaped signal.
According to an embodiment of the present utility model, the first adder receives the shaped signal and calculates a total count newly added in the current address i of the memory module at a rising edge of each clock;
the second adder reads out the data in the current address i of the memory module at the rising edge of the 4 x i+3 clocks, calculates new data at the falling edge of the 4 x i+3 clocks, and writes back the new data into the memory module at the rising edge of the 4 x i+4 clocks, wherein i is a positive integer.
According to an embodiment of the present utility model, the address generation module includes a frequency divider, a counter, and a timer.
According to an embodiment of the present utility model, the frequency divider is configured to divide a clock;
the counter is used for counting the frequency-divided clock and taking the counting result as the address of the storage module.
According to the embodiment of the utility model, the timer outputs a high level when the high count rate time-to-digital converter starts to collect and outputs a low level after the collection time set by the upper computer is maintained;
the output of the timer and the reference signal are subjected to AND operation to obtain a controlled reference signal;
the count value of the counter is reset to a preset value when the rising edge of the controlled reference signal arrives.
According to the embodiment of the utility model, the clock frequency of the accumulation module is set according to the time measurement resolution of the laser radar system by the accumulation module;
wherein the clock frequency of the address generator is the same as the clock frequency of the accumulation module.
According to an embodiment of the present utility model, there is provided a control method of a high count rate time-to-digital converter applied to a single photon lidar, which is applied to the high count rate time-to-digital converter, including:
according to a setting instruction of an upper computer, setting the acquisition time of the field programmable gate array through a high-count-rate time-to-digital converter;
under the condition that a field programmable gate array of the high-count-rate time-to-digital converter receives a starting instruction of an upper computer, resetting data in a storage module through the high-count-rate time-to-digital converter;
under the condition that the data clearing of the storage module of the high-count-rate time-to-digital converter is completed, the high-count-rate time-to-digital converter commands the counter to start working, and the address output by the counter of the high-count-rate time-to-digital converter is cleared according to an externally input reference signal;
the address output by the counter of the high-count-rate time-to-digital converter is increased along with time, and the latest time distribution histogram data is updated and written into the storage module in real time by the high-count-rate time-to-digital converter by utilizing the accumulation module;
according to the acquisition time set by the field programmable gate array, under the condition that the high-count-rate time-to-digital converter outputs a low level by using the timer, the output address value of the counter is not cleared by the high-count-rate time-to-digital converter, the output address value of the counter is maintained at a preset maximum value, and the data in the preset address range of the storage module is kept unchanged;
the high count rate time-to-digital converter reads out the data in the preset address range of the memory module in sequence and draws a new time distribution histogram.
According to the utility model, the time distribution histogram is counted in real time in the field programmable gate array, so that the transmission of a large amount of redundant information is avoided, the counting rate is greatly improved, the data transmission time is reduced, and the multichannel expansion of the single-photon laser radar is facilitated.
Drawings
FIG. 1 is a logic diagram of a high count rate time-to-digital converter according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of an accumulation module according to an embodiment of the utility model;
FIG. 3 is a schematic diagram of an address generation module according to an embodiment of the utility model;
fig. 4 is a flowchart of a control method of the high count rate time-to-digital converter according to an embodiment of the present utility model.
FIG. 5 is a key signal timing diagram of a high count rate time-to-digital converter according to an embodiment of the present utility model;
reference numerals illustrate:
the device comprises a storage module 11, an accumulation module 12, an address generation module 13, a shaper 121, a first adder 122, a second adder 123, a frequency divider 131, a timer 132 and a counter 133.
Detailed Description
The present utility model will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present utility model more apparent.
FIG. 1 is a logic diagram of a high count rate time-to-digital converter according to an embodiment of the present utility model;
as shown in fig. 1, the high count rate time-to-digital converter for single photon lidar application provided by the present utility model includes a storage module 11, an accumulation module 12, and an address generation module 13.
And the storage module 11 is used for storing a time distribution histogram of the laser radar echo signals, wherein the address of the storage module corresponds to photon flight time, and the data of the storage module represents photon total count.
The accumulation module 12 is configured to read out photon count data in a counted certain time interval, add the number of photon signals newly arrived in the present period to the photon count data in a certain time interval, obtain a new total photon count, and write the new total photon count back to the storage module.
An address generation module 13 for outputting memory address values corresponding to time intervals in the time distribution histogram during operation of the time-to-digital converter.
The high-count-rate time-to-digital converter applied to the single-photon laser radar and based on the field programmable gate array can realize real-time statistics of a time distribution histogram in an FPGA chip, avoid transmission of a large amount of redundant information and improve the working efficiency of the single-photon laser radar; meanwhile, multichannel single photon detection signals with extremely high total count rate can be accurately collected, and multichannel expansion of a single photon laser radar receiving end is facilitated.
Meanwhile, the utility model discloses a method for realizing the high-count-rate time-to-digital converter based on the field programmable gate array, which can meet the application requirements of the multichannel single-photon laser radar. The method comprises a storage module, an accumulation module and an address generation module. Wherein the storage module is used for storing a time distribution histogram of the signal; the accumulation module is responsible for reading out signal count data of n channels (channel shapers) in a designated time and updating the data of the storage module in real time; and the address generation module outputs the address value of the storage module corresponding to the time interval in the time distribution histogram. According to the utility model, the time distribution histogram is counted in real time in the field programmable gate array, so that the transmission of a large amount of redundant information is avoided, the counting rate is greatly improved, the data transmission time is reduced, and the multichannel expansion of the single-photon laser radar is facilitated.
According to an embodiment of the present utility model, the memory module uses an on-chip memory of a field programmable gate array.
The total photon count in a plurality of continuous time intervals in the time distribution histogram can be stored in each address of the storage module, so that the photon count data in a plurality of time intervals can be updated by one-time read-write operation of the storage module.
For example, the address i of the memory module may store the total photon count { C over k consecutive time intervals in the time distribution histogram k*i ,C k*i+1 ,…,C k*i+k-1 And enabling one read-write operation of the memory to update photon count data in a plurality of time intervals, wherein C represents the current total photon number, k is a positive integer book, and i is an integer greater than or equal to 0.
Fig. 2 is a schematic diagram of an accumulation module according to an embodiment of the utility model.
As shown in fig. 2, the accumulation module includes a first adder 122, a second adder 123, and a plurality of channel shapers 121.
According to an embodiment of the present utility model, the channel shaper is configured to process a received probe signal and output a shaped signal.
The channel shaper is configured to process a received probe signal and output a shaped signal, including:
the channel shaper receives the probe signal and initializes the shaped signal to a low level.
The channel shaper changes the low level to the high level on the first clock falling edge after the corresponding rising edge of the probe signal.
The channel shaper changes the high level back to the low level on the second clock falling edge after the corresponding rising edge of the probe signal.
The channel shaper outputs the shaped signal.
According to an embodiment of the present utility model, the first adder receives the shaped signal and calculates a total count of new additions in the current address i of the memory module at a rising edge of each clock.
The second adder reads out the data in the current address i of the memory module at the rising edge of the 4 x i+3 clocks, calculates new data at the falling edge of the 4 x i+3 clocks, and writes back the new data into the memory module at the rising edge of the 4 x i+4 clocks, wherein i is a positive integer.
The accumulation module firstly shapes the n-channel detection signals, the n-channel shaped signals are initially low-level, the first clock falling edge after the corresponding detection signal rising edge is changed to high-level, and the second clock falling edge after the corresponding detection signal rising edge is changed back to low-level. For the shaped signal, the current newly added total count { N ] is calculated at the rising edge of each clock k*i ,N k*i+1 ,…,N k*i+k-1 Reading data { C in the current address of the memory at the kth positive i+k-1 clock rising edge k*i ,C k*i+1 ,…,C k*i+k-1 New data { N } is calculated on the kth clock falling edge of i+k-1 k*i +C k*i ,N k*i +1+C k*i+1 ,…,N k*i+k-1 +C k*i+k-1 Writing new data back into the memory at the kth clock rising edge, wherein N represents the number of photons newly added, n+c represents the number of photons new, and N and k are both positive integers.
Fig. 3 is a schematic diagram of an address generation module according to an embodiment of the utility model.
As shown in fig. 3, the above-described address generation module includes a frequency divider 131, a timer 132, and a counter 133.
According to an embodiment of the present utility model, the frequency divider 131 is configured to divide a clock.
The counter 133 is configured to count the divided clock and use the count result as the address of the memory module.
According to the embodiment of the utility model, the timer outputs a high level when the high count rate time-to-digital converter starts collecting, and outputs a low level after maintaining the collecting time set by the upper computer.
The output of the timer is AND-operated with the reference signal to obtain a controlled reference signal.
The count value of the counter is reset to a preset value when the rising edge of the controlled reference signal arrives.
According to an embodiment of the present utility model, the address generation module includes a frequency divider, a counter, and a timer. The frequency divider divides the clock by k, and the counter counts the divided clock as the address of the memory. The counting is stopped when the count reaches the set maximum value P. By controlling the phase of the frequency division clock, the address of the accumulation module is kept unchanged in two clocks for reading out old data and writing new data. The timer outputs high level when the TDC starts to collect, and outputs low level after the collection time T set by the upper computer is maintained. The output of the timer is AND-operated with the reference signal to obtain a controlled reference signal. The count value of the counter is reset to 0 when the rising edge of the controlled reference signal arrives.
The frequency divider divides the clock by k, and the counter counts the divided clock as the address of the memory. The counting is stopped when the count reaches the set maximum value P. By controlling the phase of the frequency division clock, the address of the accumulation module is kept unchanged in two clocks for reading out old data and writing new data. The timer outputs high level when the TDC starts to collect, and outputs low level after the collection time T set by the upper computer is maintained. The output of the timer is AND-operated with the reference signal to obtain a controlled reference signal. The count value of the counter is reset to 0 when the rising edge of the controlled reference signal arrives.
According to the embodiment of the utility model, the clock frequency of the accumulation module is set according to the time measurement resolution of the laser radar system.
The clock frequency of the address generator is the same as the clock frequency of the accumulation module.
Fig. 4 is a flowchart of a control method of the high count rate time-to-digital converter according to an embodiment of the present utility model.
As shown in fig. 4, the control method of the high count rate time-to-digital converter for single photon lidar application includes operations S410 to S460.
In operation S410, according to the setting instruction of the upper computer, setting the acquisition time of the field programmable gate array through the high count rate time-to-digital converter;
in operation S420, under the condition that the field programmable gate array of the high-count-rate time-to-digital converter receives the start instruction of the upper computer, resetting the data in the storage module through the high-count-rate time-to-digital converter;
in operation S430, when the clearing of the data of the memory module of the high-count-rate time-to-digital converter is completed, the high-count-rate time-to-digital converter commands the counter to start working, and clears the address output by the counter of the high-count-rate time-to-digital converter according to the externally input reference signal;
in operation S440, the address output by the counter of the high count rate time-to-digital converter is incremented with time, and the latest time distribution histogram data is updated and written into the storage module in real time by the high count rate time-to-digital converter by using the accumulation module;
in operation S450, according to the acquisition time set by the field programmable gate array, under the condition that the high count rate time-to-digital converter outputs a low level by using the timer, the output address value of the counter is not cleared by the high count rate time-to-digital converter, the output address value of the counter is maintained at the preset maximum value, and the data in the preset address range of the storage module is kept unchanged;
in operation S460, the high count rate time-to-digital converter sequentially reads out data in a preset address range of the memory module and draws a new time distribution histogram.
FIG. 5 is a key signal timing diagram of a high count rate time-to-digital converter according to an embodiment of the present utility model.
The above-described apparatus and method provided by the present utility model are described in further detail below in conjunction with fig. 5.
As shown in fig. 5, a. Cycle starts; b. reading out the data in the memory address i; c. calculating a new total count; d. the new total count is written back to memory address i and the next cycle begins.
Consider a single-photon lidar system in which a 16-channel superconducting nanowire single-photon detector (Superconducting Nanowire Single Photon Detector, SNSPD) is used at the receiving end, the time measurement resolution is 20ns, the laser pulse repetition frequency is 10kHz, and 5000 time intervals are provided for the horizontal axis of the time distribution histogram.
As shown in fig. 1, the following modules are built into the FPGA: the storage module is used for storing a time distribution histogram of the laser radar echo signals by using an on-chip memory of the FPGA, each address stores data in k=4 time intervals, and photon counting in each time interval is stored by using 32bit data; the accumulation module is used for reading out photon counting data in a certain counted time interval, adding the number of photon counting newly arrived in the period to obtain new total photon signal counting and writing the new total photon signal counting back into the memory; the address generation module outputs memory address values corresponding to time intervals in the time distribution histogram during TDC operation.
As shown in fig. 2, the clock frequency of the accumulation module is set to 50MHz, corresponding to 20ns time measurement resolution of the lidar system. The probe signal of the SNSPD is first connected to the shaper 121, the initial signal output by the shaper 121 is at a low level, the first clock falling edge after the corresponding probe signal rising edge changes to a high level, and the second clock falling edge after the corresponding probe signal rising edge changes back to a low level. For the shaped signal, adder 122 calculates the newly added total count { N } within the current memory address i at each rising edge of the clock 4*i ,N 4*i+1 ,N 4*i+2 ,N 4*i+3 }. Adder 123 reads data { C } in the current address of the memory at the 4 x i+3 clock rising edge 4*i ,C 4*i+1 ,C 4*i+2 ,C 4*i+3 New data { N } is calculated on the 4 x i+3 clock falling edge 4*i +C 4*i ,N 4*i+1 +C 4*i+1 ,N 4*i+2 +C 4*i+2 ,N 4*i+3 +C 4*i+3 New data is written back into memory on the 4 x i +4 clock rising edge.
As shown in fig. 3, the input clock 0 of the address generation module uses the same 50MHz clock as the accumulation module. Clock 0 is divided and phase shifted by divider 4 131 to obtain clock 1 at 12.5 MHz. The counter 133 counts the clock 1, and the counted value is output as an address value of the memory module. When the counter reaches the set maximum value 1250, the counting is stopped and the output remains unchanged 1250. The timer 132 outputs a high level when the TDC starts to collect and outputs a low level after maintaining the collection time T set by the upper computer. The output of the timer 132 is anded with the reference signal to obtain a controlled reference signal. The count value of the counter is reset to 0 when the rising edge of the controlled reference signal arrives.
For ease of understanding, a timing diagram of several key signals in this embodiment is listed in fig. 5.
In the embodiment of the utility model, the working flow of the TDC is as follows:
the upper computer sets acquisition time T to the FPGA and sends a start instruction; after receiving the starting instruction, the FPGA clears the data in the memory 11; after the data of the memory 11 is cleared, the timer 132 starts to work, the externally input reference signal periodically clears the address output by the counter 133, then the address is increased with time, and the accumulation module 12 updates the latest histogram data into the memory in real time; the timer 132 outputs a low level after reaching the acquisition time T, the address value output by the counter 133 is no longer cleared, maintained at the maximum value 1250, and the data in the memory address 0 through address 1249 are no longer changed; the data in memory addresses 0 through 1249 are sequentially read out, and a time distribution histogram is drawn.
In the embodiment of the utility model, the maximum counting rate of SNSPD per channel is about 50Mcps, and the maximum counting rate can reach 800Mcps. If a general purpose TDC is used, the time information for each detected event uses 16bit data storage, then at most 12.8Gbit data per second will be generated, which is difficult to transmit and process in real time. By using the method of the utility model, the time distribution data of the detection signals can be counted in the FPGA in real time, the data quantity is only 160Kbit, and the speed of laser radar data transmission and processing is greatly improved. The data volume generated by the method disclosed by the utility model is irrelevant to the channel number of the single photon detector, and is beneficial to the expansion of the single photon laser radar to more channels.
Those skilled in the art will appreciate that the features recited in the various embodiments of the utility model and/or in the claims may be combined in various combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the utility model. In particular, the features recited in the various embodiments of the utility model and/or in the claims can be combined in various combinations and/or combinations without departing from the spirit and teachings of the utility model. All such combinations and/or combinations fall within the scope of the utility model.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the utility model, and is not meant to limit the utility model thereto, but to limit the utility model thereto, and any modifications, equivalents, improvements and equivalents thereof may be made without departing from the spirit and principles of the utility model.
Claims (5)
1. A high count rate time-to-digital converter for single photon lidar applications, implemented based on a field programmable gate array FPGA chip, the digital converter comprising:
the storage module is used for storing a time distribution histogram of the laser radar echo signals, wherein the address of the storage module corresponds to photon flight time, and the data of the storage module represents photon total count;
the accumulation module is used for reading photon counting data in a certain counted time interval, adding the number of the photon signals newly arrived in the period to the photon counting data in the certain time interval to obtain a new photon total count, and writing the new photon total count back to the storage module;
an address generation module for outputting memory address values corresponding to time intervals in the time distribution histogram during operation of the time-to-digital converter;
the storage module is respectively connected with the accumulation module and the address generation module;
wherein the accumulation module comprises a first adder, a second adder and a plurality of channel shapers;
the address generation module comprises a frequency divider, a counter and a timer.
2. The high count rate time to digital converter for single photon lidar applications of claim 1, wherein the memory module uses on-chip memory of a field programmable gate array;
and each address of the storage module can store photon total counts in a plurality of continuous time intervals in the time distribution histogram, so that the photon count data in the plurality of time intervals can be updated by one-time read-write operation of the storage module.
3. The high count rate time to digital converter for single photon lidar applications of claim 1, wherein the divider is configured to divide a clock;
the counter is used for counting the clock after frequency division and taking the counting result as the address of the storage module.
4. The high count rate time-to-digital converter for single photon lidar applications of claim 1, wherein the timer outputs a high level when the high count rate time-to-digital converter begins acquisition and outputs a low level after maintaining an acquisition time set by the host computer;
the output of the timer is AND-operated with the reference signal to obtain a controlled reference signal;
the count value of the counter is reset to a preset value when the rising edge of the controlled reference signal arrives.
5. The high count rate time to digital converter for single photon lidar applications of any of claims 1-4, wherein the accumulation module sets a clock frequency of the accumulation module based on a time measurement resolution of the lidar system;
the clock frequency of the address generation module is the same as that of the accumulation module.
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